1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #include <linux/delay.h>
5 #include <linux/iopoll.h>
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9
10 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
11 DPLL_PIN_FREQUENCY_1PPS,
12 DPLL_PIN_FREQUENCY_10MHZ,
13 };
14
15 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
16 DPLL_PIN_FREQUENCY_1PPS,
17 };
18
19 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
20 DPLL_PIN_FREQUENCY_10MHZ,
21 };
22
23 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
25 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
30 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
31 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
32 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
33 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
35 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
36 };
37
38 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
40 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
45 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
47 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
48 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
49 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
51 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
52 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
53 };
54
55 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
56 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
57 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
58 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
59 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
60 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
61 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
62 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
63 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
64 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
65 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
66 };
67
68 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
69 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
70 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
71 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
72 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
73 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
74 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
75 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
77 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
78 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
79 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
80 };
81
82 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
83 { "NONE", SI_REF0P, 0, 0 },
84 { "NONE", SI_REF0N, 0, 0 },
85 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
86 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
87 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
88 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
89 { "NONE", SI_REF2N, 0, 0 },
90 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
92 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
93 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
94 };
95
96 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
97 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
98 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
99 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
100 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
101 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
102 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
103 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
104 };
105
106 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
107 { "NONE", ZL_REF0P, 0, 0 },
108 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
109 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
110 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
111 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
112 { "NONE", ZL_REF2P, 0, 0 },
113 { "NONE", ZL_REF2N, 0, 0 },
114 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
115 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
116 { "NONE", ZL_REF3N, 0, 0 },
117 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
118 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
119 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
120 };
121
122 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
123 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
124 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
125 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
126 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
127 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
128 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
129 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
130 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
131 { "NONE", ZL_OUT5, 0, 0 },
132 };
133
134 /* Low level functions for interacting with and managing the device clock used
135 * for the Precision Time Protocol.
136 *
137 * The ice hardware represents the current time using three registers:
138 *
139 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
140 * +---------------+ +---------------+ +---------------+
141 * | 32 bits | | 32 bits | | 32 bits |
142 * +---------------+ +---------------+ +---------------+
143 *
144 * The registers are incremented every clock tick using a 40bit increment
145 * value defined over two registers:
146 *
147 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
148 * +---------------+ +---------------+
149 * | 8 bit s | | 32 bits |
150 * +---------------+ +---------------+
151 *
152 * The increment value is added to the GLTSYN_TIME_R and GLTSYN_TIME_L
153 * registers every clock source tick. Depending on the specific device
154 * configuration, the clock source frequency could be one of a number of
155 * values.
156 *
157 * For E810 devices, the increment frequency is 812.5 MHz
158 *
159 * For E822 devices the clock can be derived from different sources, and the
160 * increment has an effective frequency of one of the following:
161 * - 823.4375 MHz
162 * - 783.36 MHz
163 * - 796.875 MHz
164 * - 816 MHz
165 * - 830.078125 MHz
166 * - 783.36 MHz
167 *
168 * The hardware captures timestamps in the PHY for incoming packets, and for
169 * outgoing packets on request. To support this, the PHY maintains a timer
170 * that matches the lower 64 bits of the global source timer.
171 *
172 * In order to ensure that the PHY timers and the source timer are equivalent,
173 * shadow registers are used to prepare the desired initial values. A special
174 * sync command is issued to trigger copying from the shadow registers into
175 * the appropriate source and PHY registers simultaneously.
176 *
177 * The driver supports devices which have different PHYs with subtly different
178 * mechanisms to program and control the timers. We divide the devices into
179 * families named after the first major device, E810 and similar devices, and
180 * E822 and similar devices.
181 *
182 * - E822 based devices have additional support for fine grained Vernier
183 * calibration which requires significant setup
184 * - The layout of timestamp data in the PHY register blocks is different
185 * - The way timer synchronization commands are issued is different.
186 *
187 * To support this, very low level functions have an e810 or e822 suffix
188 * indicating what type of device they work on. Higher level abstractions for
189 * tasks that can be done on both devices do not have the suffix and will
190 * correctly look up the appropriate low level function when running.
191 *
192 * Functions which only make sense on a single device family may not have
193 * a suitable generic implementation
194 */
195
196 /**
197 * ice_get_ptp_src_clock_index - determine source clock index
198 * @hw: pointer to HW struct
199 *
200 * Determine the source clock index currently in use, based on device
201 * capabilities reported during initialization.
202 */
ice_get_ptp_src_clock_index(struct ice_hw * hw)203 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
204 {
205 return hw->func_caps.ts_func_info.tmr_index_assoc;
206 }
207
208 /**
209 * ice_ptp_read_src_incval - Read source timer increment value
210 * @hw: pointer to HW struct
211 *
212 * Read the increment value of the source timer and return it.
213 */
ice_ptp_read_src_incval(struct ice_hw * hw)214 static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
215 {
216 u32 lo, hi;
217 u8 tmr_idx;
218
219 tmr_idx = ice_get_ptp_src_clock_index(hw);
220
221 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
222 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
223
224 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
225 }
226
227 /**
228 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
229 * @hw: pointer to HW struct
230 * @cmd: Timer command
231 *
232 * Return: the source timer command register value for the given PTP timer
233 * command.
234 */
ice_ptp_tmr_cmd_to_src_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)235 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
236 enum ice_ptp_tmr_cmd cmd)
237 {
238 u32 cmd_val, tmr_idx;
239
240 switch (cmd) {
241 case ICE_PTP_INIT_TIME:
242 cmd_val = GLTSYN_CMD_INIT_TIME;
243 break;
244 case ICE_PTP_INIT_INCVAL:
245 cmd_val = GLTSYN_CMD_INIT_INCVAL;
246 break;
247 case ICE_PTP_ADJ_TIME:
248 cmd_val = GLTSYN_CMD_ADJ_TIME;
249 break;
250 case ICE_PTP_ADJ_TIME_AT_TIME:
251 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
252 break;
253 case ICE_PTP_NOP:
254 case ICE_PTP_READ_TIME:
255 cmd_val = GLTSYN_CMD_READ_TIME;
256 break;
257 default:
258 dev_warn(ice_hw_to_dev(hw),
259 "Ignoring unrecognized timer command %u\n", cmd);
260 cmd_val = 0;
261 }
262
263 tmr_idx = ice_get_ptp_src_clock_index(hw);
264
265 return tmr_idx << SEL_CPK_SRC | cmd_val;
266 }
267
268 /**
269 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
270 * @hw: pointer to HW struct
271 * @cmd: Timer command
272 *
273 * Note that some hardware families use a different command register value for
274 * the PHY ports, while other hardware families use the same register values
275 * as the source timer.
276 *
277 * Return: the PHY port timer command register value for the given PTP timer
278 * command.
279 */
ice_ptp_tmr_cmd_to_port_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)280 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
281 enum ice_ptp_tmr_cmd cmd)
282 {
283 u32 cmd_val, tmr_idx;
284
285 /* Certain hardware families share the same register values for the
286 * port register and source timer register.
287 */
288 switch (hw->mac_type) {
289 case ICE_MAC_E810:
290 case ICE_MAC_E830:
291 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
292 default:
293 break;
294 }
295
296 switch (cmd) {
297 case ICE_PTP_INIT_TIME:
298 cmd_val = PHY_CMD_INIT_TIME;
299 break;
300 case ICE_PTP_INIT_INCVAL:
301 cmd_val = PHY_CMD_INIT_INCVAL;
302 break;
303 case ICE_PTP_ADJ_TIME:
304 cmd_val = PHY_CMD_ADJ_TIME;
305 break;
306 case ICE_PTP_ADJ_TIME_AT_TIME:
307 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
308 break;
309 case ICE_PTP_READ_TIME:
310 cmd_val = PHY_CMD_READ_TIME;
311 break;
312 case ICE_PTP_NOP:
313 cmd_val = 0;
314 break;
315 default:
316 dev_warn(ice_hw_to_dev(hw),
317 "Ignoring unrecognized timer command %u\n", cmd);
318 cmd_val = 0;
319 }
320
321 tmr_idx = ice_get_ptp_src_clock_index(hw);
322
323 return tmr_idx << SEL_PHY_SRC | cmd_val;
324 }
325
326 /**
327 * ice_ptp_src_cmd - Prepare source timer for a timer command
328 * @hw: pointer to HW structure
329 * @cmd: Timer command
330 *
331 * Prepare the source timer for an upcoming timer sync command.
332 */
ice_ptp_src_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)333 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
334 {
335 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
336 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
337
338 if (!ice_is_primary(hw))
339 hw = ice_get_primary_hw(pf);
340
341 wr32(hw, GLTSYN_CMD, cmd_val);
342 }
343
344 /**
345 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
346 * @hw: pointer to HW struct
347 *
348 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
349 * write immediately. This triggers the hardware to begin executing all of the
350 * source and PHY timer commands synchronously.
351 */
ice_ptp_exec_tmr_cmd(struct ice_hw * hw)352 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
353 {
354 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
355
356 if (!ice_is_primary(hw))
357 hw = ice_get_primary_hw(pf);
358
359 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
360 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
361 ice_flush(hw);
362 }
363
364 /**
365 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay
366 * @hw: pointer to HW struct
367 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds
368 */
ice_ptp_cfg_sync_delay(const struct ice_hw * hw,u32 delay)369 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay)
370 {
371 wr32(hw, GLTSYN_SYNC_DLAY, delay);
372 ice_flush(hw);
373 }
374
375 /* 56G PHY device functions
376 *
377 * The following functions operate on devices with the ETH 56G PHY.
378 */
379
380 /**
381 * ice_ptp_init_phc_e825c - Perform E825C specific PHC initialization
382 * @hw: pointer to HW struct
383 *
384 * Perform E825C-specific PTP hardware clock initialization steps.
385 *
386 * Return: 0 on success, or a negative error value on failure.
387 */
ice_ptp_init_phc_e825c(struct ice_hw * hw)388 static int ice_ptp_init_phc_e825c(struct ice_hw *hw)
389 {
390 int err;
391
392 /* Soft reset all ports, to ensure everything is at a clean state */
393 for (int port = 0; port < hw->ptp.num_lports; port++) {
394 err = ice_ptp_phy_soft_reset_eth56g(hw, port);
395 if (err) {
396 ice_debug(hw, ICE_DBG_PTP, "Failed to soft reset port %d, err %d\n",
397 port, err);
398 return err;
399 }
400 }
401
402 return 0;
403 }
404
405 /**
406 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number
407 * @hw: pointer to the HW struct
408 * @port: destination port
409 *
410 * Return: destination sideband queue PHY device.
411 */
ice_ptp_get_dest_dev_e825(struct ice_hw * hw,u8 port)412 static enum ice_sbq_dev_id ice_ptp_get_dest_dev_e825(struct ice_hw *hw,
413 u8 port)
414 {
415 u8 curr_phy, tgt_phy;
416
417 tgt_phy = port >= hw->ptp.ports_per_phy;
418 curr_phy = hw->lane_num >= hw->ptp.ports_per_phy;
419 /* In the driver, lanes 4..7 are in fact 0..3 on a second PHY.
420 * On a single complex E825C, PHY 0 is always destination device phy_0
421 * and PHY 1 is phy_0_peer.
422 * On dual complex E825C, device phy_0 points to PHY on a current
423 * complex and phy_0_peer to PHY on a different complex.
424 */
425 if ((!ice_is_dual(hw) && tgt_phy == 1) ||
426 (ice_is_dual(hw) && tgt_phy != curr_phy))
427 return ice_sbq_dev_phy_0_peer;
428 else
429 return ice_sbq_dev_phy_0;
430 }
431
432 /**
433 * ice_write_phy_eth56g - Write a PHY port register
434 * @hw: pointer to the HW struct
435 * @port: destination port
436 * @addr: PHY register address
437 * @val: Value to write
438 *
439 * Return: 0 on success, other error codes when failed to write to PHY
440 */
ice_write_phy_eth56g(struct ice_hw * hw,u8 port,u32 addr,u32 val)441 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val)
442 {
443 struct ice_sbq_msg_input msg = {
444 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
445 .opcode = ice_sbq_msg_wr,
446 .msg_addr_low = lower_16_bits(addr),
447 .msg_addr_high = upper_16_bits(addr),
448 .data = val
449 };
450 int err;
451
452 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
453 if (err)
454 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
455 err);
456
457 return err;
458 }
459
460 /**
461 * ice_read_phy_eth56g - Read a PHY port register
462 * @hw: pointer to the HW struct
463 * @port: destination port
464 * @addr: PHY register address
465 * @val: Value to write
466 *
467 * Return: 0 on success, other error codes when failed to read from PHY
468 */
ice_read_phy_eth56g(struct ice_hw * hw,u8 port,u32 addr,u32 * val)469 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val)
470 {
471 struct ice_sbq_msg_input msg = {
472 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port),
473 .opcode = ice_sbq_msg_rd,
474 .msg_addr_low = lower_16_bits(addr),
475 .msg_addr_high = upper_16_bits(addr)
476 };
477 int err;
478
479 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
480 if (err)
481 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
482 err);
483 else
484 *val = msg.data;
485
486 return err;
487 }
488
489 /**
490 * ice_phy_res_address_eth56g - Calculate a PHY port register address
491 * @hw: pointer to the HW struct
492 * @lane: Lane number to be written
493 * @res_type: resource type (register/memory)
494 * @offset: Offset from PHY port register base
495 * @addr: The result address
496 *
497 * Return:
498 * * %0 - success
499 * * %EINVAL - invalid port number or resource type
500 */
ice_phy_res_address_eth56g(struct ice_hw * hw,u8 lane,enum eth56g_res_type res_type,u32 offset,u32 * addr)501 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane,
502 enum eth56g_res_type res_type,
503 u32 offset,
504 u32 *addr)
505 {
506 if (res_type >= NUM_ETH56G_PHY_RES)
507 return -EINVAL;
508
509 /* Lanes 4..7 are in fact 0..3 on a second PHY */
510 lane %= hw->ptp.ports_per_phy;
511 *addr = eth56g_phy_res[res_type].base_addr +
512 lane * eth56g_phy_res[res_type].step + offset;
513
514 return 0;
515 }
516
517 /**
518 * ice_write_port_eth56g - Write a PHY port register
519 * @hw: pointer to the HW struct
520 * @offset: PHY register offset
521 * @port: Port number
522 * @val: Value to write
523 * @res_type: resource type (register/memory)
524 *
525 * Return:
526 * * %0 - success
527 * * %EINVAL - invalid port number or resource type
528 * * %other - failed to write to PHY
529 */
ice_write_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val,enum eth56g_res_type res_type)530 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
531 u32 val, enum eth56g_res_type res_type)
532 {
533 u32 addr;
534 int err;
535
536 if (port >= hw->ptp.num_lports)
537 return -EINVAL;
538
539 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
540 if (err)
541 return err;
542
543 return ice_write_phy_eth56g(hw, port, addr, val);
544 }
545
546 /**
547 * ice_read_port_eth56g - Read a PHY port register
548 * @hw: pointer to the HW struct
549 * @offset: PHY register offset
550 * @port: Port number
551 * @val: Value to write
552 * @res_type: resource type (register/memory)
553 *
554 * Return:
555 * * %0 - success
556 * * %EINVAL - invalid port number or resource type
557 * * %other - failed to read from PHY
558 */
ice_read_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val,enum eth56g_res_type res_type)559 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
560 u32 *val, enum eth56g_res_type res_type)
561 {
562 u32 addr;
563 int err;
564
565 if (port >= hw->ptp.num_lports)
566 return -EINVAL;
567
568 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr);
569 if (err)
570 return err;
571
572 return ice_read_phy_eth56g(hw, port, addr, val);
573 }
574
575 /**
576 * ice_write_ptp_reg_eth56g - Write a PHY port register
577 * @hw: pointer to the HW struct
578 * @port: Port number to be written
579 * @offset: Offset from PHY port register base
580 * @val: Value to write
581 *
582 * Return:
583 * * %0 - success
584 * * %EINVAL - invalid port number or resource type
585 * * %other - failed to write to PHY
586 */
ice_write_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)587 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
588 u32 val)
589 {
590 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
591 }
592
593 /**
594 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
595 * parameter
596 * @hw: pointer to the HW struct
597 * @port: Port number to be written
598 * @offset: Offset from PHY port register base
599 * @val: Value to write
600 *
601 * Return:
602 * * %0 - success
603 * * %EINVAL - invalid port number or resource type
604 * * %other - failed to write to PHY
605 */
ice_write_mac_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)606 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
607 u32 val)
608 {
609 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
610 }
611
612 /**
613 * ice_write_xpcs_reg_eth56g - Write a PHY port register
614 * @hw: pointer to the HW struct
615 * @port: Port number to be written
616 * @offset: Offset from PHY port register base
617 * @val: Value to write
618 *
619 * Return:
620 * * %0 - success
621 * * %EINVAL - invalid port number or resource type
622 * * %other - failed to write to PHY
623 */
ice_write_xpcs_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)624 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
625 u32 val)
626 {
627 return ice_write_port_eth56g(hw, port, offset, val,
628 ETH56G_PHY_REG_XPCS);
629 }
630
631 /**
632 * ice_read_ptp_reg_eth56g - Read a PHY port register
633 * @hw: pointer to the HW struct
634 * @port: Port number to be read
635 * @offset: Offset from PHY port register base
636 * @val: Pointer to the value to read (out param)
637 *
638 * Return:
639 * * %0 - success
640 * * %EINVAL - invalid port number or resource type
641 * * %other - failed to read from PHY
642 */
ice_read_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)643 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
644 u32 *val)
645 {
646 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
647 }
648
649 /**
650 * ice_read_mac_reg_eth56g - Read a PHY port register
651 * @hw: pointer to the HW struct
652 * @port: Port number to be read
653 * @offset: Offset from PHY port register base
654 * @val: Pointer to the value to read (out param)
655 *
656 * Return:
657 * * %0 - success
658 * * %EINVAL - invalid port number or resource type
659 * * %other - failed to read from PHY
660 */
ice_read_mac_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)661 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
662 u32 *val)
663 {
664 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
665 }
666
667 /**
668 * ice_read_gpcs_reg_eth56g - Read a PHY port register
669 * @hw: pointer to the HW struct
670 * @port: Port number to be read
671 * @offset: Offset from PHY port register base
672 * @val: Pointer to the value to read (out param)
673 *
674 * Return:
675 * * %0 - success
676 * * %EINVAL - invalid port number or resource type
677 * * %other - failed to read from PHY
678 */
ice_read_gpcs_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)679 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
680 u32 *val)
681 {
682 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS);
683 }
684
685 /**
686 * ice_read_port_mem_eth56g - Read a PHY port memory location
687 * @hw: pointer to the HW struct
688 * @port: Port number to be read
689 * @offset: Offset from PHY port register base
690 * @val: Pointer to the value to read (out param)
691 *
692 * Return:
693 * * %0 - success
694 * * %EINVAL - invalid port number or resource type
695 * * %other - failed to read from PHY
696 */
ice_read_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)697 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
698 u32 *val)
699 {
700 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
701 }
702
703 /**
704 * ice_write_port_mem_eth56g - Write a PHY port memory location
705 * @hw: pointer to the HW struct
706 * @port: Port number to be read
707 * @offset: Offset from PHY port register base
708 * @val: Pointer to the value to read (out param)
709 *
710 * Return:
711 * * %0 - success
712 * * %EINVAL - invalid port number or resource type
713 * * %other - failed to write to PHY
714 */
ice_write_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)715 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
716 u32 val)
717 {
718 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
719 }
720
721 /**
722 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register
723 * @hw: pointer to the HW struct
724 * @offset: PHY register offset
725 * @port: Port number
726 * @val: Value to write
727 *
728 * Return:
729 * * %0 - success
730 * * %EIO - invalid port number or resource type
731 * * %other - failed to write to PHY
732 */
ice_write_quad_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)733 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
734 u32 offset, u32 val)
735 {
736 u32 addr;
737
738 if (port >= hw->ptp.num_lports)
739 return -EIO;
740
741 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
742
743 return ice_write_phy_eth56g(hw, port, addr, val);
744 }
745
746 /**
747 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register
748 * @hw: pointer to the HW struct
749 * @offset: PHY register offset
750 * @port: Port number
751 * @val: Value to read
752 *
753 * Return:
754 * * %0 - success
755 * * %EIO - invalid port number or resource type
756 * * %other - failed to read from PHY
757 */
ice_read_quad_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val)758 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
759 u32 offset, u32 *val)
760 {
761 u32 addr;
762
763 if (port >= hw->ptp.num_lports)
764 return -EIO;
765
766 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
767
768 return ice_read_phy_eth56g(hw, port, addr, val);
769 }
770
771 /**
772 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
773 * @low_addr: the low address to check
774 * @high_addr: on return, contains the high address of the 64bit register
775 *
776 * Write the appropriate high register offset to use.
777 *
778 * Return: true if the provided low address is one of the known 64bit PHY values
779 * represented as two 32bit registers, false otherwise.
780 */
ice_is_64b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)781 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
782 {
783 switch (low_addr) {
784 case PHY_REG_TX_TIMER_INC_PRE_L:
785 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U;
786 return true;
787 case PHY_REG_RX_TIMER_INC_PRE_L:
788 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U;
789 return true;
790 case PHY_REG_TX_CAPTURE_L:
791 *high_addr = PHY_REG_TX_CAPTURE_U;
792 return true;
793 case PHY_REG_RX_CAPTURE_L:
794 *high_addr = PHY_REG_RX_CAPTURE_U;
795 return true;
796 case PHY_REG_TOTAL_TX_OFFSET_L:
797 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U;
798 return true;
799 case PHY_REG_TOTAL_RX_OFFSET_L:
800 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U;
801 return true;
802 case PHY_REG_TX_MEMORY_STATUS_L:
803 *high_addr = PHY_REG_TX_MEMORY_STATUS_U;
804 return true;
805 default:
806 return false;
807 }
808 }
809
810 /**
811 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
812 * @low_addr: the low address to check
813 * @high_addr: on return, contains the high address of the 40bit value
814 *
815 * Write the appropriate high register offset to use.
816 *
817 * Return: true if the provided low address is one of the known 40bit PHY
818 * values split into two registers with the lower 8 bits in the low register and
819 * the upper 32 bits in the high register, false otherwise.
820 */
ice_is_40b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)821 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
822 {
823 switch (low_addr) {
824 case PHY_REG_TIMETUS_L:
825 *high_addr = PHY_REG_TIMETUS_U;
826 return true;
827 case PHY_PCS_REF_TUS_L:
828 *high_addr = PHY_PCS_REF_TUS_U;
829 return true;
830 case PHY_PCS_REF_INC_L:
831 *high_addr = PHY_PCS_REF_INC_U;
832 return true;
833 default:
834 return false;
835 }
836 }
837
838 /**
839 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
840 * @hw: pointer to the HW struct
841 * @port: PHY port to read from
842 * @low_addr: offset of the lower register to read from
843 * @val: on return, the contents of the 64bit value from the PHY registers
844 * @res_type: resource type
845 *
846 * Check if the caller has specified a known 40 bit register offset and read
847 * the two registers associated with a 40bit value and return it in the val
848 * pointer.
849 *
850 * Return:
851 * * %0 - success
852 * * %EINVAL - not a 64 bit register
853 * * %other - failed to read from PHY
854 */
ice_read_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val,enum eth56g_res_type res_type)855 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
856 u64 *val, enum eth56g_res_type res_type)
857 {
858 u16 high_addr;
859 u32 lo, hi;
860 int err;
861
862 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
863 return -EINVAL;
864
865 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type);
866 if (err) {
867 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
868 low_addr, err);
869 return err;
870 }
871
872 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type);
873 if (err) {
874 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
875 high_addr, err);
876 return err;
877 }
878
879 *val = ((u64)hi << 32) | lo;
880
881 return 0;
882 }
883
884 /**
885 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
886 * @hw: pointer to the HW struct
887 * @port: PHY port to read from
888 * @low_addr: offset of the lower register to read from
889 * @val: on return, the contents of the 64bit value from the PHY registers
890 *
891 * Check if the caller has specified a known 40 bit register offset and read
892 * the two registers associated with a 40bit value and return it in the val
893 * pointer.
894 *
895 * Return:
896 * * %0 - success
897 * * %EINVAL - not a 64 bit register
898 * * %other - failed to read from PHY
899 */
ice_read_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)900 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
901 u64 *val)
902 {
903 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val,
904 ETH56G_PHY_REG_PTP);
905 }
906
907 /**
908 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
909 * @hw: pointer to the HW struct
910 * @port: port to write to
911 * @low_addr: offset of the low register
912 * @val: 40b value to write
913 * @res_type: resource type
914 *
915 * Check if the caller has specified a known 40 bit register offset and write
916 * provided 40b value to the two associated registers by splitting it up into
917 * two chunks, the lower 8 bits and the upper 32 bits.
918 *
919 * Return:
920 * * %0 - success
921 * * %EINVAL - not a 40 bit register
922 * * %other - failed to write to PHY
923 */
ice_write_40b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)924 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
925 u16 low_addr, u64 val,
926 enum eth56g_res_type res_type)
927 {
928 u16 high_addr;
929 u32 lo, hi;
930 int err;
931
932 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr))
933 return -EINVAL;
934
935 lo = FIELD_GET(P_REG_40B_LOW_M, val);
936 hi = (u32)(val >> P_REG_40B_HIGH_S);
937
938 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
939 if (err) {
940 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
941 low_addr, err);
942 return err;
943 }
944
945 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
946 if (err) {
947 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
948 high_addr, err);
949 return err;
950 }
951
952 return 0;
953 }
954
955 /**
956 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
957 * @hw: pointer to the HW struct
958 * @port: port to write to
959 * @low_addr: offset of the low register
960 * @val: 40b value to write
961 *
962 * Check if the caller has specified a known 40 bit register offset and write
963 * provided 40b value to the two associated registers by splitting it up into
964 * two chunks, the lower 8 bits and the upper 32 bits.
965 *
966 * Return:
967 * * %0 - success
968 * * %EINVAL - not a 40 bit register
969 * * %other - failed to write to PHY
970 */
ice_write_40b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)971 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
972 u16 low_addr, u64 val)
973 {
974 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val,
975 ETH56G_PHY_REG_PTP);
976 }
977
978 /**
979 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
980 * @hw: pointer to the HW struct
981 * @port: PHY port to read from
982 * @low_addr: offset of the lower register to read from
983 * @val: the contents of the 64bit value to write to PHY
984 * @res_type: resource type
985 *
986 * Check if the caller has specified a known 64 bit register offset and write
987 * the 64bit value to the two associated 32bit PHY registers.
988 *
989 * Return:
990 * * %0 - success
991 * * %EINVAL - not a 64 bit register
992 * * %other - failed to write to PHY
993 */
ice_write_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)994 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
995 u16 low_addr, u64 val,
996 enum eth56g_res_type res_type)
997 {
998 u16 high_addr;
999 u32 lo, hi;
1000 int err;
1001
1002 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1003 return -EINVAL;
1004
1005 lo = lower_32_bits(val);
1006 hi = upper_32_bits(val);
1007
1008 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1009 if (err) {
1010 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1011 low_addr, err);
1012 return err;
1013 }
1014
1015 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1016 if (err) {
1017 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1018 high_addr, err);
1019 return err;
1020 }
1021
1022 return 0;
1023 }
1024
1025 /**
1026 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1027 * @hw: pointer to the HW struct
1028 * @port: PHY port to read from
1029 * @low_addr: offset of the lower register to read from
1030 * @val: the contents of the 64bit value to write to PHY
1031 *
1032 * Check if the caller has specified a known 64 bit register offset and write
1033 * the 64bit value to the two associated 32bit PHY registers.
1034 *
1035 * Return:
1036 * * %0 - success
1037 * * %EINVAL - not a 64 bit register
1038 * * %other - failed to write to PHY
1039 */
ice_write_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1040 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1041 u16 low_addr, u64 val)
1042 {
1043 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val,
1044 ETH56G_PHY_REG_PTP);
1045 }
1046
1047 /**
1048 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1049 * @hw: pointer to the HW struct
1050 * @port: the port to read from
1051 * @idx: the timestamp index to read
1052 * @tstamp: on return, the 40bit timestamp value
1053 *
1054 * Read a 40bit timestamp value out of the two associated entries in the
1055 * port memory block of the internal PHYs of the 56G devices.
1056 *
1057 * Return:
1058 * * %0 - success
1059 * * %other - failed to read from PHY
1060 */
ice_read_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx,u64 * tstamp)1061 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
1062 u64 *tstamp)
1063 {
1064 u16 lo_addr, hi_addr;
1065 u32 lo, hi;
1066 int err;
1067
1068 lo_addr = (u16)PHY_TSTAMP_L(idx);
1069 hi_addr = (u16)PHY_TSTAMP_U(idx);
1070
1071 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo);
1072 if (err) {
1073 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
1074 err);
1075 return err;
1076 }
1077
1078 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi);
1079 if (err) {
1080 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
1081 err);
1082 return err;
1083 }
1084
1085 /* For 56G based internal PHYs, the timestamp is reported with the
1086 * lower 8 bits in the low register, and the upper 32 bits in the high
1087 * register.
1088 */
1089 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
1090 FIELD_PREP(PHY_40B_LOW_M, lo);
1091 return 0;
1092 }
1093
1094 /**
1095 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1096 * @hw: pointer to the HW struct
1097 * @port: the quad to read from
1098 * @idx: the timestamp index to reset
1099 *
1100 * Read and then forcibly clear the timestamp index to ensure the valid bit is
1101 * cleared and the timestamp status bit is reset in the PHY port memory of
1102 * internal PHYs of the 56G devices.
1103 *
1104 * To directly clear the contents of the timestamp block entirely, discarding
1105 * all timestamp data at once, software should instead use
1106 * ice_ptp_reset_ts_memory_quad_eth56g().
1107 *
1108 * This function should only be called on an idx whose bit is set according to
1109 * ice_get_phy_tx_tstamp_ready().
1110 *
1111 * Return:
1112 * * %0 - success
1113 * * %other - failed to write to PHY
1114 */
ice_clear_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx)1115 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
1116 {
1117 u64 unused_tstamp;
1118 u16 lo_addr;
1119 int err;
1120
1121 /* Read the timestamp register to ensure the timestamp status bit is
1122 * cleared.
1123 */
1124 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp);
1125 if (err) {
1126 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
1127 port, idx, err);
1128 }
1129
1130 lo_addr = (u16)PHY_TSTAMP_L(idx);
1131
1132 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0);
1133 if (err) {
1134 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
1135 port, idx, err);
1136 return err;
1137 }
1138
1139 return 0;
1140 }
1141
1142 /**
1143 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1144 * @hw: pointer to the HW struct
1145 */
ice_ptp_reset_ts_memory_eth56g(struct ice_hw * hw)1146 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
1147 {
1148 unsigned int port;
1149
1150 for (port = 0; port < hw->ptp.num_lports; port++) {
1151 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
1152 0);
1153 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
1154 0);
1155 }
1156 }
1157
1158 /**
1159 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1160 * @hw: pointer to the HW struct
1161 * @port: port number
1162 * @time: time to initialize the PHY port clocks to
1163 *
1164 * Write a new initial time value into registers of a specific PHY port.
1165 *
1166 * Return:
1167 * * %0 - success
1168 * * %other - failed to write to PHY
1169 */
ice_ptp_prep_port_time_eth56g(struct ice_hw * hw,u8 port,u64 time)1170 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port,
1171 u64 time)
1172 {
1173 int err;
1174
1175 /* Tx case */
1176 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1177 time);
1178 if (err)
1179 return err;
1180
1181 /* Rx case */
1182 return ice_write_64b_ptp_reg_eth56g(hw, port,
1183 PHY_REG_RX_TIMER_INC_PRE_L, time);
1184 }
1185
1186 /**
1187 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1188 * @hw: pointer to the HW struct
1189 * @time: Time to initialize the PHY port clocks to
1190 *
1191 * Program the PHY port registers with a new initial time value. The port
1192 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
1193 * command. The time value is the upper 32 bits of the PHY timer, usually in
1194 * units of nominal nanoseconds.
1195 *
1196 * Return:
1197 * * %0 - success
1198 * * %other - failed to write to PHY
1199 */
ice_ptp_prep_phy_time_eth56g(struct ice_hw * hw,u32 time)1200 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
1201 {
1202 u64 phy_time;
1203 u8 port;
1204
1205 /* The time represents the upper 32 bits of the PHY timer, so we need
1206 * to shift to account for this when programming.
1207 */
1208 phy_time = (u64)time << 32;
1209
1210 for (port = 0; port < hw->ptp.num_lports; port++) {
1211 int err;
1212
1213 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time);
1214 if (err) {
1215 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1216 port, err);
1217 return err;
1218 }
1219 }
1220
1221 return 0;
1222 }
1223
1224 /**
1225 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1226 * @hw: pointer to HW struct
1227 * @port: Port number to be programmed
1228 * @time: time in cycles to adjust the port clocks
1229 *
1230 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1231 * registers. The atomic adjustment won't be completed until the driver issues
1232 * an ICE_PTP_ADJ_TIME command.
1233 *
1234 * Note that time is not in units of nanoseconds. It is in clock time
1235 * including the lower sub-nanosecond portion of the port timer.
1236 *
1237 * Negative adjustments are supported using 2s complement arithmetic.
1238 *
1239 * Return:
1240 * * %0 - success
1241 * * %other - failed to write to PHY
1242 */
ice_ptp_prep_port_adj_eth56g(struct ice_hw * hw,u8 port,s64 time)1243 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time)
1244 {
1245 u32 l_time, u_time;
1246 int err;
1247
1248 l_time = lower_32_bits(time);
1249 u_time = upper_32_bits(time);
1250
1251 /* Tx case */
1252 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1253 l_time);
1254 if (err)
1255 goto exit_err;
1256
1257 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
1258 u_time);
1259 if (err)
1260 goto exit_err;
1261
1262 /* Rx case */
1263 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
1264 l_time);
1265 if (err)
1266 goto exit_err;
1267
1268 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
1269 u_time);
1270 if (err)
1271 goto exit_err;
1272
1273 return 0;
1274
1275 exit_err:
1276 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1277 port, err);
1278 return err;
1279 }
1280
1281 /**
1282 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1283 * @hw: pointer to HW struct
1284 * @adj: adjustment in nanoseconds
1285 *
1286 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1287 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1288 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
1289 *
1290 * Return:
1291 * * %0 - success
1292 * * %other - failed to write to PHY
1293 */
ice_ptp_prep_phy_adj_eth56g(struct ice_hw * hw,s32 adj)1294 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj)
1295 {
1296 s64 cycles;
1297 u8 port;
1298
1299 /* The port clock supports adjustment of the sub-nanosecond portion of
1300 * the clock (lowest 32 bits). We shift the provided adjustment in
1301 * nanoseconds by 32 to calculate the appropriate adjustment to program
1302 * into the PHY ports.
1303 */
1304 cycles = (s64)adj << 32;
1305
1306 for (port = 0; port < hw->ptp.num_lports; port++) {
1307 int err;
1308
1309 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles);
1310 if (err)
1311 return err;
1312 }
1313
1314 return 0;
1315 }
1316
1317 /**
1318 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1319 * @hw: pointer to HW struct
1320 * @incval: new increment value to prepare
1321 *
1322 * Prepare each of the PHY ports for a new increment value by programming the
1323 * port's TIMETUS registers. The new increment value will be updated after
1324 * issuing an ICE_PTP_INIT_INCVAL command.
1325 *
1326 * Return:
1327 * * %0 - success
1328 * * %other - failed to write to PHY
1329 */
ice_ptp_prep_phy_incval_eth56g(struct ice_hw * hw,u64 incval)1330 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
1331 {
1332 u8 port;
1333
1334 for (port = 0; port < hw->ptp.num_lports; port++) {
1335 int err;
1336
1337 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
1338 incval);
1339 if (err) {
1340 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1341 port, err);
1342 return err;
1343 }
1344 }
1345
1346 return 0;
1347 }
1348
1349 /**
1350 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1351 * @hw: pointer to HW struct
1352 * @port: Port number to read
1353 * @tx_ts: on return, the Tx port time capture
1354 * @rx_ts: on return, the Rx port time capture
1355 *
1356 * Read the port's Tx and Rx local time capture values.
1357 *
1358 * Return:
1359 * * %0 - success
1360 * * %other - failed to read from PHY
1361 */
ice_ptp_read_port_capture_eth56g(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)1362 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
1363 u64 *tx_ts, u64 *rx_ts)
1364 {
1365 int err;
1366
1367 /* Tx case */
1368 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
1369 tx_ts);
1370 if (err) {
1371 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1372 err);
1373 return err;
1374 }
1375
1376 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
1377
1378 /* Rx case */
1379 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
1380 rx_ts);
1381 if (err) {
1382 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1383 err);
1384 return err;
1385 }
1386
1387 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
1388
1389 return 0;
1390 }
1391
1392 /**
1393 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1394 * @hw: pointer to HW struct
1395 * @port: Port to which cmd has to be sent
1396 * @cmd: Command to be sent to the port
1397 *
1398 * Prepare the requested port for an upcoming timer sync command.
1399 *
1400 * Return:
1401 * * %0 - success
1402 * * %other - failed to write to PHY
1403 */
ice_ptp_write_port_cmd_eth56g(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)1404 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
1405 enum ice_ptp_tmr_cmd cmd)
1406 {
1407 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
1408 int err;
1409
1410 /* Tx case */
1411 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val);
1412 if (err) {
1413 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1414 err);
1415 return err;
1416 }
1417
1418 /* Rx case */
1419 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val);
1420 if (err) {
1421 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1422 err);
1423 return err;
1424 }
1425
1426 return 0;
1427 }
1428
1429 /**
1430 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1431 * @li: pointer to link information struct
1432 *
1433 * Return: simplified ETH56G PHY speed
1434 */
1435 static enum ice_eth56g_link_spd
ice_phy_get_speed_eth56g(struct ice_link_status * li)1436 ice_phy_get_speed_eth56g(struct ice_link_status *li)
1437 {
1438 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low,
1439 li->phy_type_high);
1440
1441 switch (speed) {
1442 case ICE_AQ_LINK_SPEED_1000MB:
1443 return ICE_ETH56G_LNK_SPD_1G;
1444 case ICE_AQ_LINK_SPEED_2500MB:
1445 return ICE_ETH56G_LNK_SPD_2_5G;
1446 case ICE_AQ_LINK_SPEED_10GB:
1447 return ICE_ETH56G_LNK_SPD_10G;
1448 case ICE_AQ_LINK_SPEED_25GB:
1449 return ICE_ETH56G_LNK_SPD_25G;
1450 case ICE_AQ_LINK_SPEED_40GB:
1451 return ICE_ETH56G_LNK_SPD_40G;
1452 case ICE_AQ_LINK_SPEED_50GB:
1453 switch (li->phy_type_low) {
1454 case ICE_PHY_TYPE_LOW_50GBASE_SR:
1455 case ICE_PHY_TYPE_LOW_50GBASE_FR:
1456 case ICE_PHY_TYPE_LOW_50GBASE_LR:
1457 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
1458 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
1459 case ICE_PHY_TYPE_LOW_50G_AUI1:
1460 return ICE_ETH56G_LNK_SPD_50G;
1461 default:
1462 return ICE_ETH56G_LNK_SPD_50G2;
1463 }
1464 case ICE_AQ_LINK_SPEED_100GB:
1465 if (li->phy_type_high ||
1466 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2)
1467 return ICE_ETH56G_LNK_SPD_100G2;
1468 else
1469 return ICE_ETH56G_LNK_SPD_100G;
1470 default:
1471 return ICE_ETH56G_LNK_SPD_1G;
1472 }
1473 }
1474
1475 /**
1476 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1477 * @hw: pointer to the HW struct
1478 * @port: port to configure
1479 *
1480 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1481 * timestamp calibration process.
1482 *
1483 * Return:
1484 * * %0 - success
1485 * * %other - PHY read/write failed
1486 */
ice_phy_cfg_parpcs_eth56g(struct ice_hw * hw,u8 port)1487 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
1488 {
1489 u32 val;
1490 int err;
1491
1492 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH,
1493 ICE_ETH56G_NOMINAL_THRESH4);
1494 if (err) {
1495 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
1496 err);
1497 return err;
1498 }
1499
1500 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
1501 case ICE_ETH56G_LNK_SPD_1G:
1502 case ICE_ETH56G_LNK_SPD_2_5G:
1503 err = ice_read_quad_ptp_reg_eth56g(hw, port,
1504 PHY_GPCS_CONFIG_REG0, &val);
1505 if (err) {
1506 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
1507 err);
1508 return err;
1509 }
1510
1511 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M;
1512 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
1513 ICE_ETH56G_NOMINAL_TX_THRESH);
1514
1515 err = ice_write_quad_ptp_reg_eth56g(hw, port,
1516 PHY_GPCS_CONFIG_REG0, val);
1517 if (err) {
1518 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
1519 err);
1520 return err;
1521 }
1522 break;
1523 default:
1524 break;
1525 }
1526
1527 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L,
1528 ICE_ETH56G_NOMINAL_PCS_REF_TUS);
1529 if (err) {
1530 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
1531 err);
1532 return err;
1533 }
1534
1535 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L,
1536 ICE_ETH56G_NOMINAL_PCS_REF_INC);
1537 if (err) {
1538 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
1539 err);
1540 return err;
1541 }
1542
1543 return 0;
1544 }
1545
1546 /**
1547 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
1548 * @hw: Pointer to the HW struct
1549 * @port: Port to configure
1550 *
1551 * Return:
1552 * * %0 - success
1553 * * %other - PHY read/write failed
1554 */
ice_phy_cfg_ptp_1step_eth56g(struct ice_hw * hw,u8 port)1555 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
1556 {
1557 u8 quad_lane = port % ICE_PORTS_PER_QUAD;
1558 u32 addr, val, peer_delay;
1559 bool enable, sfd_ena;
1560 int err;
1561
1562 enable = hw->ptp.phy.eth56g.onestep_ena;
1563 peer_delay = hw->ptp.phy.eth56g.peer_delay;
1564 sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
1565
1566 addr = PHY_PTP_1STEP_CONFIG;
1567 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val);
1568 if (err)
1569 return err;
1570
1571 if (enable)
1572 val |= BIT(quad_lane);
1573 else
1574 val &= ~BIT(quad_lane);
1575
1576 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
1577
1578 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
1579 if (err)
1580 return err;
1581
1582 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane);
1583 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
1584 if (peer_delay)
1585 val |= PHY_PTP_1STEP_PD_ADD_PD_M;
1586 val |= PHY_PTP_1STEP_PD_DLY_V_M;
1587 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
1588 if (err)
1589 return err;
1590
1591 val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
1592 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val);
1593 if (err)
1594 return err;
1595
1596 addr = PHY_MAC_XIF_MODE;
1597 err = ice_read_mac_reg_eth56g(hw, port, addr, &val);
1598 if (err)
1599 return err;
1600
1601 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M |
1602 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M);
1603
1604 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
1605 case ICE_ETH56G_LNK_SPD_1G:
1606 case ICE_ETH56G_LNK_SPD_2_5G:
1607 val |= PHY_MAC_XIF_GMII_TS_SEL_M;
1608 break;
1609 default:
1610 break;
1611 }
1612
1613 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) |
1614 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
1615 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
1616
1617 return ice_write_mac_reg_eth56g(hw, port, addr, val);
1618 }
1619
1620 /**
1621 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
1622 * @a: multiplier value
1623 * @b: multiplicand value
1624 *
1625 * Return: result of multiplication
1626 */
mul_u32_u32_fx_q9(u32 a,u32 b)1627 static u32 mul_u32_u32_fx_q9(u32 a, u32 b)
1628 {
1629 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
1630 }
1631
1632 /**
1633 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
1634 * @a: first value
1635 * @b: second value
1636 *
1637 * Return: result of addition
1638 */
add_u32_u32_fx(u32 a,u32 b)1639 static u32 add_u32_u32_fx(u32 a, u32 b)
1640 {
1641 return lower_32_bits(((u64)a + b));
1642 }
1643
1644 /**
1645 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
1646 * @hw: pointer to the HW struct
1647 * @port: port to configure
1648 * @bs: bitslip multiplier
1649 * @fc: FC-FEC enabled
1650 * @rs: RS-FEC enabled
1651 * @spd: link speed
1652 *
1653 * Return: calculated bitslip value
1654 */
ice_ptp_calc_bitslip_eth56g(struct ice_hw * hw,u8 port,u32 bs,bool fc,bool rs,enum ice_eth56g_link_spd spd)1655 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
1656 bool fc, bool rs,
1657 enum ice_eth56g_link_spd spd)
1658 {
1659 u32 bitslip;
1660 int err;
1661
1662 if (!bs || rs)
1663 return 0;
1664
1665 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) {
1666 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
1667 &bitslip);
1668 } else {
1669 u8 quad_lane = port % ICE_PORTS_PER_QUAD;
1670 u32 addr;
1671
1672 addr = PHY_REG_SD_BIT_SLIP(quad_lane);
1673 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip);
1674 }
1675 if (err)
1676 return 0;
1677
1678 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) {
1679 /* Bitslip register value of 0 corresponds to 10 so substitute
1680 * it for calculations
1681 */
1682 bitslip = 10;
1683 } else if (spd == ICE_ETH56G_LNK_SPD_10G ||
1684 spd == ICE_ETH56G_LNK_SPD_25G) {
1685 if (fc)
1686 bitslip = bitslip * 2 + 32;
1687 else
1688 bitslip = (u32)((s32)bitslip * -1 + 20);
1689 }
1690
1691 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W;
1692 return mul_u32_u32_fx_q9(bitslip, bs);
1693 }
1694
1695 /**
1696 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
1697 * @hw: pointer to the HW struct
1698 * @port: port to configure
1699 * @ds: deskew multiplier
1700 * @rs: RS-FEC enabled
1701 * @spd: link speed
1702 *
1703 * Return: calculated deskew value
1704 */
ice_ptp_calc_deskew_eth56g(struct ice_hw * hw,u8 port,u32 ds,bool rs,enum ice_eth56g_link_spd spd)1705 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
1706 bool rs, enum ice_eth56g_link_spd spd)
1707 {
1708 u32 deskew_i, deskew_f;
1709 int err;
1710
1711 if (!ds)
1712 return 0;
1713
1714 read_poll_timeout(ice_read_ptp_reg_eth56g, err,
1715 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500,
1716 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0,
1717 &deskew_i);
1718 if (err)
1719 return err;
1720
1721 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i);
1722 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i);
1723
1724 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2)
1725 ds = 0x633; /* 3.1 */
1726 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G)
1727 ds = 0x31b; /* 1.552 */
1728
1729 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i);
1730 /* Shift 3 fractional bits to the end of the integer part */
1731 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
1732 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
1733 }
1734
1735 /**
1736 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
1737 * @hw: pointer to the HW struct
1738 * @port: port to configure
1739 * @spd: link speed
1740 * @cfg: structure to store output values
1741 * @fc: FC-FEC enabled
1742 * @rs: RS-FEC enabled
1743 *
1744 * Return:
1745 * * %0 - success
1746 * * %other - failed to write to PHY
1747 */
ice_phy_set_offsets_eth56g(struct ice_hw * hw,u8 port,enum ice_eth56g_link_spd spd,const struct ice_eth56g_mac_reg_cfg * cfg,bool fc,bool rs)1748 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
1749 enum ice_eth56g_link_spd spd,
1750 const struct ice_eth56g_mac_reg_cfg *cfg,
1751 bool fc, bool rs)
1752 {
1753 u32 rx_offset, tx_offset, bs_ds;
1754 bool onestep, sfd;
1755
1756 onestep = hw->ptp.phy.eth56g.onestep_ena;
1757 sfd = hw->ptp.phy.eth56g.sfd_ena;
1758 bs_ds = cfg->rx_offset.bs_ds;
1759
1760 if (fc)
1761 rx_offset = cfg->rx_offset.fc;
1762 else if (rs)
1763 rx_offset = cfg->rx_offset.rs;
1764 else
1765 rx_offset = cfg->rx_offset.no_fec;
1766
1767 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes);
1768 if (sfd)
1769 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd);
1770
1771 if (spd < ICE_ETH56G_LNK_SPD_40G)
1772 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs,
1773 spd);
1774 else
1775 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd);
1776 rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
1777 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
1778 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
1779
1780 if (fc)
1781 tx_offset = cfg->tx_offset.fc;
1782 else if (rs)
1783 tx_offset = cfg->tx_offset.rs;
1784 else
1785 tx_offset = cfg->tx_offset.no_fec;
1786 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd +
1787 cfg->tx_offset.onestep * onestep;
1788
1789 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset);
1790 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset);
1791 }
1792
1793 /**
1794 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
1795 * @hw: Pointer to the HW struct
1796 * @port: Port to configure
1797 *
1798 * Return:
1799 * * %0 - success
1800 * * %other - failed to write to PHY
1801 */
ice_phy_cfg_mac_eth56g(struct ice_hw * hw,u8 port)1802 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)
1803 {
1804 const struct ice_eth56g_mac_reg_cfg *cfg;
1805 enum ice_eth56g_link_spd spd;
1806 struct ice_link_status *li;
1807 bool fc = false;
1808 bool rs = false;
1809 bool onestep;
1810 u32 val;
1811 int err;
1812
1813 onestep = hw->ptp.phy.eth56g.onestep_ena;
1814 li = &hw->port_info->phy.link_info;
1815 spd = ice_phy_get_speed_eth56g(li);
1816 if (!!(li->an_info & ICE_AQ_FEC_EN)) {
1817 if (spd == ICE_ETH56G_LNK_SPD_10G) {
1818 fc = true;
1819 } else {
1820 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN);
1821 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN);
1822 }
1823 }
1824 cfg = ð56g_mac_cfg[spd];
1825
1826 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0);
1827 if (err)
1828 return err;
1829
1830 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0);
1831 if (err)
1832 return err;
1833
1834 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M,
1835 cfg->tx_mode.def + rs * cfg->tx_mode.rs) |
1836 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) |
1837 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M,
1838 cfg->tx_cw_dly.def +
1839 onestep * cfg->tx_cw_dly.onestep) |
1840 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M,
1841 cfg->rx_mode.def + rs * cfg->rx_mode.rs) |
1842 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M,
1843 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) |
1844 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M,
1845 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) |
1846 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk);
1847 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val);
1848 if (err)
1849 return err;
1850
1851 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME,
1852 cfg->blktime);
1853 if (err)
1854 return err;
1855
1856 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs);
1857 if (err)
1858 return err;
1859
1860 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs)
1861 val = 0;
1862 else
1863 val = cfg->mktime;
1864
1865 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val);
1866 }
1867
1868 /**
1869 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
1870 * @hw: pointer to the HW struct
1871 * @port: the timestamp port
1872 * @ena: enable or disable interrupt
1873 * @threshold: interrupt threshold
1874 *
1875 * The threshold cannot be 0 while the interrupt is enabled.
1876 *
1877 * Configure TX timestamp interrupt for the specified port
1878 *
1879 * Return:
1880 * * %0 - success
1881 * * %other - PHY read/write failed
1882 */
ice_phy_cfg_intr_eth56g(struct ice_hw * hw,u8 port,bool ena,u8 threshold)1883 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
1884 {
1885 int err;
1886 u32 val;
1887
1888 if (ena && !threshold)
1889 return -EINVAL;
1890
1891 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
1892 if (err)
1893 return err;
1894
1895 val &= ~PHY_TS_INT_CONFIG_ENA_M;
1896 if (ena) {
1897 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
1898 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
1899 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG,
1900 val);
1901 if (err) {
1902 ice_debug(hw, ICE_DBG_PTP,
1903 "Failed to update 'threshold' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n",
1904 port, !!ena, threshold);
1905 return err;
1906 }
1907 val |= PHY_TS_INT_CONFIG_ENA_M;
1908 }
1909
1910 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
1911 if (err) {
1912 ice_debug(hw, ICE_DBG_PTP,
1913 "Failed to update 'ena' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n",
1914 port, !!ena, threshold);
1915 return err;
1916 }
1917
1918 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
1919 if (err) {
1920 ice_debug(hw, ICE_DBG_PTP,
1921 "Failed to read PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\n",
1922 port, !!ena, threshold);
1923 return err;
1924 }
1925
1926 return 0;
1927 }
1928
1929 /**
1930 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
1931 * @hw: pointer to the HW struct
1932 * @port: the PHY port to read
1933 * @phy_time: on return, the 64bit PHY timer value
1934 * @phc_time: on return, the lower 64bits of PHC time
1935 *
1936 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
1937 * and PHC timer values.
1938 *
1939 * Return:
1940 * * %0 - success
1941 * * %other - PHY read/write failed
1942 */
ice_read_phy_and_phc_time_eth56g(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)1943 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port,
1944 u64 *phy_time, u64 *phc_time)
1945 {
1946 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
1947 u64 tx_time, rx_time;
1948 u32 zo, lo;
1949 u8 tmr_idx;
1950 int err;
1951
1952 tmr_idx = ice_get_ptp_src_clock_index(hw);
1953
1954 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
1955 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
1956
1957 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
1958 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
1959 if (err)
1960 return err;
1961
1962 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
1963 ice_ptp_exec_tmr_cmd(hw);
1964
1965 /* Read the captured PHC time from the shadow time registers */
1966 if (ice_is_primary(hw)) {
1967 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
1968 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
1969 } else {
1970 zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx));
1971 lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx));
1972 }
1973 *phc_time = (u64)lo << 32 | zo;
1974
1975 /* Read the captured PHY time from the PHY shadow registers */
1976 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
1977 if (err)
1978 return err;
1979
1980 /* If the PHY Tx and Rx timers don't match, log a warning message.
1981 * Note that this should not happen in normal circumstances since the
1982 * driver always programs them together.
1983 */
1984 if (tx_time != rx_time)
1985 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
1986 port, tx_time, rx_time);
1987
1988 *phy_time = tx_time;
1989
1990 return 0;
1991 }
1992
1993 /**
1994 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
1995 * @hw: pointer to the HW struct
1996 * @port: the PHY port to synchronize
1997 *
1998 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
1999 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
2000 * simultaneous read of the PHY timer and PHC timer. Then we use the
2001 * difference to calculate an appropriate 2s complement addition to add
2002 * to the PHY timer in order to ensure it reads the same value as the
2003 * primary PHC timer.
2004 *
2005 * Return:
2006 * * %0 - success
2007 * * %-EBUSY- failed to acquire PTP semaphore
2008 * * %other - PHY read/write failed
2009 */
ice_sync_phy_timer_eth56g(struct ice_hw * hw,u8 port)2010 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2011 {
2012 u64 phc_time, phy_time, difference;
2013 int err;
2014
2015 if (!ice_ptp_lock(hw)) {
2016 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2017 return -EBUSY;
2018 }
2019
2020 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2021 if (err)
2022 goto err_unlock;
2023
2024 /* Calculate the amount required to add to the port time in order for
2025 * it to match the PHC time.
2026 *
2027 * Note that the port adjustment is done using 2s complement
2028 * arithmetic. This is convenient since it means that we can simply
2029 * calculate the difference between the PHC time and the port time,
2030 * and it will be interpreted correctly.
2031 */
2032
2033 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2034 difference = phc_time - phy_time;
2035
2036 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference);
2037 if (err)
2038 goto err_unlock;
2039
2040 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2041 if (err)
2042 goto err_unlock;
2043
2044 /* Issue the sync to activate the time adjustment */
2045 ice_ptp_exec_tmr_cmd(hw);
2046
2047 /* Re-capture the timer values to flush the command registers and
2048 * verify that the time was properly adjusted.
2049 */
2050 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2051 if (err)
2052 goto err_unlock;
2053
2054 dev_info(ice_hw_to_dev(hw),
2055 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2056 port, phy_time, phc_time);
2057
2058 err_unlock:
2059 ice_ptp_unlock(hw);
2060 return err;
2061 }
2062
2063 /**
2064 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2065 * @hw: pointer to the HW struct
2066 * @port: the PHY port to stop
2067 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
2068 *
2069 * Stop the clock of a PHY port. This must be done as part of the flow to
2070 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2071 * initialized or when link speed changes.
2072 *
2073 * Return:
2074 * * %0 - success
2075 * * %other - failed to write to PHY
2076 */
ice_stop_phy_timer_eth56g(struct ice_hw * hw,u8 port,bool soft_reset)2077 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
2078 {
2079 int err;
2080
2081 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
2082 if (err)
2083 return err;
2084
2085 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
2086 if (err)
2087 return err;
2088
2089 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2090
2091 return 0;
2092 }
2093
2094 /**
2095 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2096 * @hw: pointer to the HW struct
2097 * @port: the PHY port to start
2098 *
2099 * Start the clock of a PHY port. This must be done as part of the flow to
2100 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2101 * initialized or when link speed changes.
2102 *
2103 * Return:
2104 * * %0 - success
2105 * * %other - PHY read/write failed
2106 */
ice_start_phy_timer_eth56g(struct ice_hw * hw,u8 port)2107 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2108 {
2109 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
2110 u32 lo, hi;
2111 u64 incval;
2112 u8 tmr_idx;
2113 int err;
2114
2115 tmr_idx = ice_get_ptp_src_clock_index(hw);
2116
2117 err = ice_stop_phy_timer_eth56g(hw, port, false);
2118 if (err)
2119 return err;
2120
2121 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2122
2123 err = ice_phy_cfg_parpcs_eth56g(hw, port);
2124 if (err)
2125 return err;
2126
2127 err = ice_phy_cfg_ptp_1step_eth56g(hw, port);
2128 if (err)
2129 return err;
2130
2131 err = ice_phy_cfg_mac_eth56g(hw, port);
2132 if (err)
2133 return err;
2134
2135 if (ice_is_primary(hw)) {
2136 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2137 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2138 } else {
2139 lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx));
2140 hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx));
2141 }
2142 incval = (u64)hi << 32 | lo;
2143
2144 if (!ice_ptp_lock(hw)) {
2145 dev_err(ice_hw_to_dev(hw), "Failed to acquire PTP semaphore\n");
2146 return -EBUSY;
2147 }
2148
2149 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval);
2150 if (err)
2151 goto err_ptp_unlock;
2152
2153 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2154 if (err)
2155 goto err_ptp_unlock;
2156
2157 ice_ptp_exec_tmr_cmd(hw);
2158
2159 ice_ptp_unlock(hw);
2160
2161 err = ice_sync_phy_timer_eth56g(hw, port);
2162 if (err)
2163 return err;
2164
2165 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
2166 if (err)
2167 return err;
2168
2169 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
2170 if (err)
2171 return err;
2172
2173 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2174
2175 return 0;
2176
2177 err_ptp_unlock:
2178 ice_ptp_unlock(hw);
2179 return err;
2180 }
2181
2182 /**
2183 * ice_check_phy_tx_tstamp_ready_eth56g - Check Tx memory status for all ports
2184 * @hw: pointer to the HW struct
2185 *
2186 * Check the PHY_REG_TX_MEMORY_STATUS for all ports. A set bit indicates
2187 * a waiting timestamp.
2188 *
2189 * Return: 1 if any port has at least one timestamp ready bit set,
2190 * 0 otherwise, and a negative error code if unable to read the bitmap.
2191 */
ice_check_phy_tx_tstamp_ready_eth56g(struct ice_hw * hw)2192 static int ice_check_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw)
2193 {
2194 int port;
2195
2196 for (port = 0; port < hw->ptp.num_lports; port++) {
2197 u64 tstamp_ready;
2198 int err;
2199
2200 err = ice_get_phy_tx_tstamp_ready(hw, port, &tstamp_ready);
2201 if (err)
2202 return err;
2203
2204 if (tstamp_ready)
2205 return 1;
2206 }
2207
2208 return 0;
2209 }
2210
2211 /**
2212 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2213 * @hw: pointer to the HW struct
2214 * @ts_status: the timestamp mask pointer
2215 *
2216 * Read the PHY Tx timestamp status mask indicating which ports have Tx
2217 * timestamps available.
2218 *
2219 * Return:
2220 * * %0 - success
2221 * * %other - failed to read from PHY
2222 */
ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw * hw,u32 * ts_status)2223 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
2224 {
2225 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g;
2226 u8 phy, mask;
2227 u32 status;
2228
2229 mask = (1 << hw->ptp.ports_per_phy) - 1;
2230 *ts_status = 0;
2231
2232 for (phy = 0; phy < params->num_phys; phy++) {
2233 u8 port;
2234 int err;
2235
2236 /* ice_read_phy_eth56g expects a port index, so use the first
2237 * port of the PHY
2238 */
2239 port = phy * hw->ptp.ports_per_phy;
2240
2241 err = ice_read_phy_eth56g(hw, port, PHY_PTP_INT_STATUS, &status);
2242 if (err)
2243 return err;
2244
2245 *ts_status |= (status & mask) << port;
2246 }
2247
2248 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
2249
2250 return 0;
2251 }
2252
2253 /**
2254 * ice_ptp_phy_soft_reset_eth56g - Perform a PHY soft reset on ETH56G
2255 * @hw: pointer to the HW structure
2256 * @port: PHY port number
2257 *
2258 * Trigger a soft reset of the ETH56G PHY by toggling the soft reset
2259 * bit in the PHY global register. The reset sequence consists of:
2260 * 1. Clearing the soft reset bit
2261 * 2. Asserting the soft reset bit
2262 * 3. Clearing the soft reset bit again
2263 *
2264 * Short delays are inserted between each step to allow the hardware
2265 * to settle. This provides a controlled way to reinitialize the PHY
2266 * without requiring a full device reset.
2267 *
2268 * Return: 0 on success, or a negative error code on failure when
2269 * reading or writing the PHY register.
2270 */
ice_ptp_phy_soft_reset_eth56g(struct ice_hw * hw,u8 port)2271 int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port)
2272 {
2273 u32 global_val;
2274 int err;
2275
2276 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, &global_val);
2277 if (err) {
2278 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_REG_GLOBAL for port %d, err %d\n",
2279 port, err);
2280 return err;
2281 }
2282
2283 global_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;
2284 ice_debug(hw, ICE_DBG_PTP, "Clearing soft reset bit for port %d, val: 0x%x\n",
2285 port, global_val);
2286 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);
2287 if (err) {
2288 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
2289 port, err);
2290 return err;
2291 }
2292
2293 usleep_range(5000, 6000);
2294
2295 global_val |= PHY_REG_GLOBAL_SOFT_RESET_M;
2296 ice_debug(hw, ICE_DBG_PTP, "Set soft reset bit for port %d, val: 0x%x\n",
2297 port, global_val);
2298 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);
2299 if (err) {
2300 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
2301 port, err);
2302 return err;
2303 }
2304 usleep_range(5000, 6000);
2305
2306 global_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;
2307 ice_debug(hw, ICE_DBG_PTP, "Clear soft reset bit for port %d, val: 0x%x\n",
2308 port, global_val);
2309 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);
2310 if (err)
2311 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
2312 port, err);
2313 return err;
2314 }
2315
2316 /**
2317 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2318 * @hw: pointer to the HW struct
2319 * @port: the PHY port to read from
2320 * @tstamp_ready: contents of the Tx memory status register
2321 *
2322 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
2323 * the PHY are ready. A set bit means the corresponding timestamp is valid and
2324 * ready to be captured from the PHY timestamp block.
2325 *
2326 * Return:
2327 * * %0 - success
2328 * * %other - failed to read from PHY
2329 */
ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw * hw,u8 port,u64 * tstamp_ready)2330 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
2331 u64 *tstamp_ready)
2332 {
2333 int err;
2334
2335 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
2336 tstamp_ready);
2337 if (err) {
2338 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
2339 port, err);
2340 return err;
2341 }
2342
2343 return 0;
2344 }
2345
2346 /**
2347 * ice_ptp_init_phy_e825 - initialize PHY parameters
2348 * @hw: pointer to the HW struct
2349 */
ice_ptp_init_phy_e825(struct ice_hw * hw)2350 static void ice_ptp_init_phy_e825(struct ice_hw *hw)
2351 {
2352 struct ice_ptp_hw *ptp = &hw->ptp;
2353 struct ice_eth56g_params *params;
2354
2355 params = &ptp->phy.eth56g;
2356 params->onestep_ena = false;
2357 params->peer_delay = 0;
2358 params->sfd_ena = false;
2359 params->num_phys = 2;
2360 ptp->ports_per_phy = 4;
2361 ptp->num_lports = params->num_phys * ptp->ports_per_phy;
2362 }
2363
2364 /* E822 family functions
2365 *
2366 * The following functions operate on the E822 family of devices.
2367 */
2368
2369 /**
2370 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2371 * @hw: pointer to the HW struct
2372 * @msg: the PHY message buffer to fill in
2373 * @port: the port to access
2374 * @offset: the register offset
2375 */
ice_fill_phy_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 port,u16 offset)2376 static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
2377 struct ice_sbq_msg_input *msg, u8 port,
2378 u16 offset)
2379 {
2380 int phy_port, quadtype;
2381
2382 phy_port = port % hw->ptp.ports_per_phy;
2383 quadtype = ICE_GET_QUAD_NUM(port) %
2384 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
2385
2386 if (quadtype == 0) {
2387 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
2388 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
2389 } else {
2390 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
2391 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
2392 }
2393
2394 msg->dest_dev = ice_sbq_dev_phy_0;
2395 }
2396
2397 /**
2398 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2399 * @low_addr: the low address to check
2400 * @high_addr: on return, contains the high address of the 64bit register
2401 *
2402 * Checks if the provided low address is one of the known 64bit PHY values
2403 * represented as two 32bit registers. If it is, return the appropriate high
2404 * register offset to use.
2405 */
ice_is_64b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2406 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2407 {
2408 switch (low_addr) {
2409 case P_REG_PAR_PCS_TX_OFFSET_L:
2410 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
2411 return true;
2412 case P_REG_PAR_PCS_RX_OFFSET_L:
2413 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
2414 return true;
2415 case P_REG_PAR_TX_TIME_L:
2416 *high_addr = P_REG_PAR_TX_TIME_U;
2417 return true;
2418 case P_REG_PAR_RX_TIME_L:
2419 *high_addr = P_REG_PAR_RX_TIME_U;
2420 return true;
2421 case P_REG_TOTAL_TX_OFFSET_L:
2422 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
2423 return true;
2424 case P_REG_TOTAL_RX_OFFSET_L:
2425 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
2426 return true;
2427 case P_REG_UIX66_10G_40G_L:
2428 *high_addr = P_REG_UIX66_10G_40G_U;
2429 return true;
2430 case P_REG_UIX66_25G_100G_L:
2431 *high_addr = P_REG_UIX66_25G_100G_U;
2432 return true;
2433 case P_REG_TX_CAPTURE_L:
2434 *high_addr = P_REG_TX_CAPTURE_U;
2435 return true;
2436 case P_REG_RX_CAPTURE_L:
2437 *high_addr = P_REG_RX_CAPTURE_U;
2438 return true;
2439 case P_REG_TX_TIMER_INC_PRE_L:
2440 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
2441 return true;
2442 case P_REG_RX_TIMER_INC_PRE_L:
2443 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
2444 return true;
2445 default:
2446 return false;
2447 }
2448 }
2449
2450 /**
2451 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2452 * @low_addr: the low address to check
2453 * @high_addr: on return, contains the high address of the 40bit value
2454 *
2455 * Checks if the provided low address is one of the known 40bit PHY values
2456 * split into two registers with the lower 8 bits in the low register and the
2457 * upper 32 bits in the high register. If it is, return the appropriate high
2458 * register offset to use.
2459 */
ice_is_40b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2460 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2461 {
2462 switch (low_addr) {
2463 case P_REG_TIMETUS_L:
2464 *high_addr = P_REG_TIMETUS_U;
2465 return true;
2466 case P_REG_PAR_RX_TUS_L:
2467 *high_addr = P_REG_PAR_RX_TUS_U;
2468 return true;
2469 case P_REG_PAR_TX_TUS_L:
2470 *high_addr = P_REG_PAR_TX_TUS_U;
2471 return true;
2472 case P_REG_PCS_RX_TUS_L:
2473 *high_addr = P_REG_PCS_RX_TUS_U;
2474 return true;
2475 case P_REG_PCS_TX_TUS_L:
2476 *high_addr = P_REG_PCS_TX_TUS_U;
2477 return true;
2478 case P_REG_DESK_PAR_RX_TUS_L:
2479 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
2480 return true;
2481 case P_REG_DESK_PAR_TX_TUS_L:
2482 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
2483 return true;
2484 case P_REG_DESK_PCS_RX_TUS_L:
2485 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
2486 return true;
2487 case P_REG_DESK_PCS_TX_TUS_L:
2488 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
2489 return true;
2490 default:
2491 return false;
2492 }
2493 }
2494
2495 /**
2496 * ice_read_phy_reg_e82x - Read a PHY register
2497 * @hw: pointer to the HW struct
2498 * @port: PHY port to read from
2499 * @offset: PHY register offset to read
2500 * @val: on return, the contents read from the PHY
2501 *
2502 * Read a PHY register for the given port over the device sideband queue.
2503 */
2504 static int
ice_read_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 * val)2505 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
2506 {
2507 struct ice_sbq_msg_input msg = {0};
2508 int err;
2509
2510 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2511 msg.opcode = ice_sbq_msg_rd;
2512
2513 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
2514 if (err) {
2515 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2516 err);
2517 return err;
2518 }
2519
2520 *val = msg.data;
2521
2522 return 0;
2523 }
2524
2525 /**
2526 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2527 * @hw: pointer to the HW struct
2528 * @port: PHY port to read from
2529 * @low_addr: offset of the lower register to read from
2530 * @val: on return, the contents of the 64bit value from the PHY registers
2531 *
2532 * Reads the two registers associated with a 64bit value and returns it in the
2533 * val pointer. The offset always specifies the lower register offset to use.
2534 * The high offset is looked up. This function only operates on registers
2535 * known to be two parts of a 64bit value.
2536 */
2537 static int
ice_read_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)2538 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
2539 {
2540 u32 low, high;
2541 u16 high_addr;
2542 int err;
2543
2544 /* Only operate on registers known to be split into two 32bit
2545 * registers.
2546 */
2547 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
2548 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
2549 low_addr);
2550 return -EINVAL;
2551 }
2552
2553 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low);
2554 if (err) {
2555 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
2556 low_addr, err);
2557 return err;
2558 }
2559
2560 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high);
2561 if (err) {
2562 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
2563 high_addr, err);
2564 return err;
2565 }
2566
2567 *val = (u64)high << 32 | low;
2568
2569 return 0;
2570 }
2571
2572 /**
2573 * ice_write_phy_reg_e82x - Write a PHY register
2574 * @hw: pointer to the HW struct
2575 * @port: PHY port to write to
2576 * @offset: PHY register offset to write
2577 * @val: The value to write to the register
2578 *
2579 * Write a PHY register for the given port over the device sideband queue.
2580 */
2581 static int
ice_write_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 val)2582 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
2583 {
2584 struct ice_sbq_msg_input msg = {0};
2585 int err;
2586
2587 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2588 msg.opcode = ice_sbq_msg_wr;
2589 msg.data = val;
2590
2591 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
2592 if (err) {
2593 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2594 err);
2595 return err;
2596 }
2597
2598 return 0;
2599 }
2600
2601 /**
2602 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
2603 * @hw: pointer to the HW struct
2604 * @port: port to write to
2605 * @low_addr: offset of the low register
2606 * @val: 40b value to write
2607 *
2608 * Write the provided 40b value to the two associated registers by splitting
2609 * it up into two chunks, the lower 8 bits and the upper 32 bits.
2610 */
2611 static int
ice_write_40b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)2612 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
2613 {
2614 u32 low, high;
2615 u16 high_addr;
2616 int err;
2617
2618 /* Only operate on registers known to be split into a lower 8 bit
2619 * register and an upper 32 bit register.
2620 */
2621 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) {
2622 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
2623 low_addr);
2624 return -EINVAL;
2625 }
2626 low = FIELD_GET(P_REG_40B_LOW_M, val);
2627 high = (u32)(val >> P_REG_40B_HIGH_S);
2628
2629 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
2630 if (err) {
2631 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
2632 low_addr, err);
2633 return err;
2634 }
2635
2636 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
2637 if (err) {
2638 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
2639 high_addr, err);
2640 return err;
2641 }
2642
2643 return 0;
2644 }
2645
2646 /**
2647 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
2648 * @hw: pointer to the HW struct
2649 * @port: PHY port to read from
2650 * @low_addr: offset of the lower register to read from
2651 * @val: the contents of the 64bit value to write to PHY
2652 *
2653 * Write the 64bit value to the two associated 32bit PHY registers. The offset
2654 * is always specified as the lower register, and the high address is looked
2655 * up. This function only operates on registers known to be two parts of
2656 * a 64bit value.
2657 */
2658 static int
ice_write_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)2659 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
2660 {
2661 u32 low, high;
2662 u16 high_addr;
2663 int err;
2664
2665 /* Only operate on registers known to be split into two 32bit
2666 * registers.
2667 */
2668 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
2669 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
2670 low_addr);
2671 return -EINVAL;
2672 }
2673
2674 low = lower_32_bits(val);
2675 high = upper_32_bits(val);
2676
2677 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
2678 if (err) {
2679 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
2680 low_addr, err);
2681 return err;
2682 }
2683
2684 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
2685 if (err) {
2686 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
2687 high_addr, err);
2688 return err;
2689 }
2690
2691 return 0;
2692 }
2693
2694 /**
2695 * ice_fill_quad_msg_e82x - Fill message data for quad register access
2696 * @hw: pointer to the HW struct
2697 * @msg: the PHY message buffer to fill in
2698 * @quad: the quad to access
2699 * @offset: the register offset
2700 *
2701 * Fill a message buffer for accessing a register in a quad shared between
2702 * multiple PHYs.
2703 *
2704 * Return:
2705 * * %0 - OK
2706 * * %-EINVAL - invalid quad number
2707 */
ice_fill_quad_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 quad,u16 offset)2708 static int ice_fill_quad_msg_e82x(struct ice_hw *hw,
2709 struct ice_sbq_msg_input *msg, u8 quad,
2710 u16 offset)
2711 {
2712 u32 addr;
2713
2714 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports))
2715 return -EINVAL;
2716
2717 msg->dest_dev = ice_sbq_dev_phy_0;
2718
2719 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy)))
2720 addr = Q_0_BASE + offset;
2721 else
2722 addr = Q_1_BASE + offset;
2723
2724 msg->msg_addr_low = lower_16_bits(addr);
2725 msg->msg_addr_high = upper_16_bits(addr);
2726
2727 return 0;
2728 }
2729
2730 /**
2731 * ice_read_quad_reg_e82x - Read a PHY quad register
2732 * @hw: pointer to the HW struct
2733 * @quad: quad to read from
2734 * @offset: quad register offset to read
2735 * @val: on return, the contents read from the quad
2736 *
2737 * Read a quad register over the device sideband queue. Quad registers are
2738 * shared between multiple PHYs.
2739 */
2740 int
ice_read_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 * val)2741 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
2742 {
2743 struct ice_sbq_msg_input msg = {0};
2744 int err;
2745
2746 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
2747 if (err)
2748 return err;
2749
2750 msg.opcode = ice_sbq_msg_rd;
2751
2752 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
2753 if (err) {
2754 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2755 err);
2756 return err;
2757 }
2758
2759 *val = msg.data;
2760
2761 return 0;
2762 }
2763
2764 /**
2765 * ice_write_quad_reg_e82x - Write a PHY quad register
2766 * @hw: pointer to the HW struct
2767 * @quad: quad to write to
2768 * @offset: quad register offset to write
2769 * @val: The value to write to the register
2770 *
2771 * Write a quad register over the device sideband queue. Quad registers are
2772 * shared between multiple PHYs.
2773 */
2774 int
ice_write_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 val)2775 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
2776 {
2777 struct ice_sbq_msg_input msg = {0};
2778 int err;
2779
2780 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
2781 if (err)
2782 return err;
2783
2784 msg.opcode = ice_sbq_msg_wr;
2785 msg.data = val;
2786
2787 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
2788 if (err) {
2789 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2790 err);
2791 return err;
2792 }
2793
2794 return 0;
2795 }
2796
2797 /**
2798 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
2799 * @hw: pointer to the HW struct
2800 * @quad: the quad to read from
2801 * @idx: the timestamp index to read
2802 * @tstamp: on return, the 40bit timestamp value
2803 *
2804 * Read a 40bit timestamp value out of the two associated registers in the
2805 * quad memory block that is shared between the internal PHYs of the E822
2806 * family of devices.
2807 */
2808 static int
ice_read_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx,u64 * tstamp)2809 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
2810 {
2811 u16 lo_addr, hi_addr;
2812 u32 lo, hi;
2813 int err;
2814
2815 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
2816 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
2817
2818 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);
2819 if (err) {
2820 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
2821 err);
2822 return err;
2823 }
2824
2825 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);
2826 if (err) {
2827 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
2828 err);
2829 return err;
2830 }
2831
2832 /* For E822 based internal PHYs, the timestamp is reported with the
2833 * lower 8 bits in the low register, and the upper 32 bits in the high
2834 * register.
2835 */
2836 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) |
2837 FIELD_PREP(PHY_40B_LOW_M, lo);
2838
2839 return 0;
2840 }
2841
2842 /**
2843 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
2844 * @hw: pointer to the HW struct
2845 * @quad: the quad to read from
2846 * @idx: the timestamp index to reset
2847 *
2848 * Read the timestamp out of the quad to clear its timestamp status bit from
2849 * the PHY quad block that is shared between the internal PHYs of the E822
2850 * devices.
2851 *
2852 * Note that unlike E810, software cannot directly write to the quad memory
2853 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function
2854 * to determine which timestamps are valid. Reading a timestamp auto-clears
2855 * the valid bit.
2856 *
2857 * To directly clear the contents of the timestamp block entirely, discarding
2858 * all timestamp data at once, software should instead use
2859 * ice_ptp_reset_ts_memory_quad_e82x().
2860 *
2861 * This function should only be called on an idx whose bit is set according to
2862 * ice_get_phy_tx_tstamp_ready().
2863 */
2864 static int
ice_clear_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx)2865 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)
2866 {
2867 u64 unused_tstamp;
2868 int err;
2869
2870 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);
2871 if (err) {
2872 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
2873 quad, idx, err);
2874 return err;
2875 }
2876
2877 return 0;
2878 }
2879
2880 /**
2881 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
2882 * @hw: pointer to the HW struct
2883 * @quad: the quad to read from
2884 *
2885 * Clear all timestamps from the PHY quad block that is shared between the
2886 * internal PHYs on the E822 devices.
2887 */
ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw * hw,u8 quad)2888 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
2889 {
2890 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
2891 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
2892 }
2893
2894 /**
2895 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
2896 * @hw: pointer to the HW struct
2897 */
ice_ptp_reset_ts_memory_e82x(struct ice_hw * hw)2898 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
2899 {
2900 unsigned int quad;
2901
2902 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++)
2903 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
2904 }
2905
2906 /**
2907 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
2908 * @hw: pointer to the HW struct
2909 *
2910 * Set the window length used for the vernier port calibration process.
2911 */
ice_ptp_set_vernier_wl(struct ice_hw * hw)2912 static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
2913 {
2914 u8 port;
2915
2916 for (port = 0; port < hw->ptp.num_lports; port++) {
2917 int err;
2918
2919 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
2920 PTP_VERNIER_WL);
2921 if (err) {
2922 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
2923 port, err);
2924 return err;
2925 }
2926 }
2927
2928 return 0;
2929 }
2930
2931 /**
2932 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
2933 * @hw: pointer to HW struct
2934 *
2935 * Perform PHC initialization steps specific to E822 devices.
2936 */
ice_ptp_init_phc_e82x(struct ice_hw * hw)2937 static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
2938 {
2939 u32 val;
2940
2941 /* Enable reading switch and PHY registers over the sideband queue */
2942 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
2943 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
2944 val = rd32(hw, PF_SB_REM_DEV_CTL);
2945 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
2946 wr32(hw, PF_SB_REM_DEV_CTL, val);
2947
2948 /* Set window length for all the ports */
2949 return ice_ptp_set_vernier_wl(hw);
2950 }
2951
2952 /**
2953 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
2954 * @hw: pointer to the HW struct
2955 * @time: Time to initialize the PHY port clocks to
2956 *
2957 * Program the PHY port registers with a new initial time value. The port
2958 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
2959 * command. The time value is the upper 32 bits of the PHY timer, usually in
2960 * units of nominal nanoseconds.
2961 */
2962 static int
ice_ptp_prep_phy_time_e82x(struct ice_hw * hw,u32 time)2963 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)
2964 {
2965 u64 phy_time;
2966 u8 port;
2967 int err;
2968
2969 /* The time represents the upper 32 bits of the PHY timer, so we need
2970 * to shift to account for this when programming.
2971 */
2972 phy_time = (u64)time << 32;
2973
2974 for (port = 0; port < hw->ptp.num_lports; port++) {
2975 /* Tx case */
2976 err = ice_write_64b_phy_reg_e82x(hw, port,
2977 P_REG_TX_TIMER_INC_PRE_L,
2978 phy_time);
2979 if (err)
2980 goto exit_err;
2981
2982 /* Rx case */
2983 err = ice_write_64b_phy_reg_e82x(hw, port,
2984 P_REG_RX_TIMER_INC_PRE_L,
2985 phy_time);
2986 if (err)
2987 goto exit_err;
2988 }
2989
2990 return 0;
2991
2992 exit_err:
2993 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
2994 port, err);
2995
2996 return err;
2997 }
2998
2999 /**
3000 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3001 * @hw: pointer to HW struct
3002 * @port: Port number to be programmed
3003 * @time: time in cycles to adjust the port Tx and Rx clocks
3004 *
3005 * Program the port for an atomic adjustment by writing the Tx and Rx timer
3006 * registers. The atomic adjustment won't be completed until the driver issues
3007 * an ICE_PTP_ADJ_TIME command.
3008 *
3009 * Note that time is not in units of nanoseconds. It is in clock time
3010 * including the lower sub-nanosecond portion of the port timer.
3011 *
3012 * Negative adjustments are supported using 2s complement arithmetic.
3013 */
3014 static int
ice_ptp_prep_port_adj_e82x(struct ice_hw * hw,u8 port,s64 time)3015 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time)
3016 {
3017 u32 l_time, u_time;
3018 int err;
3019
3020 l_time = lower_32_bits(time);
3021 u_time = upper_32_bits(time);
3022
3023 /* Tx case */
3024 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,
3025 l_time);
3026 if (err)
3027 goto exit_err;
3028
3029 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,
3030 u_time);
3031 if (err)
3032 goto exit_err;
3033
3034 /* Rx case */
3035 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,
3036 l_time);
3037 if (err)
3038 goto exit_err;
3039
3040 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,
3041 u_time);
3042 if (err)
3043 goto exit_err;
3044
3045 return 0;
3046
3047 exit_err:
3048 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
3049 port, err);
3050 return err;
3051 }
3052
3053 /**
3054 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3055 * @hw: pointer to HW struct
3056 * @adj: adjustment in nanoseconds
3057 *
3058 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
3059 * Tx and Rx port registers. The actual adjustment is completed by issuing an
3060 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
3061 */
3062 static int
ice_ptp_prep_phy_adj_e82x(struct ice_hw * hw,s32 adj)3063 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)
3064 {
3065 s64 cycles;
3066 u8 port;
3067
3068 /* The port clock supports adjustment of the sub-nanosecond portion of
3069 * the clock. We shift the provided adjustment in nanoseconds to
3070 * calculate the appropriate adjustment to program into the PHY ports.
3071 */
3072 if (adj > 0)
3073 cycles = (s64)adj << 32;
3074 else
3075 cycles = -(((s64)-adj) << 32);
3076
3077 for (port = 0; port < hw->ptp.num_lports; port++) {
3078 int err;
3079
3080 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
3081 if (err)
3082 return err;
3083 }
3084
3085 return 0;
3086 }
3087
3088 /**
3089 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3090 * @hw: pointer to HW struct
3091 * @incval: new increment value to prepare
3092 *
3093 * Prepare each of the PHY ports for a new increment value by programming the
3094 * port's TIMETUS registers. The new increment value will be updated after
3095 * issuing an ICE_PTP_INIT_INCVAL command.
3096 */
3097 static int
ice_ptp_prep_phy_incval_e82x(struct ice_hw * hw,u64 incval)3098 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)
3099 {
3100 int err;
3101 u8 port;
3102
3103 for (port = 0; port < hw->ptp.num_lports; port++) {
3104 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
3105 incval);
3106 if (err)
3107 goto exit_err;
3108 }
3109
3110 return 0;
3111
3112 exit_err:
3113 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
3114 port, err);
3115
3116 return err;
3117 }
3118
3119 /**
3120 * ice_ptp_read_port_capture - Read a port's local time capture
3121 * @hw: pointer to HW struct
3122 * @port: Port number to read
3123 * @tx_ts: on return, the Tx port time capture
3124 * @rx_ts: on return, the Rx port time capture
3125 *
3126 * Read the port's Tx and Rx local time capture values.
3127 *
3128 * Note this has no equivalent for the E810 devices.
3129 */
3130 static int
ice_ptp_read_port_capture(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)3131 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
3132 {
3133 int err;
3134
3135 /* Tx case */
3136 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
3137 if (err) {
3138 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
3139 err);
3140 return err;
3141 }
3142
3143 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
3144 (unsigned long long)*tx_ts);
3145
3146 /* Rx case */
3147 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
3148 if (err) {
3149 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
3150 err);
3151 return err;
3152 }
3153
3154 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
3155 (unsigned long long)*rx_ts);
3156
3157 return 0;
3158 }
3159
3160 /**
3161 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3162 * @hw: pointer to HW struct
3163 * @port: Port to which cmd has to be sent
3164 * @cmd: Command to be sent to the port
3165 *
3166 * Prepare the requested port for an upcoming timer sync command.
3167 *
3168 * Note there is no equivalent of this operation on E810, as that device
3169 * always handles all external PHYs internally.
3170 *
3171 * Return:
3172 * * %0 - success
3173 * * %other - failed to write to PHY
3174 */
ice_ptp_write_port_cmd_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)3175 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
3176 enum ice_ptp_tmr_cmd cmd)
3177 {
3178 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
3179 int err;
3180
3181 /* Tx case */
3182 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
3183 if (err) {
3184 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
3185 err);
3186 return err;
3187 }
3188
3189 /* Rx case */
3190 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD,
3191 val | TS_CMD_RX_TYPE);
3192 if (err) {
3193 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
3194 err);
3195 return err;
3196 }
3197
3198 return 0;
3199 }
3200
3201 /* E822 Vernier calibration functions
3202 *
3203 * The following functions are used as part of the vernier calibration of
3204 * a port. This calibration increases the precision of the timestamps on the
3205 * port.
3206 */
3207
3208 /**
3209 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3210 * @hw: pointer to HW struct
3211 * @port: the port to read from
3212 * @link_out: if non-NULL, holds link speed on success
3213 * @fec_out: if non-NULL, holds FEC algorithm on success
3214 *
3215 * Read the serdes data for the PHY port and extract the link speed and FEC
3216 * algorithm.
3217 */
3218 static int
ice_phy_get_speed_and_fec_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd * link_out,enum ice_ptp_fec_mode * fec_out)3219 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port,
3220 enum ice_ptp_link_spd *link_out,
3221 enum ice_ptp_fec_mode *fec_out)
3222 {
3223 enum ice_ptp_link_spd link;
3224 enum ice_ptp_fec_mode fec;
3225 u32 serdes;
3226 int err;
3227
3228 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes);
3229 if (err) {
3230 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
3231 return err;
3232 }
3233
3234 /* Determine the FEC algorithm */
3235 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
3236
3237 serdes &= P_REG_LINK_SPEED_SERDES_M;
3238
3239 /* Determine the link speed */
3240 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
3241 switch (serdes) {
3242 case ICE_PTP_SERDES_25G:
3243 link = ICE_PTP_LNK_SPD_25G_RS;
3244 break;
3245 case ICE_PTP_SERDES_50G:
3246 link = ICE_PTP_LNK_SPD_50G_RS;
3247 break;
3248 case ICE_PTP_SERDES_100G:
3249 link = ICE_PTP_LNK_SPD_100G_RS;
3250 break;
3251 default:
3252 return -EIO;
3253 }
3254 } else {
3255 switch (serdes) {
3256 case ICE_PTP_SERDES_1G:
3257 link = ICE_PTP_LNK_SPD_1G;
3258 break;
3259 case ICE_PTP_SERDES_10G:
3260 link = ICE_PTP_LNK_SPD_10G;
3261 break;
3262 case ICE_PTP_SERDES_25G:
3263 link = ICE_PTP_LNK_SPD_25G;
3264 break;
3265 case ICE_PTP_SERDES_40G:
3266 link = ICE_PTP_LNK_SPD_40G;
3267 break;
3268 case ICE_PTP_SERDES_50G:
3269 link = ICE_PTP_LNK_SPD_50G;
3270 break;
3271 default:
3272 return -EIO;
3273 }
3274 }
3275
3276 if (link_out)
3277 *link_out = link;
3278 if (fec_out)
3279 *fec_out = fec;
3280
3281 return 0;
3282 }
3283
3284 /**
3285 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3286 * @hw: pointer to HW struct
3287 * @port: to configure the quad for
3288 */
ice_phy_cfg_lane_e82x(struct ice_hw * hw,u8 port)3289 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)
3290 {
3291 enum ice_ptp_link_spd link_spd;
3292 int err;
3293 u32 val;
3294 u8 quad;
3295
3296 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL);
3297 if (err) {
3298 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
3299 err);
3300 return;
3301 }
3302
3303 quad = ICE_GET_QUAD_NUM(port);
3304
3305 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
3306 if (err) {
3307 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
3308 err);
3309 return;
3310 }
3311
3312 if (link_spd >= ICE_PTP_LNK_SPD_40G)
3313 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3314 else
3315 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3316
3317 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
3318 if (err) {
3319 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
3320 err);
3321 return;
3322 }
3323 }
3324
3325 /**
3326 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3327 * @hw: pointer to the HW structure
3328 * @port: the port to configure
3329 *
3330 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
3331 * hardware clock time units (TUs). That is, determine the number of TUs per
3332 * serdes unit interval, and program the UIX registers with this conversion.
3333 *
3334 * This conversion is used as part of the calibration process when determining
3335 * the additional error of a timestamp vs the real time of transmission or
3336 * receipt of the packet.
3337 *
3338 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
3339 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
3340 *
3341 * To calculate the conversion ratio, we use the following facts:
3342 *
3343 * a) the clock frequency in Hz (cycles per second)
3344 * b) the number of TUs per cycle (the increment value of the clock)
3345 * c) 1 second per 1 billion nanoseconds
3346 * d) the duration of 66 UIs in nanoseconds
3347 *
3348 * Given these facts, we can use the following table to work out what ratios
3349 * to multiply in order to get the number of TUs per 66 UIs:
3350 *
3351 * cycles | 1 second | incval (TUs) | nanoseconds
3352 * -------+--------------+--------------+-------------
3353 * second | 1 billion ns | cycle | 66 UIs
3354 *
3355 * To perform the multiplication using integers without too much loss of
3356 * precision, we can take use the following equation:
3357 *
3358 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
3359 *
3360 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
3361 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
3362 *
3363 * The increment value has a maximum expected range of about 34 bits, while
3364 * the frequency value is about 29 bits. Multiplying these values shouldn't
3365 * overflow the 64 bits. However, we must then further multiply them again by
3366 * the Serdes unit interval duration. To avoid overflow here, we split the
3367 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
3368 * a divide by 390,625,000. This does lose some precision, but avoids
3369 * miscalculation due to arithmetic overflow.
3370 */
ice_phy_cfg_uix_e82x(struct ice_hw * hw,u8 port)3371 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port)
3372 {
3373 u64 cur_freq, clk_incval, tu_per_sec, uix;
3374 int err;
3375
3376 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3377 clk_incval = ice_ptp_read_src_incval(hw);
3378
3379 /* Calculate TUs per second divided by 256 */
3380 tu_per_sec = (cur_freq * clk_incval) >> 8;
3381
3382 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
3383 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
3384
3385 /* Program the 10Gb/40Gb conversion ratio */
3386 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);
3387
3388 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,
3389 uix);
3390 if (err) {
3391 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
3392 err);
3393 return err;
3394 }
3395
3396 /* Program the 25Gb/100Gb conversion ratio */
3397 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);
3398
3399 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,
3400 uix);
3401 if (err) {
3402 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
3403 err);
3404 return err;
3405 }
3406
3407 return 0;
3408 }
3409
3410 /**
3411 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3412 * @hw: pointer to the HW struct
3413 * @port: port to configure
3414 *
3415 * Configure the number of TUs for the PAR and PCS clocks used as part of the
3416 * timestamp calibration process. This depends on the link speed, as the PHY
3417 * uses different markers depending on the speed.
3418 *
3419 * 1Gb/10Gb/25Gb:
3420 * - Tx/Rx PAR/PCS markers
3421 *
3422 * 25Gb RS:
3423 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3424 *
3425 * 40Gb/50Gb:
3426 * - Tx/Rx PAR/PCS markers
3427 * - Rx Deskew PAR/PCS markers
3428 *
3429 * 50G RS and 100GB RS:
3430 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3431 * - Rx Deskew PAR/PCS markers
3432 * - Tx PAR/PCS markers
3433 *
3434 * To calculate the conversion, we use the PHC clock frequency (cycles per
3435 * second), the increment value (TUs per cycle), and the related PHY clock
3436 * frequency to calculate the TUs per unit of the PHY link clock. The
3437 * following table shows how the units convert:
3438 *
3439 * cycles | TUs | second
3440 * -------+-------+--------
3441 * second | cycle | cycles
3442 *
3443 * For each conversion register, look up the appropriate frequency from the
3444 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
3445 * this to the appropriate register, preparing hardware to perform timestamp
3446 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
3447 * in order to calibrate for the internal PHY delays.
3448 *
3449 * Note that the increment value ranges up to ~34 bits, and the clock
3450 * frequency is ~29 bits, so multiplying them together should fit within the
3451 * 64 bit arithmetic.
3452 */
ice_phy_cfg_parpcs_e82x(struct ice_hw * hw,u8 port)3453 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port)
3454 {
3455 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
3456 enum ice_ptp_link_spd link_spd;
3457 enum ice_ptp_fec_mode fec_mode;
3458 int err;
3459
3460 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3461 if (err)
3462 return err;
3463
3464 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3465 clk_incval = ice_ptp_read_src_incval(hw);
3466
3467 /* Calculate TUs per cycle of the PHC clock */
3468 tu_per_sec = cur_freq * clk_incval;
3469
3470 /* For each PHY conversion register, look up the appropriate link
3471 * speed frequency and determine the TUs per that clock's cycle time.
3472 * Split this into a high and low value and then program the
3473 * appropriate register. If that link speed does not use the
3474 * associated register, write zeros to clear it instead.
3475 */
3476
3477 /* P_REG_PAR_TX_TUS */
3478 if (e822_vernier[link_spd].tx_par_clk)
3479 phy_tus = div_u64(tu_per_sec,
3480 e822_vernier[link_spd].tx_par_clk);
3481 else
3482 phy_tus = 0;
3483
3484 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,
3485 phy_tus);
3486 if (err)
3487 return err;
3488
3489 /* P_REG_PAR_RX_TUS */
3490 if (e822_vernier[link_spd].rx_par_clk)
3491 phy_tus = div_u64(tu_per_sec,
3492 e822_vernier[link_spd].rx_par_clk);
3493 else
3494 phy_tus = 0;
3495
3496 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,
3497 phy_tus);
3498 if (err)
3499 return err;
3500
3501 /* P_REG_PCS_TX_TUS */
3502 if (e822_vernier[link_spd].tx_pcs_clk)
3503 phy_tus = div_u64(tu_per_sec,
3504 e822_vernier[link_spd].tx_pcs_clk);
3505 else
3506 phy_tus = 0;
3507
3508 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,
3509 phy_tus);
3510 if (err)
3511 return err;
3512
3513 /* P_REG_PCS_RX_TUS */
3514 if (e822_vernier[link_spd].rx_pcs_clk)
3515 phy_tus = div_u64(tu_per_sec,
3516 e822_vernier[link_spd].rx_pcs_clk);
3517 else
3518 phy_tus = 0;
3519
3520 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,
3521 phy_tus);
3522 if (err)
3523 return err;
3524
3525 /* P_REG_DESK_PAR_TX_TUS */
3526 if (e822_vernier[link_spd].tx_desk_rsgb_par)
3527 phy_tus = div_u64(tu_per_sec,
3528 e822_vernier[link_spd].tx_desk_rsgb_par);
3529 else
3530 phy_tus = 0;
3531
3532 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,
3533 phy_tus);
3534 if (err)
3535 return err;
3536
3537 /* P_REG_DESK_PAR_RX_TUS */
3538 if (e822_vernier[link_spd].rx_desk_rsgb_par)
3539 phy_tus = div_u64(tu_per_sec,
3540 e822_vernier[link_spd].rx_desk_rsgb_par);
3541 else
3542 phy_tus = 0;
3543
3544 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,
3545 phy_tus);
3546 if (err)
3547 return err;
3548
3549 /* P_REG_DESK_PCS_TX_TUS */
3550 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
3551 phy_tus = div_u64(tu_per_sec,
3552 e822_vernier[link_spd].tx_desk_rsgb_pcs);
3553 else
3554 phy_tus = 0;
3555
3556 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,
3557 phy_tus);
3558 if (err)
3559 return err;
3560
3561 /* P_REG_DESK_PCS_RX_TUS */
3562 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
3563 phy_tus = div_u64(tu_per_sec,
3564 e822_vernier[link_spd].rx_desk_rsgb_pcs);
3565 else
3566 phy_tus = 0;
3567
3568 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L,
3569 phy_tus);
3570 }
3571
3572 /**
3573 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
3574 * @hw: pointer to the HW struct
3575 * @link_spd: the Link speed to calculate for
3576 *
3577 * Calculate the fixed offset due to known static latency data.
3578 */
3579 static u64
ice_calc_fixed_tx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)3580 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
3581 {
3582 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
3583
3584 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3585 clk_incval = ice_ptp_read_src_incval(hw);
3586
3587 /* Calculate TUs per second */
3588 tu_per_sec = cur_freq * clk_incval;
3589
3590 /* Calculate number of TUs to add for the fixed Tx latency. Since the
3591 * latency measurement is in 1/100th of a nanosecond, we need to
3592 * multiply by tu_per_sec and then divide by 1e11. This calculation
3593 * overflows 64 bit integer arithmetic, so break it up into two
3594 * divisions by 1e4 first then by 1e7.
3595 */
3596 fixed_offset = div_u64(tu_per_sec, 10000);
3597 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
3598 fixed_offset = div_u64(fixed_offset, 10000000);
3599
3600 return fixed_offset;
3601 }
3602
3603 /**
3604 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
3605 * @hw: pointer to the HW struct
3606 * @port: the PHY port to configure
3607 *
3608 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
3609 * adjust Tx timestamps by. This is calculated by combining some known static
3610 * latency along with the Vernier offset computations done by hardware.
3611 *
3612 * This function will not return successfully until the Tx offset calculations
3613 * have been completed, which requires waiting until at least one packet has
3614 * been transmitted by the device. It is safe to call this function
3615 * periodically until calibration succeeds, as it will only program the offset
3616 * once.
3617 *
3618 * To avoid overflow, when calculating the offset based on the known static
3619 * latency values, we use measurements in 1/100th of a nanosecond, and divide
3620 * the TUs per second up front. This avoids overflow while allowing
3621 * calculation of the adjustment using integer arithmetic.
3622 *
3623 * Returns zero on success, -EBUSY if the hardware vernier offset
3624 * calibration has not completed, or another error code on failure.
3625 */
ice_phy_cfg_tx_offset_e82x(struct ice_hw * hw,u8 port)3626 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port)
3627 {
3628 enum ice_ptp_link_spd link_spd;
3629 enum ice_ptp_fec_mode fec_mode;
3630 u64 total_offset, val;
3631 int err;
3632 u32 reg;
3633
3634 /* Nothing to do if we've already programmed the offset */
3635 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®);
3636 if (err) {
3637 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
3638 port, err);
3639 return err;
3640 }
3641
3642 if (reg)
3643 return 0;
3644
3645 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®);
3646 if (err) {
3647 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
3648 port, err);
3649 return err;
3650 }
3651
3652 if (!(reg & P_REG_TX_OV_STATUS_OV_M))
3653 return -EBUSY;
3654
3655 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3656 if (err)
3657 return err;
3658
3659 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd);
3660
3661 /* Read the first Vernier offset from the PHY register and add it to
3662 * the total offset.
3663 */
3664 if (link_spd == ICE_PTP_LNK_SPD_1G ||
3665 link_spd == ICE_PTP_LNK_SPD_10G ||
3666 link_spd == ICE_PTP_LNK_SPD_25G ||
3667 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
3668 link_spd == ICE_PTP_LNK_SPD_40G ||
3669 link_spd == ICE_PTP_LNK_SPD_50G) {
3670 err = ice_read_64b_phy_reg_e82x(hw, port,
3671 P_REG_PAR_PCS_TX_OFFSET_L,
3672 &val);
3673 if (err)
3674 return err;
3675
3676 total_offset += val;
3677 }
3678
3679 /* For Tx, we only need to use the second Vernier offset for
3680 * multi-lane link speeds with RS-FEC. The lanes will always be
3681 * aligned.
3682 */
3683 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
3684 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
3685 err = ice_read_64b_phy_reg_e82x(hw, port,
3686 P_REG_PAR_TX_TIME_L,
3687 &val);
3688 if (err)
3689 return err;
3690
3691 total_offset += val;
3692 }
3693
3694 /* Now that the total offset has been calculated, program it to the
3695 * PHY and indicate that the Tx offset is ready. After this,
3696 * timestamps will be enabled.
3697 */
3698 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,
3699 total_offset);
3700 if (err)
3701 return err;
3702
3703 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);
3704 if (err)
3705 return err;
3706
3707 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n",
3708 port);
3709
3710 return 0;
3711 }
3712
3713 /**
3714 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
3715 * @hw: pointer to the HW struct
3716 * @port: the PHY port to adjust for
3717 * @link_spd: the current link speed of the PHY
3718 * @fec_mode: the current FEC mode of the PHY
3719 * @pmd_adj: on return, the amount to adjust the Rx total offset by
3720 *
3721 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
3722 * This varies by link speed and FEC mode. The value calculated accounts for
3723 * various delays caused when receiving a packet.
3724 */
3725 static int
ice_phy_calc_pmd_adj_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd link_spd,enum ice_ptp_fec_mode fec_mode,u64 * pmd_adj)3726 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port,
3727 enum ice_ptp_link_spd link_spd,
3728 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
3729 {
3730 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
3731 u8 pmd_align;
3732 u32 val;
3733 int err;
3734
3735 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val);
3736 if (err) {
3737 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
3738 err);
3739 return err;
3740 }
3741
3742 pmd_align = (u8)val;
3743
3744 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3745 clk_incval = ice_ptp_read_src_incval(hw);
3746
3747 /* Calculate TUs per second */
3748 tu_per_sec = cur_freq * clk_incval;
3749
3750 /* The PMD alignment adjustment measurement depends on the link speed,
3751 * and whether FEC is enabled. For each link speed, the alignment
3752 * adjustment is calculated by dividing a value by the length of
3753 * a Time Unit in nanoseconds.
3754 *
3755 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
3756 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
3757 * 10G w/FEC: align * 0.1 * 32/33
3758 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
3759 * 25G w/FEC: align * 0.4 * 32/33
3760 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
3761 * 40G w/FEC: align * 0.1 * 32/33
3762 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
3763 * 50G w/FEC: align * 0.8 * 32/33
3764 *
3765 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
3766 *
3767 * To allow for calculating this value using integer arithmetic, we
3768 * instead start with the number of TUs per second, (inverse of the
3769 * length of a Time Unit in nanoseconds), multiply by a value based
3770 * on the PMD alignment register, and then divide by the right value
3771 * calculated based on the table above. To avoid integer overflow this
3772 * division is broken up into a step of dividing by 125 first.
3773 */
3774 if (link_spd == ICE_PTP_LNK_SPD_1G) {
3775 if (pmd_align == 4)
3776 mult = 10;
3777 else
3778 mult = (pmd_align + 6) % 10;
3779 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
3780 link_spd == ICE_PTP_LNK_SPD_25G ||
3781 link_spd == ICE_PTP_LNK_SPD_40G ||
3782 link_spd == ICE_PTP_LNK_SPD_50G) {
3783 /* If Clause 74 FEC, always calculate PMD adjust */
3784 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
3785 mult = pmd_align;
3786 else
3787 mult = 0;
3788 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
3789 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
3790 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
3791 if (pmd_align < 17)
3792 mult = pmd_align + 40;
3793 else
3794 mult = pmd_align;
3795 } else {
3796 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
3797 link_spd);
3798 mult = 0;
3799 }
3800
3801 /* In some cases, there's no need to adjust for the PMD alignment */
3802 if (!mult) {
3803 *pmd_adj = 0;
3804 return 0;
3805 }
3806
3807 /* Calculate the adjustment by multiplying TUs per second by the
3808 * appropriate multiplier and divisor. To avoid overflow, we first
3809 * divide by 125, and then handle remaining divisor based on the link
3810 * speed pmd_adj_divisor value.
3811 */
3812 adj = div_u64(tu_per_sec, 125);
3813 adj *= mult;
3814 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor);
3815
3816 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
3817 * cycle count is necessary.
3818 */
3819 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
3820 u64 cycle_adj;
3821 u8 rx_cycle;
3822
3823 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,
3824 &val);
3825 if (err) {
3826 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
3827 err);
3828 return err;
3829 }
3830
3831 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
3832 if (rx_cycle) {
3833 mult = (4 - rx_cycle) * 40;
3834
3835 cycle_adj = div_u64(tu_per_sec, 125);
3836 cycle_adj *= mult;
3837 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
3838
3839 adj += cycle_adj;
3840 }
3841 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
3842 u64 cycle_adj;
3843 u8 rx_cycle;
3844
3845 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,
3846 &val);
3847 if (err) {
3848 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
3849 err);
3850 return err;
3851 }
3852
3853 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
3854 if (rx_cycle) {
3855 mult = rx_cycle * 40;
3856
3857 cycle_adj = div_u64(tu_per_sec, 125);
3858 cycle_adj *= mult;
3859 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
3860
3861 adj += cycle_adj;
3862 }
3863 }
3864
3865 /* Return the calculated adjustment */
3866 *pmd_adj = adj;
3867
3868 return 0;
3869 }
3870
3871 /**
3872 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
3873 * @hw: pointer to HW struct
3874 * @link_spd: The Link speed to calculate for
3875 *
3876 * Determine the fixed Rx latency for a given link speed.
3877 */
3878 static u64
ice_calc_fixed_rx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)3879 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
3880 {
3881 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
3882
3883 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3884 clk_incval = ice_ptp_read_src_incval(hw);
3885
3886 /* Calculate TUs per second */
3887 tu_per_sec = cur_freq * clk_incval;
3888
3889 /* Calculate number of TUs to add for the fixed Rx latency. Since the
3890 * latency measurement is in 1/100th of a nanosecond, we need to
3891 * multiply by tu_per_sec and then divide by 1e11. This calculation
3892 * overflows 64 bit integer arithmetic, so break it up into two
3893 * divisions by 1e4 first then by 1e7.
3894 */
3895 fixed_offset = div_u64(tu_per_sec, 10000);
3896 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
3897 fixed_offset = div_u64(fixed_offset, 10000000);
3898
3899 return fixed_offset;
3900 }
3901
3902 /**
3903 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
3904 * @hw: pointer to the HW struct
3905 * @port: the PHY port to configure
3906 *
3907 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
3908 * adjust Rx timestamps by. This combines calculations from the Vernier offset
3909 * measurements taken in hardware with some data about known fixed delay as
3910 * well as adjusting for multi-lane alignment delay.
3911 *
3912 * This function will not return successfully until the Rx offset calculations
3913 * have been completed, which requires waiting until at least one packet has
3914 * been received by the device. It is safe to call this function periodically
3915 * until calibration succeeds, as it will only program the offset once.
3916 *
3917 * This function must be called only after the offset registers are valid,
3918 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
3919 * has measured the offset.
3920 *
3921 * To avoid overflow, when calculating the offset based on the known static
3922 * latency values, we use measurements in 1/100th of a nanosecond, and divide
3923 * the TUs per second up front. This avoids overflow while allowing
3924 * calculation of the adjustment using integer arithmetic.
3925 *
3926 * Returns zero on success, -EBUSY if the hardware vernier offset
3927 * calibration has not completed, or another error code on failure.
3928 */
ice_phy_cfg_rx_offset_e82x(struct ice_hw * hw,u8 port)3929 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
3930 {
3931 enum ice_ptp_link_spd link_spd;
3932 enum ice_ptp_fec_mode fec_mode;
3933 u64 total_offset, pmd, val;
3934 int err;
3935 u32 reg;
3936
3937 /* Nothing to do if we've already programmed the offset */
3938 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®);
3939 if (err) {
3940 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
3941 port, err);
3942 return err;
3943 }
3944
3945 if (reg)
3946 return 0;
3947
3948 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®);
3949 if (err) {
3950 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
3951 port, err);
3952 return err;
3953 }
3954
3955 if (!(reg & P_REG_RX_OV_STATUS_OV_M))
3956 return -EBUSY;
3957
3958 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3959 if (err)
3960 return err;
3961
3962 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd);
3963
3964 /* Read the first Vernier offset from the PHY register and add it to
3965 * the total offset.
3966 */
3967 err = ice_read_64b_phy_reg_e82x(hw, port,
3968 P_REG_PAR_PCS_RX_OFFSET_L,
3969 &val);
3970 if (err)
3971 return err;
3972
3973 total_offset += val;
3974
3975 /* For Rx, all multi-lane link speeds include a second Vernier
3976 * calibration, because the lanes might not be aligned.
3977 */
3978 if (link_spd == ICE_PTP_LNK_SPD_40G ||
3979 link_spd == ICE_PTP_LNK_SPD_50G ||
3980 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
3981 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
3982 err = ice_read_64b_phy_reg_e82x(hw, port,
3983 P_REG_PAR_RX_TIME_L,
3984 &val);
3985 if (err)
3986 return err;
3987
3988 total_offset += val;
3989 }
3990
3991 /* In addition, Rx must account for the PMD alignment */
3992 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd);
3993 if (err)
3994 return err;
3995
3996 /* For RS-FEC, this adjustment adds delay, but for other modes, it
3997 * subtracts delay.
3998 */
3999 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
4000 total_offset += pmd;
4001 else
4002 total_offset -= pmd;
4003
4004 /* Now that the total offset has been calculated, program it to the
4005 * PHY and indicate that the Rx offset is ready. After this,
4006 * timestamps will be enabled.
4007 */
4008 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,
4009 total_offset);
4010 if (err)
4011 return err;
4012
4013 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);
4014 if (err)
4015 return err;
4016
4017 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n",
4018 port);
4019
4020 return 0;
4021 }
4022
4023 /**
4024 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4025 * @hw: pointer to the HW struct
4026 *
4027 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
4028 * and received timestamps as invalid.
4029 *
4030 * Return: 0 on success, other error codes when failed to write to PHY
4031 */
ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw * hw)4032 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
4033 {
4034 u8 port;
4035
4036 for (port = 0; port < hw->ptp.num_lports; port++) {
4037 int err;
4038
4039 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4040 if (err) {
4041 dev_warn(ice_hw_to_dev(hw),
4042 "Failed to clear PHY TX_OFFSET_READY register\n");
4043 return err;
4044 }
4045
4046 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4047 if (err) {
4048 dev_warn(ice_hw_to_dev(hw),
4049 "Failed to clear PHY RX_OFFSET_READY register\n");
4050 return err;
4051 }
4052 }
4053
4054 return 0;
4055 }
4056
4057 /**
4058 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4059 * @hw: pointer to the HW struct
4060 * @port: the PHY port to read
4061 * @phy_time: on return, the 64bit PHY timer value
4062 * @phc_time: on return, the lower 64bits of PHC time
4063 *
4064 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
4065 * and PHC timer values.
4066 */
4067 static int
ice_read_phy_and_phc_time_e82x(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)4068 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time,
4069 u64 *phc_time)
4070 {
4071 u64 tx_time, rx_time;
4072 u32 zo, lo;
4073 u8 tmr_idx;
4074 int err;
4075
4076 tmr_idx = ice_get_ptp_src_clock_index(hw);
4077
4078 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
4079 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
4080
4081 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
4082 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
4083 if (err)
4084 return err;
4085
4086 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
4087 ice_ptp_exec_tmr_cmd(hw);
4088
4089 /* Read the captured PHC time from the shadow time registers */
4090 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
4091 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
4092 *phc_time = (u64)lo << 32 | zo;
4093
4094 /* Read the captured PHY time from the PHY shadow registers */
4095 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
4096 if (err)
4097 return err;
4098
4099 /* If the PHY Tx and Rx timers don't match, log a warning message.
4100 * Note that this should not happen in normal circumstances since the
4101 * driver always programs them together.
4102 */
4103 if (tx_time != rx_time)
4104 dev_warn(ice_hw_to_dev(hw),
4105 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
4106 port, (unsigned long long)tx_time,
4107 (unsigned long long)rx_time);
4108
4109 *phy_time = tx_time;
4110
4111 return 0;
4112 }
4113
4114 /**
4115 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4116 * @hw: pointer to the HW struct
4117 * @port: the PHY port to synchronize
4118 *
4119 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
4120 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
4121 * simultaneous read of the PHY timer and PHC timer. Then we use the
4122 * difference to calculate an appropriate 2s complement addition to add
4123 * to the PHY timer in order to ensure it reads the same value as the
4124 * primary PHC timer.
4125 */
ice_sync_phy_timer_e82x(struct ice_hw * hw,u8 port)4126 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port)
4127 {
4128 u64 phc_time, phy_time, difference;
4129 int err;
4130
4131 if (!ice_ptp_lock(hw)) {
4132 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
4133 return -EBUSY;
4134 }
4135
4136 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4137 if (err)
4138 goto err_unlock;
4139
4140 /* Calculate the amount required to add to the port time in order for
4141 * it to match the PHC time.
4142 *
4143 * Note that the port adjustment is done using 2s complement
4144 * arithmetic. This is convenient since it means that we can simply
4145 * calculate the difference between the PHC time and the port time,
4146 * and it will be interpreted correctly.
4147 */
4148 difference = phc_time - phy_time;
4149
4150 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);
4151 if (err)
4152 goto err_unlock;
4153
4154 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
4155 if (err)
4156 goto err_unlock;
4157
4158 /* Do not perform any action on the main timer */
4159 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4160
4161 /* Issue the sync to activate the time adjustment */
4162 ice_ptp_exec_tmr_cmd(hw);
4163
4164 /* Re-capture the timer values to flush the command registers and
4165 * verify that the time was properly adjusted.
4166 */
4167 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4168 if (err)
4169 goto err_unlock;
4170
4171 dev_info(ice_hw_to_dev(hw),
4172 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
4173 port, (unsigned long long)phy_time,
4174 (unsigned long long)phc_time);
4175
4176 ice_ptp_unlock(hw);
4177
4178 return 0;
4179
4180 err_unlock:
4181 ice_ptp_unlock(hw);
4182 return err;
4183 }
4184
4185 /**
4186 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4187 * @hw: pointer to the HW struct
4188 * @port: the PHY port to stop
4189 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
4190 *
4191 * Stop the clock of a PHY port. This must be done as part of the flow to
4192 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4193 * initialized or when link speed changes.
4194 */
4195 int
ice_stop_phy_timer_e82x(struct ice_hw * hw,u8 port,bool soft_reset)4196 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset)
4197 {
4198 int err;
4199 u32 val;
4200
4201 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4202 if (err)
4203 return err;
4204
4205 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4206 if (err)
4207 return err;
4208
4209 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4210 if (err)
4211 return err;
4212
4213 val &= ~P_REG_PS_START_M;
4214 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4215 if (err)
4216 return err;
4217
4218 val &= ~P_REG_PS_ENA_CLK_M;
4219 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4220 if (err)
4221 return err;
4222
4223 if (soft_reset) {
4224 val |= P_REG_PS_SFT_RESET_M;
4225 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4226 if (err)
4227 return err;
4228 }
4229
4230 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
4231
4232 return 0;
4233 }
4234
4235 /**
4236 * ice_start_phy_timer_e82x - Start the PHY clock timer
4237 * @hw: pointer to the HW struct
4238 * @port: the PHY port to start
4239 *
4240 * Start the clock of a PHY port. This must be done as part of the flow to
4241 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4242 * initialized or when link speed changes.
4243 *
4244 * Hardware will take Vernier measurements on Tx or Rx of packets.
4245 */
ice_start_phy_timer_e82x(struct ice_hw * hw,u8 port)4246 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port)
4247 {
4248 u32 lo, hi, val;
4249 u64 incval;
4250 u8 tmr_idx;
4251 int err;
4252
4253 tmr_idx = ice_get_ptp_src_clock_index(hw);
4254
4255 err = ice_stop_phy_timer_e82x(hw, port, false);
4256 if (err)
4257 return err;
4258
4259 ice_phy_cfg_lane_e82x(hw, port);
4260
4261 err = ice_phy_cfg_uix_e82x(hw, port);
4262 if (err)
4263 return err;
4264
4265 err = ice_phy_cfg_parpcs_e82x(hw, port);
4266 if (err)
4267 return err;
4268
4269 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
4270 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
4271 incval = (u64)hi << 32 | lo;
4272
4273 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);
4274 if (err)
4275 return err;
4276
4277 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4278 if (err)
4279 return err;
4280
4281 /* Do not perform any action on the main timer */
4282 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4283
4284 ice_ptp_exec_tmr_cmd(hw);
4285
4286 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4287 if (err)
4288 return err;
4289
4290 val |= P_REG_PS_SFT_RESET_M;
4291 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4292 if (err)
4293 return err;
4294
4295 val |= P_REG_PS_START_M;
4296 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4297 if (err)
4298 return err;
4299
4300 val &= ~P_REG_PS_SFT_RESET_M;
4301 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4302 if (err)
4303 return err;
4304
4305 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4306 if (err)
4307 return err;
4308
4309 ice_ptp_exec_tmr_cmd(hw);
4310
4311 val |= P_REG_PS_ENA_CLK_M;
4312 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4313 if (err)
4314 return err;
4315
4316 val |= P_REG_PS_LOAD_OFFSET_M;
4317 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4318 if (err)
4319 return err;
4320
4321 ice_ptp_exec_tmr_cmd(hw);
4322
4323 err = ice_sync_phy_timer_e82x(hw, port);
4324 if (err)
4325 return err;
4326
4327 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
4328
4329 return 0;
4330 }
4331
4332 /**
4333 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4334 * @hw: pointer to the HW struct
4335 * @quad: the timestamp quad to read from
4336 * @tstamp_ready: contents of the Tx memory status register
4337 *
4338 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
4339 * the PHY are ready. A set bit means the corresponding timestamp is valid and
4340 * ready to be captured from the PHY timestamp block.
4341 */
4342 static int
ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw * hw,u8 quad,u64 * tstamp_ready)4343 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
4344 {
4345 u32 hi, lo;
4346 int err;
4347
4348 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
4349 if (err) {
4350 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
4351 quad, err);
4352 return err;
4353 }
4354
4355 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
4356 if (err) {
4357 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
4358 quad, err);
4359 return err;
4360 }
4361
4362 *tstamp_ready = (u64)hi << 32 | (u64)lo;
4363
4364 return 0;
4365 }
4366
4367 /**
4368 * ice_check_phy_tx_tstamp_ready_e82x - Check Tx memory status for all quads
4369 * @hw: pointer to the HW struct
4370 *
4371 * Check the Q_REG_TX_MEMORY_STATUS for all quads. A set bit indicates
4372 * a waiting timestamp.
4373 *
4374 * Return: 1 if any quad has at least one timestamp ready bit set,
4375 * 0 otherwise, and a negative error value if unable to read the bitmap.
4376 */
ice_check_phy_tx_tstamp_ready_e82x(struct ice_hw * hw)4377 static int ice_check_phy_tx_tstamp_ready_e82x(struct ice_hw *hw)
4378 {
4379 int quad;
4380
4381 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {
4382 u64 tstamp_ready;
4383 int err;
4384
4385 err = ice_get_phy_tx_tstamp_ready(hw, quad, &tstamp_ready);
4386 if (err)
4387 return err;
4388
4389 if (tstamp_ready)
4390 return 1;
4391 }
4392
4393 return 0;
4394 }
4395
4396 /**
4397 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4398 * @hw: pointer to the HW struct
4399 * @quad: the timestamp quad
4400 * @ena: enable or disable interrupt
4401 * @threshold: interrupt threshold
4402 *
4403 * Configure TX timestamp interrupt for the specified quad
4404 *
4405 * Return: 0 on success, other error codes when failed to read/write quad
4406 */
4407
ice_phy_cfg_intr_e82x(struct ice_hw * hw,u8 quad,bool ena,u8 threshold)4408 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
4409 {
4410 int err;
4411 u32 val;
4412
4413 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
4414 if (err)
4415 return err;
4416
4417 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4418 if (ena) {
4419 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4420 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
4421 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
4422 }
4423
4424 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
4425 }
4426
4427 /**
4428 * ice_ptp_init_phy_e82x - initialize PHY parameters
4429 * @ptp: pointer to the PTP HW struct
4430 */
ice_ptp_init_phy_e82x(struct ice_ptp_hw * ptp)4431 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)
4432 {
4433 ptp->num_lports = 8;
4434 ptp->ports_per_phy = 8;
4435 }
4436
4437 /* E810 functions
4438 *
4439 * The following functions operate on the E810 series devices which use
4440 * a separate external PHY.
4441 */
4442
4443 /**
4444 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4445 * @hw: pointer to the HW struct
4446 * @addr: the address to read from
4447 * @val: On return, the value read from the PHY
4448 *
4449 * Read a register from the external PHY on the E810 device.
4450 */
ice_read_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 * val)4451 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
4452 {
4453 struct ice_sbq_msg_input msg = {0};
4454 int err;
4455
4456 msg.msg_addr_low = lower_16_bits(addr);
4457 msg.msg_addr_high = upper_16_bits(addr);
4458 msg.opcode = ice_sbq_msg_rd;
4459 msg.dest_dev = ice_sbq_dev_phy_0;
4460
4461 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
4462 if (err) {
4463 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4464 err);
4465 return err;
4466 }
4467
4468 *val = msg.data;
4469
4470 return 0;
4471 }
4472
4473 /**
4474 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4475 * @hw: pointer to the HW struct
4476 * @addr: the address to writem to
4477 * @val: the value to write to the PHY
4478 *
4479 * Write a value to a register of the external PHY on the E810 device.
4480 */
ice_write_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 val)4481 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
4482 {
4483 struct ice_sbq_msg_input msg = {0};
4484 int err;
4485
4486 msg.msg_addr_low = lower_16_bits(addr);
4487 msg.msg_addr_high = upper_16_bits(addr);
4488 msg.opcode = ice_sbq_msg_wr;
4489 msg.dest_dev = ice_sbq_dev_phy_0;
4490 msg.data = val;
4491
4492 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);
4493 if (err) {
4494 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4495 err);
4496 return err;
4497 }
4498
4499 return 0;
4500 }
4501
4502 /**
4503 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4504 * @hw: pointer to the HW struct
4505 * @idx: the timestamp index to read
4506 * @hi: 8 bit timestamp high value
4507 * @lo: 32 bit timestamp low value
4508 *
4509 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4510 * timestamp block of the external PHY on the E810 device using the low latency
4511 * timestamp read.
4512 */
4513 static int
ice_read_phy_tstamp_ll_e810(struct ice_hw * hw,u8 idx,u8 * hi,u32 * lo)4514 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
4515 {
4516 struct ice_e810_params *params = &hw->ptp.phy.e810;
4517 u32 val;
4518 int err;
4519
4520 spin_lock_irq(¶ms->atqbal_wq.lock);
4521
4522 /* Wait for any pending in-progress low latency interrupt */
4523 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
4524 !(params->atqbal_flags &
4525 ATQBAL_FLAGS_INTR_IN_PROGRESS));
4526 if (err) {
4527 spin_unlock_irq(¶ms->atqbal_wq.lock);
4528 return err;
4529 }
4530
4531 /* Write TS index to read to the PF register so the FW can read it */
4532 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC;
4533 wr32(hw, REG_LL_PROXY_H, val);
4534
4535 /* Read the register repeatedly until the FW provides us the TS */
4536 err = read_poll_timeout_atomic(rd32, val,
4537 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10,
4538 REG_LL_PROXY_H_TIMEOUT_US, false, hw,
4539 REG_LL_PROXY_H);
4540 if (err) {
4541 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
4542 spin_unlock_irq(¶ms->atqbal_wq.lock);
4543 return err;
4544 }
4545
4546 /* High 8 bit value of the TS is on the bits 16:23 */
4547 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val);
4548
4549 /* Read the low 32 bit value and set the TS valid bit */
4550 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID;
4551
4552 spin_unlock_irq(¶ms->atqbal_wq.lock);
4553
4554 return 0;
4555 }
4556
4557 /**
4558 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4559 * @hw: pointer to the HW struct
4560 * @lport: the lport to read from
4561 * @idx: the timestamp index to read
4562 * @hi: 8 bit timestamp high value
4563 * @lo: 32 bit timestamp low value
4564 *
4565 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4566 * timestamp block of the external PHY on the E810 device using sideband queue.
4567 */
4568 static int
ice_read_phy_tstamp_sbq_e810(struct ice_hw * hw,u8 lport,u8 idx,u8 * hi,u32 * lo)4569 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
4570 u32 *lo)
4571 {
4572 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4573 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4574 u32 lo_val, hi_val;
4575 int err;
4576
4577 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
4578 if (err) {
4579 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
4580 err);
4581 return err;
4582 }
4583
4584 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
4585 if (err) {
4586 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
4587 err);
4588 return err;
4589 }
4590
4591 *lo = lo_val;
4592 *hi = (u8)hi_val;
4593
4594 return 0;
4595 }
4596
4597 /**
4598 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4599 * @hw: pointer to the HW struct
4600 * @lport: the lport to read from
4601 * @idx: the timestamp index to read
4602 * @tstamp: on return, the 40bit timestamp value
4603 *
4604 * Read a 40bit timestamp value out of the timestamp block of the external PHY
4605 * on the E810 device.
4606 */
4607 static int
ice_read_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx,u64 * tstamp)4608 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
4609 {
4610 u32 lo = 0;
4611 u8 hi = 0;
4612 int err;
4613
4614 if (hw->dev_caps.ts_dev_info.ts_ll_read)
4615 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
4616 else
4617 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
4618
4619 if (err)
4620 return err;
4621
4622 /* For E810 devices, the timestamp is reported with the lower 32 bits
4623 * in the low register, and the upper 8 bits in the high register.
4624 */
4625 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
4626 FIELD_PREP(PHY_EXT_40B_LOW_M, lo);
4627
4628 return 0;
4629 }
4630
4631 /**
4632 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
4633 * @hw: pointer to the HW struct
4634 * @lport: the lport to read from
4635 * @idx: the timestamp index to reset
4636 *
4637 * Read the timestamp and then forcibly overwrite its value to clear the valid
4638 * bit from the timestamp block of the external PHY on the E810 device.
4639 *
4640 * This function should only be called on an idx whose bit is set according to
4641 * ice_get_phy_tx_tstamp_ready().
4642 */
ice_clear_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx)4643 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
4644 {
4645 u32 lo_addr, hi_addr;
4646 u64 unused_tstamp;
4647 int err;
4648
4649 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
4650 if (err) {
4651 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
4652 lport, idx, err);
4653 return err;
4654 }
4655
4656 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4657 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4658
4659 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
4660 if (err) {
4661 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
4662 lport, idx, err);
4663 return err;
4664 }
4665
4666 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
4667 if (err) {
4668 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
4669 lport, idx, err);
4670 return err;
4671 }
4672
4673 return 0;
4674 }
4675
4676 /**
4677 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
4678 * @hw: pointer to HW struct
4679 *
4680 * Perform E810-specific PTP hardware clock initialization steps.
4681 *
4682 * Return: 0 on success, other error codes when failed to initialize TimeSync
4683 */
ice_ptp_init_phc_e810(struct ice_hw * hw)4684 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
4685 {
4686 u8 tmr_idx;
4687 int err;
4688
4689 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY);
4690
4691 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4692 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
4693 GLTSYN_ENA_TSYN_ENA_M);
4694 if (err)
4695 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
4696 err);
4697
4698 return err;
4699 }
4700
4701 /**
4702 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
4703 * @hw: Board private structure
4704 * @time: Time to initialize the PHY port clock to
4705 *
4706 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
4707 * initial clock time. The time will not actually be programmed until the
4708 * driver issues an ICE_PTP_INIT_TIME command.
4709 *
4710 * The time value is the upper 32 bits of the PHY timer, usually in units of
4711 * nominal nanoseconds.
4712 */
ice_ptp_prep_phy_time_e810(struct ice_hw * hw,u32 time)4713 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
4714 {
4715 u8 tmr_idx;
4716 int err;
4717
4718 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4719 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
4720 if (err) {
4721 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
4722 err);
4723 return err;
4724 }
4725
4726 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
4727 if (err) {
4728 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
4729 err);
4730 return err;
4731 }
4732
4733 return 0;
4734 }
4735
4736 /**
4737 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment
4738 * @hw: pointer to HW struct
4739 * @adj: adjustment value to program
4740 *
4741 * Use the low latency firmware interface to program PHY time adjustment to
4742 * all PHY ports.
4743 *
4744 * Return: 0 on success, -EBUSY on timeout
4745 */
ice_ptp_prep_phy_adj_ll_e810(struct ice_hw * hw,s32 adj)4746 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj)
4747 {
4748 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4749 struct ice_e810_params *params = &hw->ptp.phy.e810;
4750 u32 val;
4751 int err;
4752
4753 spin_lock_irq(¶ms->atqbal_wq.lock);
4754
4755 /* Wait for any pending in-progress low latency interrupt */
4756 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
4757 !(params->atqbal_flags &
4758 ATQBAL_FLAGS_INTR_IN_PROGRESS));
4759 if (err) {
4760 spin_unlock_irq(¶ms->atqbal_wq.lock);
4761 return err;
4762 }
4763
4764 wr32(hw, REG_LL_PROXY_L, adj);
4765 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) |
4766 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC;
4767 wr32(hw, REG_LL_PROXY_H, val);
4768
4769 /* Read the register repeatedly until the FW indicates completion */
4770 err = read_poll_timeout_atomic(rd32, val,
4771 !FIELD_GET(REG_LL_PROXY_H_EXEC, val),
4772 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
4773 REG_LL_PROXY_H);
4774 if (err) {
4775 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
4776 spin_unlock_irq(¶ms->atqbal_wq.lock);
4777 return err;
4778 }
4779
4780 spin_unlock_irq(¶ms->atqbal_wq.lock);
4781
4782 return 0;
4783 }
4784
4785 /**
4786 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
4787 * @hw: pointer to HW struct
4788 * @adj: adjustment value to program
4789 *
4790 * Prepare the PHY port for an atomic adjustment by programming the PHY
4791 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
4792 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.
4793 *
4794 * The adjustment value only contains the portion used for the upper 32bits of
4795 * the PHY timer, usually in units of nominal nanoseconds. Negative
4796 * adjustments are supported using 2s complement arithmetic.
4797 */
ice_ptp_prep_phy_adj_e810(struct ice_hw * hw,s32 adj)4798 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
4799 {
4800 u8 tmr_idx;
4801 int err;
4802
4803 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
4804 return ice_ptp_prep_phy_adj_ll_e810(hw, adj);
4805
4806 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4807
4808 /* Adjustments are represented as signed 2's complement values in
4809 * nanoseconds. Sub-nanosecond adjustment is not supported.
4810 */
4811 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
4812 if (err) {
4813 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
4814 err);
4815 return err;
4816 }
4817
4818 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
4819 if (err) {
4820 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
4821 err);
4822 return err;
4823 }
4824
4825 return 0;
4826 }
4827
4828 /**
4829 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change
4830 * @hw: pointer to HW struct
4831 * @incval: The new 40bit increment value to prepare
4832 *
4833 * Use the low latency firmware interface to program PHY time increment value
4834 * for all PHY ports.
4835 *
4836 * Return: 0 on success, -EBUSY on timeout
4837 */
ice_ptp_prep_phy_incval_ll_e810(struct ice_hw * hw,u64 incval)4838 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval)
4839 {
4840 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4841 struct ice_e810_params *params = &hw->ptp.phy.e810;
4842 u32 val;
4843 int err;
4844
4845 spin_lock_irq(¶ms->atqbal_wq.lock);
4846
4847 /* Wait for any pending in-progress low latency interrupt */
4848 err = wait_event_interruptible_locked_irq(params->atqbal_wq,
4849 !(params->atqbal_flags &
4850 ATQBAL_FLAGS_INTR_IN_PROGRESS));
4851 if (err) {
4852 spin_unlock_irq(¶ms->atqbal_wq.lock);
4853 return err;
4854 }
4855
4856 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval));
4857 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) |
4858 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) |
4859 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC;
4860 wr32(hw, REG_LL_PROXY_H, val);
4861
4862 /* Read the register repeatedly until the FW indicates completion */
4863 err = read_poll_timeout_atomic(rd32, val,
4864 !FIELD_GET(REG_LL_PROXY_H_EXEC, val),
4865 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw,
4866 REG_LL_PROXY_H);
4867 if (err) {
4868 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
4869 spin_unlock_irq(¶ms->atqbal_wq.lock);
4870 return err;
4871 }
4872
4873 spin_unlock_irq(¶ms->atqbal_wq.lock);
4874
4875 return 0;
4876 }
4877
4878 /**
4879 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
4880 * @hw: pointer to HW struct
4881 * @incval: The new 40bit increment value to prepare
4882 *
4883 * Prepare the PHY port for a new increment value by programming the PHY
4884 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
4885 * completed by issuing an ICE_PTP_INIT_INCVAL command.
4886 */
ice_ptp_prep_phy_incval_e810(struct ice_hw * hw,u64 incval)4887 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
4888 {
4889 u32 high, low;
4890 u8 tmr_idx;
4891 int err;
4892
4893 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update)
4894 return ice_ptp_prep_phy_incval_ll_e810(hw, incval);
4895
4896 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
4897 low = lower_32_bits(incval);
4898 high = upper_32_bits(incval);
4899
4900 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
4901 if (err) {
4902 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
4903 err);
4904 return err;
4905 }
4906
4907 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
4908 if (err) {
4909 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
4910 err);
4911 return err;
4912 }
4913
4914 return 0;
4915 }
4916
4917 /**
4918 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
4919 * @hw: pointer to HW struct
4920 * @cmd: Command to be sent to the port
4921 *
4922 * Prepare the external PHYs connected to this device for a timer sync
4923 * command.
4924 */
ice_ptp_port_cmd_e810(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)4925 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
4926 {
4927 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
4928
4929 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val);
4930 }
4931
4932 /**
4933 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
4934 * @hw: pointer to the HW struct
4935 * @port: the PHY port to read
4936 * @tstamp_ready: contents of the Tx memory status register
4937 *
4938 * E810 devices do not use a Tx memory status register. Instead simply
4939 * indicate that all timestamps are currently ready.
4940 */
4941 static int
ice_get_phy_tx_tstamp_ready_e810(struct ice_hw * hw,u8 port,u64 * tstamp_ready)4942 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
4943 {
4944 *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
4945 return 0;
4946 }
4947
4948 /**
4949 * ice_check_phy_tx_tstamp_ready_e810 - Check Tx memory status register
4950 * @hw: pointer to the HW struct
4951 *
4952 * The E810 devices do not have a Tx memory status register. Note this is
4953 * intentionally different behavior from ice_get_phy_tx_tstamp_ready_e810
4954 * which always says that all bits are ready. This function is called in cases
4955 * where code will trigger interrupts if timestamps are waiting, and should
4956 * not be called for E810 hardware.
4957 *
4958 * Return: 0.
4959 */
ice_check_phy_tx_tstamp_ready_e810(struct ice_hw * hw)4960 static int ice_check_phy_tx_tstamp_ready_e810(struct ice_hw *hw)
4961 {
4962 return 0;
4963 }
4964
4965 /* E810 SMA functions
4966 *
4967 * The following functions operate specifically on E810 hardware and are used
4968 * to access the extended GPIOs available.
4969 */
4970
4971 /**
4972 * ice_read_sma_ctrl
4973 * @hw: pointer to the hw struct
4974 * @data: pointer to data to be read from the GPIO controller
4975 *
4976 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
4977 * PCA9575 expander, so only bits 3-7 in data are valid.
4978 */
ice_read_sma_ctrl(struct ice_hw * hw,u8 * data)4979 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data)
4980 {
4981 int status;
4982 u16 handle;
4983 u8 i;
4984
4985 status = ice_get_pca9575_handle(hw, &handle);
4986 if (status)
4987 return status;
4988
4989 *data = 0;
4990
4991 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
4992 bool pin;
4993
4994 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
4995 &pin, NULL);
4996 if (status)
4997 break;
4998 *data |= (u8)(!pin) << i;
4999 }
5000
5001 return status;
5002 }
5003
5004 /**
5005 * ice_write_sma_ctrl
5006 * @hw: pointer to the hw struct
5007 * @data: data to be written to the GPIO controller
5008 *
5009 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5010 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5011 */
ice_write_sma_ctrl(struct ice_hw * hw,u8 data)5012 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data)
5013 {
5014 int status;
5015 u16 handle;
5016 u8 i;
5017
5018 status = ice_get_pca9575_handle(hw, &handle);
5019 if (status)
5020 return status;
5021
5022 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
5023 bool pin;
5024
5025 pin = !(data & (1 << i));
5026 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5027 pin, NULL);
5028 if (status)
5029 break;
5030 }
5031
5032 return status;
5033 }
5034
5035 /**
5036 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM
5037 * @hw: pointer to the HW struct
5038 * @entries: returns the SDP available connections section from NVM
5039 * @num_entries: returns the number of valid entries
5040 *
5041 * Return: 0 on success, negative error code if NVM read failed or section does
5042 * not exist or is corrupted
5043 */
ice_ptp_read_sdp_ac(struct ice_hw * hw,__le16 * entries,uint * num_entries)5044 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries)
5045 {
5046 __le16 data;
5047 u32 offset;
5048 int err;
5049
5050 err = ice_acquire_nvm(hw, ICE_RES_READ);
5051 if (err)
5052 goto exit;
5053
5054 /* Read the offset of SDP_AC */
5055 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET;
5056 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5057 NULL);
5058 if (err)
5059 goto exit;
5060
5061 /* Check if section exist */
5062 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data));
5063 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) {
5064 err = -EINVAL;
5065 goto exit;
5066 }
5067
5068 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) {
5069 offset &= ICE_AQC_NVM_SDP_AC_PTR_M;
5070 offset *= ICE_AQC_NVM_SECTOR_UNIT;
5071 } else {
5072 offset *= sizeof(data);
5073 }
5074
5075 /* Skip reading section length and read the number of valid entries */
5076 offset += sizeof(data);
5077 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true,
5078 NULL);
5079 if (err)
5080 goto exit;
5081 *num_entries = le16_to_cpu(data);
5082
5083 /* Read SDP configuration section */
5084 offset += sizeof(data);
5085 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data),
5086 entries, false, true, NULL);
5087
5088 exit:
5089 if (err)
5090 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n");
5091 ice_release_nvm(hw);
5092 return err;
5093 }
5094
5095 /**
5096 * ice_ptp_init_phy_e810 - initialize PHY parameters
5097 * @ptp: pointer to the PTP HW struct
5098 */
ice_ptp_init_phy_e810(struct ice_ptp_hw * ptp)5099 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp)
5100 {
5101 ptp->num_lports = 8;
5102 ptp->ports_per_phy = 4;
5103
5104 init_waitqueue_head(&ptp->phy.e810.atqbal_wq);
5105 }
5106
5107 /* E830 functions
5108 *
5109 * The following functions operate on the E830 series devices.
5110 *
5111 */
5112
5113 /**
5114 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
5115 * @hw: pointer to HW struct
5116 *
5117 * Perform E830-specific PTP hardware clock initialization steps.
5118 */
ice_ptp_init_phc_e830(const struct ice_hw * hw)5119 static void ice_ptp_init_phc_e830(const struct ice_hw *hw)
5120 {
5121 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY);
5122 }
5123
5124 /**
5125 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change
5126 * @hw: pointer to HW struct
5127 * @incval: The new 40bit increment value to prepare
5128 *
5129 * Prepare the PHY port for a new increment value by programming the PHC
5130 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is
5131 * completed by FW automatically.
5132 */
ice_ptp_write_direct_incval_e830(const struct ice_hw * hw,u64 incval)5133 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw,
5134 u64 incval)
5135 {
5136 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5137
5138 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval));
5139 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval));
5140 }
5141
5142 /**
5143 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time
5144 * @hw: Board private structure
5145 * @time: Time to initialize the PHY port clock to
5146 *
5147 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
5148 * initial clock time. The time will not actually be programmed until the
5149 * driver issues an ICE_PTP_INIT_TIME command.
5150 *
5151 * The time value is the upper 32 bits of the PHY timer, usually in units of
5152 * nominal nanoseconds.
5153 */
ice_ptp_write_direct_phc_time_e830(const struct ice_hw * hw,u64 time)5154 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw,
5155 u64 time)
5156 {
5157 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5158
5159 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0);
5160 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time));
5161 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time));
5162 }
5163
5164 /**
5165 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
5166 * @hw: pointer to HW struct
5167 * @cmd: Command to be sent to the port
5168 *
5169 * Prepare the external PHYs connected to this device for a timer sync
5170 * command.
5171 *
5172 * Return: 0 on success, negative error code when PHY write failed
5173 */
ice_ptp_port_cmd_e830(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5174 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5175 {
5176 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
5177
5178 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val);
5179 }
5180
5181 /**
5182 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
5183 * @hw: pointer to the HW struct
5184 * @idx: the timestamp index to read
5185 * @tstamp: on return, the 40bit timestamp value
5186 *
5187 * Read a 40bit timestamp value out of the timestamp block of the external PHY
5188 * on the E830 device.
5189 */
ice_read_phy_tstamp_e830(const struct ice_hw * hw,u8 idx,u64 * tstamp)5190 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx,
5191 u64 *tstamp)
5192 {
5193 u32 hi, lo;
5194
5195 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx));
5196 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx));
5197
5198 /* For E830 devices, the timestamp is reported with the lower 32 bits
5199 * in the low register, and the upper 8 bits in the high register.
5200 */
5201 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
5202 FIELD_PREP(PHY_EXT_40B_LOW_M, lo);
5203 }
5204
5205 /**
5206 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register
5207 * @hw: pointer to the HW struct
5208 * @port: the PHY port to read
5209 * @tstamp_ready: contents of the Tx memory status register
5210 */
ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw * hw,u8 port,u64 * tstamp_ready)5211 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port,
5212 u64 *tstamp_ready)
5213 {
5214 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H);
5215 *tstamp_ready <<= 32;
5216 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L);
5217 }
5218
5219 /**
5220 * ice_check_phy_tx_tstamp_ready_e830 - Check Tx memory status register
5221 * @hw: pointer to the HW struct
5222 *
5223 * Return: 1 if the device has waiting timestamps, 0 otherwise.
5224 */
ice_check_phy_tx_tstamp_ready_e830(struct ice_hw * hw)5225 static int ice_check_phy_tx_tstamp_ready_e830(struct ice_hw *hw)
5226 {
5227 u64 tstamp_ready;
5228
5229 ice_get_phy_tx_tstamp_ready_e830(hw, 0, &tstamp_ready);
5230
5231 return !!tstamp_ready;
5232 }
5233
5234 /**
5235 * ice_ptp_init_phy_e830 - initialize PHY parameters
5236 * @ptp: pointer to the PTP HW struct
5237 */
ice_ptp_init_phy_e830(struct ice_ptp_hw * ptp)5238 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp)
5239 {
5240 ptp->num_lports = 8;
5241 ptp->ports_per_phy = 4;
5242 }
5243
5244 /* Device agnostic functions
5245 *
5246 * The following functions implement shared behavior common to all devices,
5247 * possibly calling a device specific implementation where necessary.
5248 */
5249
5250 /**
5251 * ice_ptp_lock - Acquire PTP global semaphore register lock
5252 * @hw: pointer to the HW struct
5253 *
5254 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
5255 * was acquired, false otherwise.
5256 *
5257 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
5258 * value. If software sees the busy bit cleared, this means that this function
5259 * acquired the lock (and the busy bit is now set). If software sees the busy
5260 * bit set, it means that another function acquired the lock.
5261 *
5262 * Software must clear the busy bit with a write to release the lock for other
5263 * functions when done.
5264 */
ice_ptp_lock(struct ice_hw * hw)5265 bool ice_ptp_lock(struct ice_hw *hw)
5266 {
5267 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
5268 u32 hw_lock;
5269 int i;
5270
5271 if (!ice_is_primary(hw))
5272 hw = ice_get_primary_hw(pf);
5273
5274 #define MAX_TRIES 15
5275
5276 for (i = 0; i < MAX_TRIES; i++) {
5277 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
5278 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
5279 if (hw_lock) {
5280 /* Somebody is holding the lock */
5281 usleep_range(5000, 6000);
5282 continue;
5283 }
5284
5285 break;
5286 }
5287
5288 return !hw_lock;
5289 }
5290
5291 /**
5292 * ice_ptp_unlock - Release PTP global semaphore register lock
5293 * @hw: pointer to the HW struct
5294 *
5295 * Release the global PTP hardware semaphore lock. This is done by writing to
5296 * the PFTSYN_SEM register.
5297 */
ice_ptp_unlock(struct ice_hw * hw)5298 void ice_ptp_unlock(struct ice_hw *hw)
5299 {
5300 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
5301
5302 if (!ice_is_primary(hw))
5303 hw = ice_get_primary_hw(pf);
5304
5305 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
5306 }
5307
5308 /**
5309 * ice_ptp_init_hw - Initialize hw based on device type
5310 * @hw: pointer to the HW structure
5311 *
5312 * Determine the PHY model for the device, and initialize hw
5313 * for use by other functions.
5314 */
ice_ptp_init_hw(struct ice_hw * hw)5315 void ice_ptp_init_hw(struct ice_hw *hw)
5316 {
5317 struct ice_ptp_hw *ptp = &hw->ptp;
5318
5319 switch (hw->mac_type) {
5320 case ICE_MAC_E810:
5321 ice_ptp_init_phy_e810(ptp);
5322 break;
5323 case ICE_MAC_E830:
5324 ice_ptp_init_phy_e830(ptp);
5325 break;
5326 case ICE_MAC_GENERIC:
5327 ice_ptp_init_phy_e82x(ptp);
5328 break;
5329 case ICE_MAC_GENERIC_3K_E825:
5330 ice_ptp_init_phy_e825(hw);
5331 break;
5332 default:
5333 return;
5334 }
5335 }
5336
5337 /**
5338 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5339 * @hw: pointer to HW struct
5340 * @port: Port to which cmd has to be sent
5341 * @cmd: Command to be sent to the port
5342 *
5343 * Prepare one port for the upcoming timer sync command. Do not use this for
5344 * programming only a single port, instead use ice_ptp_one_port_cmd() to
5345 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5346 *
5347 * Return:
5348 * * %0 - success
5349 * %-EBUSY - PHY type not supported
5350 * * %other - failed to write port command
5351 */
ice_ptp_write_port_cmd(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)5352 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
5353 enum ice_ptp_tmr_cmd cmd)
5354 {
5355 switch (hw->mac_type) {
5356 case ICE_MAC_GENERIC:
5357 return ice_ptp_write_port_cmd_e82x(hw, port, cmd);
5358 case ICE_MAC_GENERIC_3K_E825:
5359 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd);
5360 default:
5361 return -EOPNOTSUPP;
5362 }
5363 }
5364
5365 /**
5366 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5367 * @hw: pointer to HW struct
5368 * @configured_port: the port that should execute the command
5369 * @configured_cmd: the command to be executed on the configured port
5370 *
5371 * Prepare one port for executing a timer command, while preparing all other
5372 * ports to ICE_PTP_NOP. This allows executing a command on a single port
5373 * while ensuring all other ports do not execute stale commands.
5374 *
5375 * Return:
5376 * * %0 - success
5377 * * %other - failed to write port command
5378 */
ice_ptp_one_port_cmd(struct ice_hw * hw,u8 configured_port,enum ice_ptp_tmr_cmd configured_cmd)5379 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
5380 enum ice_ptp_tmr_cmd configured_cmd)
5381 {
5382 u32 port;
5383
5384 for (port = 0; port < hw->ptp.num_lports; port++) {
5385 int err;
5386
5387 /* Program the configured port with the configured command,
5388 * program all other ports with ICE_PTP_NOP.
5389 */
5390 if (port == configured_port)
5391 err = ice_ptp_write_port_cmd(hw, port, configured_cmd);
5392 else
5393 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP);
5394
5395 if (err)
5396 return err;
5397 }
5398
5399 return 0;
5400 }
5401
5402 /**
5403 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5404 * @hw: pointer to HW struct
5405 * @cmd: the timer command to setup
5406 *
5407 * Prepare all PHY ports on this device for the requested timer command. For
5408 * some families this can be done in one shot, but for other families each
5409 * port must be configured individually.
5410 *
5411 * Return:
5412 * * %0 - success
5413 * * %other - failed to write port command
5414 */
ice_ptp_port_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5415 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5416 {
5417 u32 port;
5418
5419 /* PHY models which can program all ports simultaneously */
5420 switch (hw->mac_type) {
5421 case ICE_MAC_E810:
5422 return ice_ptp_port_cmd_e810(hw, cmd);
5423 case ICE_MAC_E830:
5424 return ice_ptp_port_cmd_e830(hw, cmd);
5425 default:
5426 break;
5427 }
5428
5429 /* PHY models which require programming each port separately */
5430 for (port = 0; port < hw->ptp.num_lports; port++) {
5431 int err;
5432
5433 err = ice_ptp_write_port_cmd(hw, port, cmd);
5434 if (err)
5435 return err;
5436 }
5437
5438 return 0;
5439 }
5440
5441 /**
5442 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5443 * @hw: pointer to HW struct
5444 * @cmd: the command to issue
5445 *
5446 * Prepare the source timer and PHY timers and then trigger the requested
5447 * command. This causes the shadow registers previously written in preparation
5448 * for the command to be synchronously applied to both the source and PHY
5449 * timers.
5450 */
ice_ptp_tmr_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5451 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5452 {
5453 int err;
5454
5455 /* First, prepare the source timer */
5456 ice_ptp_src_cmd(hw, cmd);
5457
5458 /* Next, prepare the ports */
5459 err = ice_ptp_port_cmd(hw, cmd);
5460 if (err) {
5461 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
5462 cmd, err);
5463 return err;
5464 }
5465
5466 /* Write the sync command register to drive both source and PHY timer
5467 * commands synchronously
5468 */
5469 ice_ptp_exec_tmr_cmd(hw);
5470
5471 return 0;
5472 }
5473
5474 /**
5475 * ice_ptp_init_time - Initialize device time to provided value
5476 * @hw: pointer to HW struct
5477 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
5478 *
5479 * Initialize the device to the specified time provided. This requires a three
5480 * step process:
5481 *
5482 * 1) write the new init time to the source timer shadow registers
5483 * 2) write the new init time to the PHY timer shadow registers
5484 * 3) issue an init_time timer command to synchronously switch both the source
5485 * and port timers to the new init time value at the next clock cycle.
5486 */
ice_ptp_init_time(struct ice_hw * hw,u64 time)5487 int ice_ptp_init_time(struct ice_hw *hw, u64 time)
5488 {
5489 u8 tmr_idx;
5490 int err;
5491
5492 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5493
5494 /* Source timers */
5495 /* For E830 we don't need to use shadow registers, its automatic */
5496 if (hw->mac_type == ICE_MAC_E830) {
5497 ice_ptp_write_direct_phc_time_e830(hw, time);
5498 return 0;
5499 }
5500
5501 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time));
5502 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time));
5503 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
5504
5505 /* PHY timers */
5506 /* Fill Rx and Tx ports and send msg to PHY */
5507 switch (hw->mac_type) {
5508 case ICE_MAC_E810:
5509 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
5510 break;
5511 case ICE_MAC_GENERIC:
5512 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF);
5513 break;
5514 case ICE_MAC_GENERIC_3K_E825:
5515 err = ice_ptp_prep_phy_time_eth56g(hw,
5516 (u32)(time & 0xFFFFFFFF));
5517 break;
5518 default:
5519 err = -EOPNOTSUPP;
5520 }
5521
5522 if (err)
5523 return err;
5524
5525 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);
5526 }
5527
5528 /**
5529 * ice_ptp_write_incval - Program PHC with new increment value
5530 * @hw: pointer to HW struct
5531 * @incval: Source timer increment value per clock cycle
5532 *
5533 * Program the PHC with a new increment value. This requires a three-step
5534 * process:
5535 *
5536 * 1) Write the increment value to the source timer shadow registers
5537 * 2) Write the increment value to the PHY timer shadow registers
5538 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both
5539 * the source and port timers to the new increment value at the next clock
5540 * cycle.
5541 */
ice_ptp_write_incval(struct ice_hw * hw,u64 incval)5542 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
5543 {
5544 u8 tmr_idx;
5545 int err;
5546
5547 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5548
5549 /* For E830 we don't need to use shadow registers, its automatic */
5550 if (hw->mac_type == ICE_MAC_E830) {
5551 ice_ptp_write_direct_incval_e830(hw, incval);
5552 return 0;
5553 }
5554
5555 /* Shadow Adjust */
5556 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
5557 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
5558
5559 switch (hw->mac_type) {
5560 case ICE_MAC_E810:
5561 err = ice_ptp_prep_phy_incval_e810(hw, incval);
5562 break;
5563 case ICE_MAC_GENERIC:
5564 err = ice_ptp_prep_phy_incval_e82x(hw, incval);
5565 break;
5566 case ICE_MAC_GENERIC_3K_E825:
5567 err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
5568 break;
5569 default:
5570 err = -EOPNOTSUPP;
5571 }
5572
5573 if (err)
5574 return err;
5575
5576 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);
5577 }
5578
5579 /**
5580 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5581 * @hw: pointer to HW struct
5582 * @incval: Source timer increment value per clock cycle
5583 *
5584 * Program a new PHC incval while holding the PTP semaphore.
5585 */
ice_ptp_write_incval_locked(struct ice_hw * hw,u64 incval)5586 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
5587 {
5588 int err;
5589
5590 if (!ice_ptp_lock(hw))
5591 return -EBUSY;
5592
5593 err = ice_ptp_write_incval(hw, incval);
5594
5595 ice_ptp_unlock(hw);
5596
5597 return err;
5598 }
5599
5600 /**
5601 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5602 * @hw: pointer to HW struct
5603 * @adj: Adjustment in nanoseconds
5604 *
5605 * Perform an atomic adjustment of the PHC time by the specified number of
5606 * nanoseconds. This requires a three-step process:
5607 *
5608 * 1) Write the adjustment to the source timer shadow registers
5609 * 2) Write the adjustment to the PHY timer shadow registers
5610 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the
5611 * adjustment to both the source and port timers at the next clock cycle.
5612 */
ice_ptp_adj_clock(struct ice_hw * hw,s32 adj)5613 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
5614 {
5615 int err = 0;
5616 u8 tmr_idx;
5617
5618 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5619
5620 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
5621 * For an ICE_PTP_ADJ_TIME command, this set of registers represents
5622 * the value to add to the clock time. It supports subtraction by
5623 * interpreting the value as a 2's complement integer.
5624 */
5625 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
5626 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
5627
5628 switch (hw->mac_type) {
5629 case ICE_MAC_E810:
5630 err = ice_ptp_prep_phy_adj_e810(hw, adj);
5631 break;
5632 case ICE_MAC_E830:
5633 /* E830 sync PHYs automatically after setting cmd register */
5634 break;
5635 case ICE_MAC_GENERIC:
5636 err = ice_ptp_prep_phy_adj_e82x(hw, adj);
5637 break;
5638 case ICE_MAC_GENERIC_3K_E825:
5639 err = ice_ptp_prep_phy_adj_eth56g(hw, adj);
5640 break;
5641 default:
5642 err = -EOPNOTSUPP;
5643 }
5644
5645 if (err)
5646 return err;
5647
5648 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);
5649 }
5650
5651 /**
5652 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5653 * @hw: pointer to the HW struct
5654 * @block: the block to read from
5655 * @idx: the timestamp index to read
5656 * @tstamp: on return, the 40bit timestamp value
5657 *
5658 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
5659 * the block is the quad to read from. For E810 devices, the block is the
5660 * logical port to read from.
5661 */
ice_read_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx,u64 * tstamp)5662 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
5663 {
5664 switch (hw->mac_type) {
5665 case ICE_MAC_E810:
5666 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
5667 case ICE_MAC_E830:
5668 ice_read_phy_tstamp_e830(hw, idx, tstamp);
5669 return 0;
5670 case ICE_MAC_GENERIC:
5671 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp);
5672 case ICE_MAC_GENERIC_3K_E825:
5673 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp);
5674 default:
5675 return -EOPNOTSUPP;
5676 }
5677 }
5678
5679 /**
5680 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
5681 * @hw: pointer to the HW struct
5682 * @block: the block to read from
5683 * @idx: the timestamp index to reset
5684 *
5685 * Clear a timestamp from the timestamp block, discarding its value without
5686 * returning it. This resets the memory status bit for the timestamp index
5687 * allowing it to be reused for another timestamp in the future.
5688 *
5689 * For E822 devices, the block number is the PHY quad to clear from. For E810
5690 * devices, the block number is the logical port to clear from.
5691 *
5692 * This function must only be called on a timestamp index whose valid bit is
5693 * set according to ice_get_phy_tx_tstamp_ready().
5694 */
ice_clear_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx)5695 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
5696 {
5697 switch (hw->mac_type) {
5698 case ICE_MAC_E810:
5699 return ice_clear_phy_tstamp_e810(hw, block, idx);
5700 case ICE_MAC_GENERIC:
5701 return ice_clear_phy_tstamp_e82x(hw, block, idx);
5702 case ICE_MAC_GENERIC_3K_E825:
5703 return ice_clear_ptp_tstamp_eth56g(hw, block, idx);
5704 default:
5705 return -EOPNOTSUPP;
5706 }
5707 }
5708
5709 /**
5710 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
5711 * @hw: pointer to the hw struct
5712 * @idx: index of the found C827 PHY
5713 * Return:
5714 * * 0 - success
5715 * * negative - failure
5716 */
ice_get_pf_c827_idx(struct ice_hw * hw,u8 * idx)5717 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
5718 {
5719 struct ice_aqc_get_link_topo cmd;
5720 u8 node_part_number;
5721 u16 node_handle;
5722 int status;
5723 u8 ctx;
5724
5725 if (hw->mac_type != ICE_MAC_E810)
5726 return -ENODEV;
5727
5728 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) {
5729 *idx = C827_0;
5730 return 0;
5731 }
5732
5733 memset(&cmd, 0, sizeof(cmd));
5734
5735 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S;
5736 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S;
5737 cmd.addr.topo_params.node_type_ctx = ctx;
5738
5739 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
5740 &node_handle);
5741 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
5742 return -ENOENT;
5743
5744 if (node_handle == E810C_QSFP_C827_0_HANDLE)
5745 *idx = C827_0;
5746 else if (node_handle == E810C_QSFP_C827_1_HANDLE)
5747 *idx = C827_1;
5748 else
5749 return -EIO;
5750
5751 return 0;
5752 }
5753
5754 /**
5755 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
5756 * @hw: pointer to the HW struct
5757 */
ice_ptp_reset_ts_memory(struct ice_hw * hw)5758 void ice_ptp_reset_ts_memory(struct ice_hw *hw)
5759 {
5760 switch (hw->mac_type) {
5761 case ICE_MAC_GENERIC:
5762 ice_ptp_reset_ts_memory_e82x(hw);
5763 break;
5764 case ICE_MAC_GENERIC_3K_E825:
5765 ice_ptp_reset_ts_memory_eth56g(hw);
5766 break;
5767 case ICE_MAC_E810:
5768 default:
5769 return;
5770 }
5771 }
5772
5773 /**
5774 * ice_ptp_init_phc - Initialize PTP hardware clock
5775 * @hw: pointer to the HW struct
5776 *
5777 * Perform the steps required to initialize the PTP hardware clock.
5778 */
ice_ptp_init_phc(struct ice_hw * hw)5779 int ice_ptp_init_phc(struct ice_hw *hw)
5780 {
5781 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5782
5783 /* Enable source clocks */
5784 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
5785
5786 /* Clear event err indications for auxiliary pins */
5787 (void)rd32(hw, GLTSYN_STAT(src_idx));
5788
5789 switch (hw->mac_type) {
5790 case ICE_MAC_E810:
5791 return ice_ptp_init_phc_e810(hw);
5792 case ICE_MAC_E830:
5793 ice_ptp_init_phc_e830(hw);
5794 return 0;
5795 case ICE_MAC_GENERIC:
5796 return ice_ptp_init_phc_e82x(hw);
5797 case ICE_MAC_GENERIC_3K_E825:
5798 return ice_ptp_init_phc_e825c(hw);
5799 default:
5800 return -EOPNOTSUPP;
5801 }
5802 }
5803
5804 /**
5805 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
5806 * @hw: pointer to the HW struct
5807 * @block: the timestamp block to check
5808 * @tstamp_ready: storage for the PHY Tx memory status information
5809 *
5810 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
5811 * which indicates which timestamps in the block may be captured. A set bit
5812 * means the timestamp can be read. An unset bit means the timestamp is not
5813 * ready and software should avoid reading the register.
5814 */
ice_get_phy_tx_tstamp_ready(struct ice_hw * hw,u8 block,u64 * tstamp_ready)5815 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
5816 {
5817 switch (hw->mac_type) {
5818 case ICE_MAC_E810:
5819 return ice_get_phy_tx_tstamp_ready_e810(hw, block,
5820 tstamp_ready);
5821 case ICE_MAC_E830:
5822 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready);
5823 return 0;
5824 case ICE_MAC_GENERIC:
5825 return ice_get_phy_tx_tstamp_ready_e82x(hw, block,
5826 tstamp_ready);
5827 case ICE_MAC_GENERIC_3K_E825:
5828 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
5829 tstamp_ready);
5830 default:
5831 return -EOPNOTSUPP;
5832 }
5833 }
5834
5835 /**
5836 * ice_check_phy_tx_tstamp_ready - Check PHY Tx timestamp memory status
5837 * @hw: pointer to the HW struct
5838 *
5839 * Check the PHY for Tx timestamp memory status on all ports. If you need to
5840 * see individual timestamp status for each index, use
5841 * ice_get_phy_tx_tstamp_ready() instead.
5842 *
5843 * Return: 1 if any port has timestamps available, 0 if there are no timestamps
5844 * available, and a negative error code on failure.
5845 */
ice_check_phy_tx_tstamp_ready(struct ice_hw * hw)5846 int ice_check_phy_tx_tstamp_ready(struct ice_hw *hw)
5847 {
5848 switch (hw->mac_type) {
5849 case ICE_MAC_E810:
5850 return ice_check_phy_tx_tstamp_ready_e810(hw);
5851 case ICE_MAC_E830:
5852 return ice_check_phy_tx_tstamp_ready_e830(hw);
5853 case ICE_MAC_GENERIC:
5854 return ice_check_phy_tx_tstamp_ready_e82x(hw);
5855 case ICE_MAC_GENERIC_3K_E825:
5856 return ice_check_phy_tx_tstamp_ready_eth56g(hw);
5857 default:
5858 return -EOPNOTSUPP;
5859 }
5860 }
5861
5862 /**
5863 * ice_cgu_get_pin_desc_e823 - get pin description array
5864 * @hw: pointer to the hw struct
5865 * @input: if request is done against input or output pin
5866 * @size: number of inputs/outputs
5867 *
5868 * Return: pointer to pin description array associated to given hw.
5869 */
5870 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc_e823(struct ice_hw * hw,bool input,int * size)5871 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size)
5872 {
5873 static const struct ice_cgu_pin_desc *t;
5874
5875 if (hw->cgu_part_number ==
5876 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) {
5877 if (input) {
5878 t = ice_e823_zl_cgu_inputs;
5879 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs);
5880 } else {
5881 t = ice_e823_zl_cgu_outputs;
5882 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs);
5883 }
5884 } else if (hw->cgu_part_number ==
5885 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) {
5886 if (input) {
5887 t = ice_e823_si_cgu_inputs;
5888 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs);
5889 } else {
5890 t = ice_e823_si_cgu_outputs;
5891 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs);
5892 }
5893 } else {
5894 t = NULL;
5895 *size = 0;
5896 }
5897
5898 return t;
5899 }
5900
5901 /**
5902 * ice_cgu_get_pin_desc - get pin description array
5903 * @hw: pointer to the hw struct
5904 * @input: if request is done against input or output pins
5905 * @size: size of array returned by function
5906 *
5907 * Return: pointer to pin description array associated to given hw.
5908 */
5909 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc(struct ice_hw * hw,bool input,int * size)5910 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
5911 {
5912 const struct ice_cgu_pin_desc *t = NULL;
5913
5914 switch (hw->device_id) {
5915 case ICE_DEV_ID_E810C_SFP:
5916 if (input) {
5917 t = ice_e810t_sfp_cgu_inputs;
5918 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs);
5919 } else {
5920 t = ice_e810t_sfp_cgu_outputs;
5921 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs);
5922 }
5923 break;
5924 case ICE_DEV_ID_E810C_QSFP:
5925 if (input) {
5926 t = ice_e810t_qsfp_cgu_inputs;
5927 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs);
5928 } else {
5929 t = ice_e810t_qsfp_cgu_outputs;
5930 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs);
5931 }
5932 break;
5933 case ICE_DEV_ID_E823L_10G_BASE_T:
5934 case ICE_DEV_ID_E823L_1GBE:
5935 case ICE_DEV_ID_E823L_BACKPLANE:
5936 case ICE_DEV_ID_E823L_QSFP:
5937 case ICE_DEV_ID_E823L_SFP:
5938 case ICE_DEV_ID_E823C_10G_BASE_T:
5939 case ICE_DEV_ID_E823C_BACKPLANE:
5940 case ICE_DEV_ID_E823C_QSFP:
5941 case ICE_DEV_ID_E823C_SFP:
5942 case ICE_DEV_ID_E823C_SGMII:
5943 t = ice_cgu_get_pin_desc_e823(hw, input, size);
5944 break;
5945 default:
5946 break;
5947 }
5948
5949 return t;
5950 }
5951
5952 /**
5953 * ice_cgu_get_num_pins - get pin description array size
5954 * @hw: pointer to the hw struct
5955 * @input: if request is done against input or output pins
5956 *
5957 * Return: size of pin description array for given hw.
5958 */
ice_cgu_get_num_pins(struct ice_hw * hw,bool input)5959 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input)
5960 {
5961 const struct ice_cgu_pin_desc *t;
5962 int size;
5963
5964 t = ice_cgu_get_pin_desc(hw, input, &size);
5965 if (t)
5966 return size;
5967
5968 return 0;
5969 }
5970
5971 /**
5972 * ice_cgu_get_pin_type - get pin's type
5973 * @hw: pointer to the hw struct
5974 * @pin: pin index
5975 * @input: if request is done against input or output pin
5976 *
5977 * Return: type of a pin.
5978 */
ice_cgu_get_pin_type(struct ice_hw * hw,u8 pin,bool input)5979 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input)
5980 {
5981 const struct ice_cgu_pin_desc *t;
5982 int t_size;
5983
5984 t = ice_cgu_get_pin_desc(hw, input, &t_size);
5985
5986 if (!t)
5987 return 0;
5988
5989 if (pin >= t_size)
5990 return 0;
5991
5992 return t[pin].type;
5993 }
5994
5995 /**
5996 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
5997 * @hw: pointer to the hw struct
5998 * @pin: pin index
5999 * @input: if request is done against input or output pin
6000 * @num: output number of supported frequencies
6001 *
6002 * Get frequency supported number and array of supported frequencies.
6003 *
6004 * Return: array of supported frequencies for given pin.
6005 */
6006 struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw * hw,u8 pin,bool input,u8 * num)6007 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
6008 {
6009 const struct ice_cgu_pin_desc *t;
6010 int t_size;
6011
6012 *num = 0;
6013 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6014 if (!t)
6015 return NULL;
6016 if (pin >= t_size)
6017 return NULL;
6018 *num = t[pin].freq_supp_num;
6019
6020 return t[pin].freq_supp;
6021 }
6022
6023 /**
6024 * ice_cgu_get_pin_name - get pin's name
6025 * @hw: pointer to the hw struct
6026 * @pin: pin index
6027 * @input: if request is done against input or output pin
6028 *
6029 * Return:
6030 * * null terminated char array with name
6031 * * NULL in case of failure
6032 */
ice_cgu_get_pin_name(struct ice_hw * hw,u8 pin,bool input)6033 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input)
6034 {
6035 const struct ice_cgu_pin_desc *t;
6036 int t_size;
6037
6038 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6039
6040 if (!t)
6041 return NULL;
6042
6043 if (pin >= t_size)
6044 return NULL;
6045
6046 return t[pin].name;
6047 }
6048
6049 /**
6050 * ice_get_cgu_state - get the state of the DPLL
6051 * @hw: pointer to the hw struct
6052 * @dpll_idx: Index of internal DPLL unit
6053 * @last_dpll_state: last known state of DPLL
6054 * @pin: pointer to a buffer for returning currently active pin
6055 * @ref_state: reference clock state
6056 * @eec_mode: eec mode of the DPLL
6057 * @phase_offset: pointer to a buffer for returning phase offset
6058 * @dpll_state: state of the DPLL (output)
6059 *
6060 * This function will read the state of the DPLL(dpll_idx). Non-null
6061 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
6062 * retrieve currently active pin, state, mode and phase_offset respectively.
6063 *
6064 * Return: state of the DPLL
6065 */
ice_get_cgu_state(struct ice_hw * hw,u8 dpll_idx,enum dpll_lock_status last_dpll_state,u8 * pin,u8 * ref_state,u8 * eec_mode,s64 * phase_offset,enum dpll_lock_status * dpll_state)6066 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
6067 enum dpll_lock_status last_dpll_state, u8 *pin,
6068 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
6069 enum dpll_lock_status *dpll_state)
6070 {
6071 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config;
6072 s64 hw_phase_offset;
6073 int status;
6074
6075 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state,
6076 &hw_dpll_state, &hw_config,
6077 &hw_phase_offset, &hw_eec_mode);
6078 if (status)
6079 return status;
6080
6081 if (pin)
6082 /* current ref pin in dpll_state_refsel_status_X register */
6083 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL;
6084 if (phase_offset)
6085 *phase_offset = hw_phase_offset;
6086 if (ref_state)
6087 *ref_state = hw_ref_state;
6088 if (eec_mode)
6089 *eec_mode = hw_eec_mode;
6090 if (!dpll_state)
6091 return 0;
6092
6093 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ
6094 * it would never return to FREERUN. This aligns to ITU-T G.781
6095 * Recommendation. We cannot report HOLDOVER as HO memory is cleared
6096 * while switching to another reference.
6097 * Only for situations where previous state was either: "LOCKED without
6098 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN.
6099 */
6100 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) {
6101 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY)
6102 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
6103 else
6104 *dpll_state = DPLL_LOCK_STATUS_LOCKED;
6105 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ ||
6106 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) {
6107 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
6108 } else {
6109 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
6110 }
6111
6112 return 0;
6113 }
6114
6115 /**
6116 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6117 * @hw: pointer to the hw struct
6118 * @base_idx: returns index of first recovered clock pin on device
6119 * @pin_num: returns number of recovered clock pins available on device
6120 *
6121 * Based on hw provide caller info about recovery clock pins available on the
6122 * board.
6123 *
6124 * Return:
6125 * * 0 - success, information is valid
6126 * * negative - failure, information is not valid
6127 */
ice_get_cgu_rclk_pin_info(struct ice_hw * hw,u8 * base_idx,u8 * pin_num)6128 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
6129 {
6130 u8 phy_idx;
6131 int ret;
6132
6133 switch (hw->device_id) {
6134 case ICE_DEV_ID_E810C_SFP:
6135 case ICE_DEV_ID_E810C_QSFP:
6136
6137 ret = ice_get_pf_c827_idx(hw, &phy_idx);
6138 if (ret)
6139 return ret;
6140 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN);
6141 *pin_num = ICE_E810_RCLK_PINS_NUM;
6142 ret = 0;
6143 break;
6144 case ICE_DEV_ID_E823L_10G_BASE_T:
6145 case ICE_DEV_ID_E823L_1GBE:
6146 case ICE_DEV_ID_E823L_BACKPLANE:
6147 case ICE_DEV_ID_E823L_QSFP:
6148 case ICE_DEV_ID_E823L_SFP:
6149 case ICE_DEV_ID_E823C_10G_BASE_T:
6150 case ICE_DEV_ID_E823C_BACKPLANE:
6151 case ICE_DEV_ID_E823C_QSFP:
6152 case ICE_DEV_ID_E823C_SFP:
6153 case ICE_DEV_ID_E823C_SGMII:
6154 *pin_num = ICE_E82X_RCLK_PINS_NUM;
6155 ret = 0;
6156 if (hw->cgu_part_number ==
6157 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)
6158 *base_idx = ZL_REF1P;
6159 else if (hw->cgu_part_number ==
6160 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384)
6161 *base_idx = SI_REF1P;
6162 else
6163 ret = -ENODEV;
6164 break;
6165 case ICE_DEV_ID_E825C_BACKPLANE:
6166 case ICE_DEV_ID_E825C_QSFP:
6167 case ICE_DEV_ID_E825C_SFP:
6168 case ICE_DEV_ID_E825C_SGMII:
6169 *pin_num = ICE_SYNCE_CLK_NUM;
6170 *base_idx = 0;
6171 ret = 0;
6172 break;
6173 default:
6174 ret = -ENODEV;
6175 break;
6176 }
6177
6178 return ret;
6179 }
6180
6181 /**
6182 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6183 * @hw: pointer to the hw struct
6184 * @pin_id: id of a pin
6185 * @caps: capabilities to modify
6186 *
6187 * Return:
6188 * * 0 - success, state capabilities were modified
6189 * * negative - failure, capabilities were not modified
6190 */
ice_cgu_get_output_pin_state_caps(struct ice_hw * hw,u8 pin_id,unsigned long * caps)6191 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
6192 unsigned long *caps)
6193 {
6194 bool can_change = true;
6195
6196 switch (hw->device_id) {
6197 case ICE_DEV_ID_E810C_SFP:
6198 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
6199 can_change = false;
6200 break;
6201 case ICE_DEV_ID_E810C_QSFP:
6202 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
6203 can_change = false;
6204 break;
6205 case ICE_DEV_ID_E823L_10G_BASE_T:
6206 case ICE_DEV_ID_E823L_1GBE:
6207 case ICE_DEV_ID_E823L_BACKPLANE:
6208 case ICE_DEV_ID_E823L_QSFP:
6209 case ICE_DEV_ID_E823L_SFP:
6210 case ICE_DEV_ID_E823C_10G_BASE_T:
6211 case ICE_DEV_ID_E823C_BACKPLANE:
6212 case ICE_DEV_ID_E823C_QSFP:
6213 case ICE_DEV_ID_E823C_SFP:
6214 case ICE_DEV_ID_E823C_SGMII:
6215 if (hw->cgu_part_number ==
6216 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
6217 pin_id == ZL_OUT2)
6218 can_change = false;
6219 else if (hw->cgu_part_number ==
6220 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
6221 pin_id == SI_OUT1)
6222 can_change = false;
6223 break;
6224 default:
6225 return -EINVAL;
6226 }
6227 if (can_change)
6228 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6229 else
6230 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6231
6232 return 0;
6233 }
6234