Searched refs:wm_table (Results 1 – 12 of 12) sorted by relevance
33 extern struct wm_table ddr4_wm_table_gs;34 extern struct wm_table lpddr4_wm_table_gs;35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;36 extern struct wm_table ddr4_wm_table_rn;37 extern struct wm_table ddr4_1R_wm_table_rn;38 extern struct wm_table lpddr4_wm_table_rn;
462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()679 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()682 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()686 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in rn_clk_mgr_helper_populate_bw_params()687 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()745 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; in rn_clk_mgr_construct()748 rn_bw_params.wm_table = lpddr4_wm_table_gs; in rn_clk_mgr_construct()750 rn_bw_params.wm_table = lpddr4_wm_table_rn; in rn_clk_mgr_construct()[all …]
32 extern struct wm_table ddr4_wm_table;33 extern struct wm_table lpddr5_wm_table;
341 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn3_notify_wm_ranges()342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()345 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()347 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
189 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table()190 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table()191 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()192 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()193 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table()194 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()197 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false; in dcn401_build_wm_range_table()202 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true; in dcn401_build_wm_range_table()203 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; in dcn401_build_wm_range_table()204 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()[all …]
247 struct wm_table { struct267 struct wm_table wm_table; argument
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
763 static struct wm_table ddr5_wm_table = {800 static struct wm_table lpddr5_wm_table = {872 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()875 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()876 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()1178 bw_params->wm_table.entries[i].wm_inst = i; in dcn35_clk_mgr_helper_populate_bw_params()1181 bw_params->wm_table.entries[i].valid = false; in dcn35_clk_mgr_helper_populate_bw_params()1185 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn35_clk_mgr_helper_populate_bw_params()1186 bw_params->wm_table.entries[i].valid = true; in dcn35_clk_mgr_helper_populate_bw_params()1468 dcn35_bw_params.wm_table = lpddr5_wm_table; in dcn35_clk_mgr_construct()[all …]
984 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn32_notify_wm_ranges()986 …table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_bre… in dcn32_notify_wm_ranges()
2581 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local2586 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
3709 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local3714 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
4830 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local4835 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()