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Searched refs:vgpu_vreg_t (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c74 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
91 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
194 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change()
200 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= in emulate_monitor_status_change()
202 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
203 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
204 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
205 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
209 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= in emulate_monitor_status_change()
213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
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H A Dfb_decoder.c159 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask; in intel_vgpu_get_stride()
222 val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)); in intel_vgpu_decode_primary_plane()
256 plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
272 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
275 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & in intel_vgpu_decode_primary_plane()
279 val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe)); in intel_vgpu_decode_primary_plane()
354 val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe)); in intel_vgpu_decode_cursor_plane()
380 plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane()
391 val = vgpu_vreg_t(vgpu, CURPOS(display, pipe)); in intel_vgpu_decode_cursor_plane()
397 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane()
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H A Dedid.c133 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller()
135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller()
167 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus0_mmio_write()
168 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; in gmbus0_mmio_write()
174 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; in gmbus0_mmio_write()
176 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in gmbus0_mmio_write()
203 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; in gmbus1_mmio_write()
204 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; in gmbus1_mmio_write()
252 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus1_mmio_write()
264 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; in gmbus1_mmio_write()
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H A Dmmio_context.c237 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
267 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
294 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
400 vgpu_vreg_t(vgpu, reg) = 0; in handle_tlb_pending_event()
434 old_v = vgpu_vreg_t(pre, offset); in switch_mocs()
438 new_v = vgpu_vreg_t(next, offset); in switch_mocs()
452 old_v = vgpu_vreg_t(pre, l3_offset); in switch_mocs()
456 new_v = vgpu_vreg_t(next, l3_offset); in switch_mocs()
507 vgpu_vreg_t(pre, mmio->reg) = in switch_mmio()
510 vgpu_vreg_t(pre, mmio->reg) &= in switch_mmio()
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H A Dhandlers.c355 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write()
387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
388 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; in pch_pp_control_mmio_write()
389 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; in pch_pp_control_mmio_write()
390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; in pch_pp_control_mmio_write()
393 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write()
472 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); in bdw_vgpu_get_dp_bitrate()
486 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate()
498 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()
510 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); in bdw_vgpu_get_dp_bitrate()
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H A Dcmd_parser.c1401 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); in gen8_check_mi_display_flip()
1402 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip()
1405 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & in gen8_check_mi_display_flip()
1407 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip()
1427 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), in gen8_update_plane_mmio_from_mi_display_flip()
1430 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), in gen8_update_plane_mmio_from_mi_display_flip()
1432 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1435 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), in gen8_update_plane_mmio_from_mi_display_flip()
1437 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1442 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++; in gen8_update_plane_mmio_from_mi_display_flip()
H A Dgvt.h457 #define vgpu_vreg_t(vgpu, reg) \ macro