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Searched refs:upper_32_bits (Results 1 – 25 of 451) sorted by relevance

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/linux/drivers/gpu/drm/radeon/
H A Dsi_dma.c82 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
83 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
121 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
133 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
173 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages()
177 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages()
265 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
H A Devergreen_dma.c48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
142 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
143 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
H A Dni_dma.c134 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
222 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
331 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
370 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
382 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages()
422 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages()
426 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
H A Dr600_dma.c143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
295 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
322 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
415 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
426 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
478 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
479 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
H A Dcik_sdma.c145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
208 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
237 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
400 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
614 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
616 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
728 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test()
817 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c150 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
218 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
232 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
240 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
289 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v7_0_ring_emit_ib()
292 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v7_0_ring_emit_ib()
368 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
379 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
380 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v7_0_ring_emit_fence()
502 …WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(r… in sdma_v7_0_gfx_resume_instance()
[all …]
H A Dsdma_v6_0.c152 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
218 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
232 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
238 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
287 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
290 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
366 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
377 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
378 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
512 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(r… in sdma_v6_0_gfx_resume_instance()
[all …]
H A Dsdma_v7_1.c144 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_1_ring_init_cond_exec()
212 upper_32_bits(ring->wptr << 2)); in sdma_v7_1_ring_set_wptr()
226 upper_32_bits(ring->wptr << 2)); in sdma_v7_1_ring_set_wptr()
234 upper_32_bits(ring->wptr << 2)); in sdma_v7_1_ring_set_wptr()
283 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v7_1_ring_emit_ib()
286 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v7_1_ring_emit_ib()
336 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
347 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
348 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v7_1_ring_emit_fence()
484 …, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << … in sdma_v7_1_gfx_resume_instance()
[all …]
H A Dsdma_v5_2.c149 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
222 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
237 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
246 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
250 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
299 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
302 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
382 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
393 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
394 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
[all …]
H A Dsdma_v5_0.c309 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
382 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
396 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
402 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
451 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
454 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
532 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
543 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
544 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
717 …WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring-… in sdma_v5_0_gfx_resume_instance()
[all …]
H A Dsdma_v4_4_2.c276 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
289 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
293 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
344 upper_32_bits(wptr)); in sdma_v4_4_2_page_ring_set_wptr()
385 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_4_2_ring_emit_ib()
460 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v4_4_2_ring_emit_fence()
470 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v4_4_2_ring_emit_fence()
471 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v4_4_2_ring_emit_fence()
701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v4_4_2_gfx_resume()
728 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); in sdma_v4_4_2_gfx_resume()
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H A Dumsch_mm_v4_0.c92 upper_32_bits(adev->umsch_mm.irq_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
97 upper_32_bits(adev->umsch_mm.uc_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
104 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data)); in umsch_mm_v4_0_load_microcode()
109 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data)); in umsch_mm_v4_0_load_microcode()
116 upper_32_bits(adev->umsch_mm.data_start_addr)); in umsch_mm_v4_0_load_microcode()
125 WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data)); in umsch_mm_v4_0_load_microcode()
148 WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, upper_32_bits(umsch->log_gpu_addr)); in umsch_mm_v4_0_load_microcode()
229 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in umsch_mm_v4_0_ring_start()
H A Dlsdma_v7_0.c48 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); in lsdma_v7_0_copy_mem()
51 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v7_0_copy_mem()
83 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v7_0_fill_mem()
/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dring.c28 dma_h = upper_32_bits(next_dma); in xge_setup_desc()
40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr()
52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c127 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
151 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
197 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
200 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
202 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
224 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
339 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
343 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_vi.c117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
131 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); in init_mqd()
133 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); in init_mqd()
144 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
190 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
193 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
195 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd()
222 upper_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
383 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
385 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v12_1.c187 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
212 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
254 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
267 upper_32_bits((q->queue_address + q->queue_size) >> 8); in update_mqd()
278 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
280 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
302 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
414 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
416 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
418 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
[all …]
H A Dkfd_mqd_manager_v11.c148 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
176 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
222 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
225 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
227 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
249 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
465 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
467 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
469 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v10.c115 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
136 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
184 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
187 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
189 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
211 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
389 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
391 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
77 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
80 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
104 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
105 .data_dma_base1 = upper_32_bits(data), in gm20b_pmu_acr_bld_write()
106 .overlay_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
67 .data_dma_base1 = upper_32_bits(data), in gm20b_gr_acr_bld_write()
/linux/drivers/media/pci/pt3/
H A Dpt3_dma.c54 iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
185 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
191 d->addr_h = upper_32_bits(data_addr); in pt3_alloc_dmabuf()
196 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
205 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo74c1.c48 0x0308, upper_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
50 0x0310, upper_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
/linux/drivers/pci/controller/
H A Dpcie-rcar.c90 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); in rcar_pcie_set_outbound()
116 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), in rcar_pcie_set_inbound()
118 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1)); in rcar_pcie_set_inbound()
/linux/drivers/gpu/drm/tegra/
H A Driscv.c80 riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_HI); in tegra_drm_riscv_boot_bootrom()
84 riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_HI); in tegra_drm_riscv_boot_bootrom()
88 riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_HI); in tegra_drm_riscv_boot_bootrom()

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