1a032fb9dSAlexandre Courbot /*
2a032fb9dSAlexandre Courbot * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3a032fb9dSAlexandre Courbot *
4a032fb9dSAlexandre Courbot * Permission is hereby granted, free of charge, to any person obtaining a
5a032fb9dSAlexandre Courbot * copy of this software and associated documentation files (the "Software"),
6a032fb9dSAlexandre Courbot * to deal in the Software without restriction, including without limitation
7a032fb9dSAlexandre Courbot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8a032fb9dSAlexandre Courbot * and/or sell copies of the Software, and to permit persons to whom the
9a032fb9dSAlexandre Courbot * Software is furnished to do so, subject to the following conditions:
10a032fb9dSAlexandre Courbot *
11a032fb9dSAlexandre Courbot * The above copyright notice and this permission notice shall be included in
12a032fb9dSAlexandre Courbot * all copies or substantial portions of the Software.
13a032fb9dSAlexandre Courbot *
14a032fb9dSAlexandre Courbot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15a032fb9dSAlexandre Courbot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16a032fb9dSAlexandre Courbot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17a032fb9dSAlexandre Courbot * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18a032fb9dSAlexandre Courbot * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19a032fb9dSAlexandre Courbot * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20a032fb9dSAlexandre Courbot * DEALINGS IN THE SOFTWARE.
21a032fb9dSAlexandre Courbot */
22c85ee6caSBen Skeggs #include "gf100.h"
23a032fb9dSAlexandre Courbot #include "ctxgf100.h"
24a032fb9dSAlexandre Courbot
25ef16dc27SBen Skeggs #include <core/firmware.h>
26ef16dc27SBen Skeggs #include <subdev/acr.h>
27a032fb9dSAlexandre Courbot #include <subdev/timer.h>
28a032fb9dSAlexandre Courbot
2922dcda45SBen Skeggs #include <nvfw/flcn.h>
3022dcda45SBen Skeggs
3127f3d6cfSBen Skeggs #include <nvif/class.h>
32a032fb9dSAlexandre Courbot
3322dcda45SBen Skeggs void
gm20b_gr_acr_bld_patch(struct nvkm_acr * acr,u32 bld,s64 adjust)3422dcda45SBen Skeggs gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
3522dcda45SBen Skeggs {
3622dcda45SBen Skeggs struct flcn_bl_dmem_desc hdr;
3722dcda45SBen Skeggs u64 addr;
3822dcda45SBen Skeggs
3922dcda45SBen Skeggs nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
4022dcda45SBen Skeggs addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
4122dcda45SBen Skeggs hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
4222dcda45SBen Skeggs hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
4322dcda45SBen Skeggs addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
4422dcda45SBen Skeggs hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
4522dcda45SBen Skeggs hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
4622dcda45SBen Skeggs nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
4722dcda45SBen Skeggs
4822dcda45SBen Skeggs flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
4922dcda45SBen Skeggs }
5022dcda45SBen Skeggs
5122dcda45SBen Skeggs void
gm20b_gr_acr_bld_write(struct nvkm_acr * acr,u32 bld,struct nvkm_acr_lsfw * lsfw)5222dcda45SBen Skeggs gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
5322dcda45SBen Skeggs struct nvkm_acr_lsfw *lsfw)
5422dcda45SBen Skeggs {
5522dcda45SBen Skeggs const u64 base = lsfw->offset.img + lsfw->app_start_offset;
5622dcda45SBen Skeggs const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
5722dcda45SBen Skeggs const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
5822dcda45SBen Skeggs const struct flcn_bl_dmem_desc hdr = {
5922dcda45SBen Skeggs .ctx_dma = FALCON_DMAIDX_UCODE,
6022dcda45SBen Skeggs .code_dma_base = lower_32_bits(code),
6122dcda45SBen Skeggs .non_sec_code_off = lsfw->app_resident_code_offset,
6222dcda45SBen Skeggs .non_sec_code_size = lsfw->app_resident_code_size,
6322dcda45SBen Skeggs .code_entry_point = lsfw->app_imem_entry,
6422dcda45SBen Skeggs .data_dma_base = lower_32_bits(data),
6522dcda45SBen Skeggs .data_size = lsfw->app_resident_data_size,
6622dcda45SBen Skeggs .code_dma_base1 = upper_32_bits(code),
6722dcda45SBen Skeggs .data_dma_base1 = upper_32_bits(data),
6822dcda45SBen Skeggs };
6922dcda45SBen Skeggs
7022dcda45SBen Skeggs nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
7122dcda45SBen Skeggs }
7222dcda45SBen Skeggs
73ef16dc27SBen Skeggs const struct nvkm_acr_lsf_func
74ef16dc27SBen Skeggs gm20b_gr_fecs_acr = {
7522dcda45SBen Skeggs .bld_size = sizeof(struct flcn_bl_dmem_desc),
7622dcda45SBen Skeggs .bld_write = gm20b_gr_acr_bld_write,
7722dcda45SBen Skeggs .bld_patch = gm20b_gr_acr_bld_patch,
78ef16dc27SBen Skeggs };
79ef16dc27SBen Skeggs
80a032fb9dSAlexandre Courbot static void
gm20b_gr_init_gpc_mmu(struct gf100_gr * gr)81bfee3f3dSBen Skeggs gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
82a032fb9dSAlexandre Courbot {
83276836d4SBen Skeggs struct nvkm_device *device = gr->base.engine.subdev.device;
84a032fb9dSAlexandre Courbot u32 val;
85a032fb9dSAlexandre Courbot
86923f1bd2SAlexandre Courbot /* Bypass MMU check for non-secure boot */
879d350c5eSBen Skeggs if (!device->acr) {
88276836d4SBen Skeggs nvkm_wr32(device, 0x100ce4, 0xffffffff);
89923f1bd2SAlexandre Courbot
90923f1bd2SAlexandre Courbot if (nvkm_rd32(device, 0x100ce4) != 0xffffffff)
91923f1bd2SAlexandre Courbot nvdev_warn(device,
92923f1bd2SAlexandre Courbot "cannot bypass secure boot - expect failure soon!\n");
93a032fb9dSAlexandre Courbot }
94a032fb9dSAlexandre Courbot
95276836d4SBen Skeggs val = nvkm_rd32(device, 0x100c80);
96c83e7d68SBen Skeggs val &= 0xf000187f;
97276836d4SBen Skeggs nvkm_wr32(device, 0x418880, val);
98276836d4SBen Skeggs nvkm_wr32(device, 0x418890, 0);
99276836d4SBen Skeggs nvkm_wr32(device, 0x418894, 0);
100a032fb9dSAlexandre Courbot
101276836d4SBen Skeggs nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
102276836d4SBen Skeggs nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
103276836d4SBen Skeggs nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
104a032fb9dSAlexandre Courbot
105276836d4SBen Skeggs nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
106a032fb9dSAlexandre Courbot }
107a032fb9dSAlexandre Courbot
108a032fb9dSAlexandre Courbot static void
gm20b_gr_set_hww_esr_report_mask(struct gf100_gr * gr)109bfee3f3dSBen Skeggs gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
110a032fb9dSAlexandre Courbot {
111276836d4SBen Skeggs struct nvkm_device *device = gr->base.engine.subdev.device;
112276836d4SBen Skeggs nvkm_wr32(device, 0x419e44, 0xdffffe);
113276836d4SBen Skeggs nvkm_wr32(device, 0x419e4c, 0x5);
114a032fb9dSAlexandre Courbot }
115a032fb9dSAlexandre Courbot
11627f3d6cfSBen Skeggs static const struct gf100_gr_func
11727f3d6cfSBen Skeggs gm20b_gr = {
1185f6474a4SBen Skeggs .oneinit_tiles = gm200_gr_oneinit_tiles,
119068cae74SBen Skeggs .oneinit_sm_id = gm200_gr_oneinit_sm_id,
120c85ee6caSBen Skeggs .init = gk20a_gr_init,
12102917aa3SBen Skeggs .init_zcull = gf117_gr_init_zcull,
122c85ee6caSBen Skeggs .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
12387ac331eSBen Skeggs .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
1245c05a589SBen Skeggs .trap_mp = gf100_gr_trap_mp,
125c85ee6caSBen Skeggs .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
126*be99d041SBen Skeggs .fecs.reset = gf100_gr_fecs_reset,
127734a0aa6SBen Skeggs .rops = gm200_gr_rops,
128c85ee6caSBen Skeggs .ppc_nr = 1,
12927f3d6cfSBen Skeggs .grctx = &gm20b_grctx,
130e9d03335SBen Skeggs .zbc = &gf100_gr_zbc,
13127f3d6cfSBen Skeggs .sclass = {
13227f3d6cfSBen Skeggs { -1, -1, FERMI_TWOD_A },
13327f3d6cfSBen Skeggs { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
13427f3d6cfSBen Skeggs { -1, -1, MAXWELL_B, &gf100_fermi },
13527f3d6cfSBen Skeggs { -1, -1, MAXWELL_COMPUTE_B },
13627f3d6cfSBen Skeggs {}
13727f3d6cfSBen Skeggs }
13827f3d6cfSBen Skeggs };
13927f3d6cfSBen Skeggs
140ef16dc27SBen Skeggs static int
gm20b_gr_load(struct gf100_gr * gr,int ver,const struct gf100_gr_fwif * fwif)141ef16dc27SBen Skeggs gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
142ef16dc27SBen Skeggs {
143ef16dc27SBen Skeggs struct nvkm_subdev *subdev = &gr->base.engine.subdev;
144ef16dc27SBen Skeggs int ret;
145ef16dc27SBen Skeggs
1464f556362SBen Skeggs ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,
147ef16dc27SBen Skeggs NVKM_ACR_LSF_FECS,
148ef16dc27SBen Skeggs "gr/fecs_", ver, fwif->fecs);
149ef16dc27SBen Skeggs if (ret)
150ef16dc27SBen Skeggs return ret;
151ef16dc27SBen Skeggs
152ef16dc27SBen Skeggs
153ef16dc27SBen Skeggs if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver,
154ef16dc27SBen Skeggs &gr->gpccs.inst) ||
155ef16dc27SBen Skeggs nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver,
156ef16dc27SBen Skeggs &gr->gpccs.data))
157ef16dc27SBen Skeggs return -ENOENT;
158ef16dc27SBen Skeggs
159ef16dc27SBen Skeggs gr->firmware = true;
160ef16dc27SBen Skeggs
161ef16dc27SBen Skeggs return gk20a_gr_load_sw(gr, "gr/", ver);
162ef16dc27SBen Skeggs }
163ef16dc27SBen Skeggs
164ef16dc27SBen Skeggs #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
165ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
166ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
167ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
168ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
169ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
170ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
171ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
172ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
173ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
174ef16dc27SBen Skeggs MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
175ef16dc27SBen Skeggs #endif
176ef16dc27SBen Skeggs
177ef16dc27SBen Skeggs static const struct gf100_gr_fwif
178ef16dc27SBen Skeggs gm20b_gr_fwif[] = {
179ef16dc27SBen Skeggs { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr },
180b9c246adSBen Skeggs { -1, gm200_gr_nofw },
181ef16dc27SBen Skeggs {}
182ef16dc27SBen Skeggs };
183ef16dc27SBen Skeggs
184c85ee6caSBen Skeggs int
gm20b_gr_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_gr ** pgr)185864d37c3SBen Skeggs gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
186c85ee6caSBen Skeggs {
187864d37c3SBen Skeggs return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr);
188c85ee6caSBen Skeggs }
189