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Searched refs:uint32_t (Results 1 – 25 of 1706) sorted by relevance

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/linux/drivers/gpu/drm/amd/include/
H A Dv10_structs.h28 uint32_t reserved_0; // offset: 0 (0x0)
29 uint32_t reserved_1; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t reserved_4; // offset: 4 (0x4)
33 uint32_t reserved_5; // offset: 5 (0x5)
34 uint32_t reserved_6; // offset: 6 (0x6)
35 uint32_t reserved_7; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv9_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
H A Dvi_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
H A Dcik_structs.h28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
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H A Ddiscovery.h59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
76 uint32_t signature; /* Table Signature */
79 uint32_t id; /* Table ID */
107 uint32_t base_address[]; /* variable number of Addresses */
125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/
143 …DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_ba…
170 uint32_t table_id; /* table ID */
173 uint32_t size; /* size of the entire header+data in bytes */
179 uint32_t gc_num_se;
180 uint32_t gc_num_wgp0_per_sa;
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pciercx-defs.h55 uint32_t u32;
57 __BITFIELD_FIELD(uint32_t dpe:1,
58 __BITFIELD_FIELD(uint32_t sse:1,
59 __BITFIELD_FIELD(uint32_t rma:1,
60 __BITFIELD_FIELD(uint32_t rta:1,
61 __BITFIELD_FIELD(uint32_t sta:1,
62 __BITFIELD_FIELD(uint32_t devt:2,
63 __BITFIELD_FIELD(uint32_t mdpe:1,
64 __BITFIELD_FIELD(uint32_t fbb:1,
65 __BITFIELD_FIELD(uint32_t reserved_22_22:1,
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H A Dcvmx-pci-defs.h118 uint32_t u32;
121 uint32_t reserved_18_31:14;
122 uint32_t addr_idx:14;
123 uint32_t ca:1;
124 uint32_t end_swp:2;
125 uint32_t addr_v:1;
127 uint32_t addr_v:1;
128 uint32_t end_swp:2;
129 uint32_t ca:1;
130 uint32_t addr_idx:14;
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/linux/drivers/scsi/arcmsr/
H A Darcmsr.h104 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
105 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
113 uint32_t HeaderLength;
115 uint32_t Timeout;
116 uint32_t ControlCode;
117 uint32_t ReturnCode;
118 uint32_t Length;
196 uint32_t data_len;
206 uint32_t signature; /*0, 00-03*/
207 uint32_t request_len; /*1, 04-07*/
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_6_pmfw.h134 uint32_t AccumulationCounter;
137 uint32_t MaxSocketTemperature;
138 uint32_t MaxVrTemperature;
139 uint32_t MaxHbmTemperature;
145 uint32_t SocketPowerLimit;
146 uint32_t MaxSocketPowerLimit;
147 uint32_t SocketPower;
158 uint32_t CclkFrequencyLimit;
159 uint32_t GfxclkFrequencyLimit;
160 uint32_t FclkFrequency;
[all …]
H A Dsmu_v14_0_0_pmfw.h102 uint32_t Signature;
108 uint32_t ImageVersion;
109 uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug.
110 uint32_t Padding0[3];
111 uint32_t SizeFWSigned;
112 uint32_t Padding1[25];
113 uint32_t FirmwareType;
114 uint32_t Filler[32];
119 uint32_t DpmHandlerID : 8;
120 uint32_t ActivityMonitorID : 8;
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_vi.h32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < Number of DWORDS - 1 in the
37 uint32_t type : 2; /* < packet identifier
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
[all …]
H A Dkfd_pm4_headers.h33 uint32_t reserved1:8;
35 uint32_t opcode:8;
37 uint32_t count:14;
39 uint32_t type:2;
41 uint32_t u32all;
54 uint32_t ordinal1;
59 uint32_t pasid:16;
60 uint32_t reserved1:8;
61 uint32_t diq_enable:1;
62 uint32_t process_quantum:7;
[all …]
/linux/tools/firewire/
H A Dnosy-dump.h15 uint32_t timestamp;
18 uint32_t zero:24;
19 uint32_t phy_id:6;
20 uint32_t identifier:2;
24 uint32_t zero:16;
25 uint32_t gap_count:6;
26 uint32_t set_gap_count:1;
27 uint32_t set_root:1;
28 uint32_t root_id:6;
29 uint32_t identifier:2;
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ucode.h31 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
32 uint32_t header_size_bytes; /* size of just the header in bytes */
37 uint32_t ucode_version;
38 uint32_t ucode_size_bytes; /* size of ucode in bytes */
39 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
40 uint32_t crc32; /* crc32 checksum of the payload */
46 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
47 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
53 uint32_t ucode_start_addr;
59 uint32_t ppt_offset_bytes; /* soft pptable offset */
[all …]
H A Damdgpu_socbb.h27 uint32_t state;
28 uint32_t dscclk_mhz;
29 uint32_t dcfclk_mhz;
30 uint32_t socclk_mhz;
31 uint32_t dram_speed_mts;
32 uint32_t fabricclk_mhz;
33 uint32_t dispclk_mhz;
34 uint32_t phyclk_mhz;
35 uint32_t dppclk_mhz;
39 uint32_t sr_exit_time_us;
[all …]
/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
92 uint32_t word;
155 uint32_t PortId; /* For RNN_ID requests */
164 uint32_t port_id;
167 uint32_t PortId;
177 uint32_t PortId;
183 uint32_t PortId;
186 uint32_t fc4_types[8];
[all …]
/linux/fs/xfs/
H A Dxfs_stats.h44 uint32_t xs_allocx;
45 uint32_t xs_allocb;
46 uint32_t xs_freex;
47 uint32_t xs_freeb;
48 uint32_t xs_abt_lookup;
49 uint32_t xs_abt_compare;
50 uint32_t xs_abt_insrec;
51 uint32_t xs_abt_delrec;
52 uint32_t xs_blk_mapr;
53 uint32_t xs_blk_mapw;
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_drv.h70 uint32_t osd1_ctrl_stat;
71 uint32_t osd1_ctrl_stat2;
72 uint32_t osd1_blk0_cfg[5];
73 uint32_t osd1_blk1_cfg4;
74 uint32_t osd1_blk2_cfg4;
75 uint32_t osd1_addr;
76 uint32_t osd1_stride;
77 uint32_t osd1_height;
78 uint32_t osd1_width;
79 uint32_t osd_sc_ctrl0;
[all …]
/linux/include/uapi/linux/
H A Dfuse.h293 uint32_t atimensec;
294 uint32_t mtimensec;
295 uint32_t ctimensec;
296 uint32_t mode;
297 uint32_t nlink;
298 uint32_t uid;
299 uint32_t gid;
300 uint32_t rdev;
301 uint32_t blksize;
302 uint32_t flags;
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.h45 uint32_t soft_min_clk;
46 uint32_t hard_min_clk;
47 uint32_t soft_max_clk;
48 uint32_t hard_max_clk;
52 uint32_t bootup_uma_clock;
53 uint32_t bootup_engine_clock;
54 uint32_t dentist_vco_freq;
55 uint32_t nb_dpm_enable;
56 uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
57 uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
[all …]
H A Dsmu7_hwmgr.h47 uint32_t offset;
48 uint32_t mask;
49 uint32_t shift;
50 uint32_t value;
55 uint32_t memory_clock;
56 uint32_t engine_clock;
68 uint32_t vclk;
69 uint32_t dclk;
73 uint32_t evclk;
74 uint32_t ecclk;
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h116 uint32_t per_pixel_alpha : 1;
118 uint32_t argb8888 : 1;
119 uint32_t nv12 : 1;
120 uint32_t fp16 : 1;
121 uint32_t p010 : 1;
122 uint32_t ayuv : 1;
128 uint32_t argb8888;
129 uint32_t nv12;
130 uint32_t fp16;
136 uint32_t argb8888;
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/linux/drivers/scsi/qla2xxx/
H A Dqla_nx2.h239 uint32_t test_mask;
240 uint32_t test_value;
245 uint32_t test_mask;
246 uint32_t xor_value;
247 uint32_t or_value;
256 uint32_t arg1;
257 uint32_t arg2;
262 uint32_t dr_addr;
263 uint32_t dr_value;
264 uint32_t ar_addr;
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/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h254 uint32_t pause;
259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
275 uint32_t knee_threshold;
279 uint32_t current_gain;
297 uint32_t low_part; /**< Lower 32 bits */
298 uint32_t high_part; /**< Upper 32 bits */
311 uint32_t dram_clk_change_blackout_ns;
312 uint32_t dram_clk_change_read_only_ns;
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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h36 uint32_t percentage; /*> In unit of 0.01% or 0.001%*/
37 uint32_t percentage_divider; /*> 100 or 1000 */
38 uint32_t freq_range_khz;
39 uint32_t modulation_freq_hz;
45 uint32_t feedback_amount;
46 uint32_t nfrac_amount;
47 uint32_t ds_frac_size;
48 uint32_t ds_frac_amount;
57 uint32_t ENABLE_SS:1;
58 uint32_t DISPLAY_BLANKED:1;
[all …]

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