1*77adf3f0SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
27ec0effdSAtul Deshmukh /*
37ec0effdSAtul Deshmukh * QLogic Fibre Channel HBA Driver
4bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation
57ec0effdSAtul Deshmukh */
67ec0effdSAtul Deshmukh
77ec0effdSAtul Deshmukh #ifndef __QLA_NX2_H
87ec0effdSAtul Deshmukh #define __QLA_NX2_H
97ec0effdSAtul Deshmukh
107ec0effdSAtul Deshmukh #define QSNT_ACK_TOV 30
117ec0effdSAtul Deshmukh #define INTENT_TO_RECOVER 0x01
127ec0effdSAtul Deshmukh #define PROCEED_TO_RECOVER 0x02
137ec0effdSAtul Deshmukh #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
147ec0effdSAtul Deshmukh #define IDC_LOCK_RECOVERY_STATE_MASK 0x3
157ec0effdSAtul Deshmukh #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
167ec0effdSAtul Deshmukh
177ec0effdSAtul Deshmukh #define QLA8044_DRV_LOCK_MSLEEP 200
187ec0effdSAtul Deshmukh #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
197ec0effdSAtul Deshmukh #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
207ec0effdSAtul Deshmukh
217ec0effdSAtul Deshmukh #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
227ec0effdSAtul Deshmukh #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
237ec0effdSAtul Deshmukh #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
247ec0effdSAtul Deshmukh #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
257ec0effdSAtul Deshmukh
267ec0effdSAtul Deshmukh /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
277ec0effdSAtul Deshmukh #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
287ec0effdSAtul Deshmukh #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
297ec0effdSAtul Deshmukh MIU_TA_CTL_START)
307ec0effdSAtul Deshmukh #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
317ec0effdSAtul Deshmukh
327ec0effdSAtul Deshmukh /* Imbus address bit used to indicate a host address. This bit is
337ec0effdSAtul Deshmukh * eliminated by the pcie bar and bar select before presentation
347ec0effdSAtul Deshmukh * over pcie. */
357ec0effdSAtul Deshmukh /* host memory via IMBUS */
367ec0effdSAtul Deshmukh #define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
377ec0effdSAtul Deshmukh #define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
387ec0effdSAtul Deshmukh #define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
397ec0effdSAtul Deshmukh #define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
407ec0effdSAtul Deshmukh #define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
417ec0effdSAtul Deshmukh #define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
427ec0effdSAtul Deshmukh #define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
437ec0effdSAtul Deshmukh #define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
447ec0effdSAtul Deshmukh #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
457ec0effdSAtul Deshmukh #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
467ec0effdSAtul Deshmukh #define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
477ec0effdSAtul Deshmukh #define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
487ec0effdSAtul Deshmukh #define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
497ec0effdSAtul Deshmukh #define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
507ec0effdSAtul Deshmukh #define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
517ec0effdSAtul Deshmukh #define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
527ec0effdSAtul Deshmukh #define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
537ec0effdSAtul Deshmukh #define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
547ec0effdSAtul Deshmukh
557ec0effdSAtul Deshmukh /* PCI Windowing for DDR regions. */
addr_in_range(u64 addr,u64 low,u64 high)56df3f4cd0SBart Van Assche static inline bool addr_in_range(u64 addr, u64 low, u64 high)
57df3f4cd0SBart Van Assche {
58df3f4cd0SBart Van Assche return addr <= high && addr >= low;
59df3f4cd0SBart Van Assche }
607ec0effdSAtul Deshmukh
617ec0effdSAtul Deshmukh /* Indirectly Mapped Registers */
627ec0effdSAtul Deshmukh #define QLA8044_FLASH_SPI_STATUS 0x2808E010
637ec0effdSAtul Deshmukh #define QLA8044_FLASH_SPI_CONTROL 0x2808E014
647ec0effdSAtul Deshmukh #define QLA8044_FLASH_STATUS 0x42100004
657ec0effdSAtul Deshmukh #define QLA8044_FLASH_CONTROL 0x42110004
667ec0effdSAtul Deshmukh #define QLA8044_FLASH_ADDR 0x42110008
677ec0effdSAtul Deshmukh #define QLA8044_FLASH_WRDATA 0x4211000C
687ec0effdSAtul Deshmukh #define QLA8044_FLASH_RDDATA 0x42110018
697ec0effdSAtul Deshmukh #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
707ec0effdSAtul Deshmukh #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
717ec0effdSAtul Deshmukh
727ec0effdSAtul Deshmukh /* Flash access regs */
737ec0effdSAtul Deshmukh #define QLA8044_FLASH_LOCK 0x3850
747ec0effdSAtul Deshmukh #define QLA8044_FLASH_UNLOCK 0x3854
757ec0effdSAtul Deshmukh #define QLA8044_FLASH_LOCK_ID 0x3500
767ec0effdSAtul Deshmukh
777ec0effdSAtul Deshmukh /* Driver Lock regs */
787ec0effdSAtul Deshmukh #define QLA8044_DRV_LOCK 0x3868
797ec0effdSAtul Deshmukh #define QLA8044_DRV_UNLOCK 0x386C
807ec0effdSAtul Deshmukh #define QLA8044_DRV_LOCK_ID 0x3504
817ec0effdSAtul Deshmukh #define QLA8044_DRV_LOCKRECOVERY 0x379C
827ec0effdSAtul Deshmukh
837ec0effdSAtul Deshmukh /* IDC version */
847ec0effdSAtul Deshmukh #define QLA8044_IDC_VER_MAJ_VALUE 0x1
857ec0effdSAtul Deshmukh #define QLA8044_IDC_VER_MIN_VALUE 0x0
867ec0effdSAtul Deshmukh
877ec0effdSAtul Deshmukh /* IDC Registers : Driver Coexistence Defines */
887ec0effdSAtul Deshmukh #define QLA8044_CRB_IDC_VER_MAJOR 0x3780
897ec0effdSAtul Deshmukh #define QLA8044_CRB_IDC_VER_MINOR 0x3798
907ec0effdSAtul Deshmukh #define QLA8044_IDC_DRV_AUDIT 0x3794
917ec0effdSAtul Deshmukh #define QLA8044_SRE_SHIM_CONTROL 0x0D200284
927ec0effdSAtul Deshmukh #define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
937ec0effdSAtul Deshmukh #define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
947ec0effdSAtul Deshmukh #define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
957ec0effdSAtul Deshmukh #define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
967ec0effdSAtul Deshmukh #define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
977ec0effdSAtul Deshmukh #define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
987ec0effdSAtul Deshmukh #define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
997ec0effdSAtul Deshmukh #define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
1007ec0effdSAtul Deshmukh
1017ec0effdSAtul Deshmukh /* set value to pause threshold value */
1027ec0effdSAtul Deshmukh #define QLA8044_SET_PAUSE_VAL 0x0
1037ec0effdSAtul Deshmukh #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
1047ec0effdSAtul Deshmukh #define QLA8044_PEG_HALT_STATUS1 0x34A8
1057ec0effdSAtul Deshmukh #define QLA8044_PEG_HALT_STATUS2 0x34AC
1067ec0effdSAtul Deshmukh #define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
1077ec0effdSAtul Deshmukh #define QLA8044_FW_CAPABILITIES 0x3528
1087ec0effdSAtul Deshmukh #define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
1097ec0effdSAtul Deshmukh #define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
1107ec0effdSAtul Deshmukh #define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
1117ec0effdSAtul Deshmukh #define QLA8044_CRB_DRV_SCRATCH 0x3548
1127ec0effdSAtul Deshmukh #define QLA8044_CRB_DEV_PART_INFO1 0x37E0
1137ec0effdSAtul Deshmukh #define QLA8044_CRB_DEV_PART_INFO2 0x37E4
1147ec0effdSAtul Deshmukh #define QLA8044_FW_VER_MAJOR 0x3550
1157ec0effdSAtul Deshmukh #define QLA8044_FW_VER_MINOR 0x3554
1167ec0effdSAtul Deshmukh #define QLA8044_FW_VER_SUB 0x3558
1177ec0effdSAtul Deshmukh #define QLA8044_NPAR_STATE 0x359C
1187ec0effdSAtul Deshmukh #define QLA8044_FW_IMAGE_VALID 0x35FC
1197ec0effdSAtul Deshmukh #define QLA8044_CMDPEG_STATE 0x3650
1207ec0effdSAtul Deshmukh #define QLA8044_ASIC_TEMP 0x37B4
1217ec0effdSAtul Deshmukh #define QLA8044_FW_API 0x356C
1227ec0effdSAtul Deshmukh #define QLA8044_DRV_OP_MODE 0x3570
1237ec0effdSAtul Deshmukh #define QLA8044_CRB_WIN_BASE 0x3800
1247ec0effdSAtul Deshmukh #define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
1257ec0effdSAtul Deshmukh #define QLA8044_SEM_LOCK_BASE 0x3840
1267ec0effdSAtul Deshmukh #define QLA8044_SEM_UNLOCK_BASE 0x3844
1277ec0effdSAtul Deshmukh #define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
1287ec0effdSAtul Deshmukh #define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
1297ec0effdSAtul Deshmukh #define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
1307ec0effdSAtul Deshmukh #define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
1317ec0effdSAtul Deshmukh #define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
1327ec0effdSAtul Deshmukh #define QLA8044_LINK_SPEED_FACTOR 10
133a018d8ffSHiral Patel #define QLA8044_FUN7_ACTIVE_INDEX 0x80
1347ec0effdSAtul Deshmukh
1357ec0effdSAtul Deshmukh /* FLASH API Defines */
1367ec0effdSAtul Deshmukh #define QLA8044_FLASH_MAX_WAIT_USEC 100
1377ec0effdSAtul Deshmukh #define QLA8044_FLASH_LOCK_TIMEOUT 10000
1387ec0effdSAtul Deshmukh #define QLA8044_FLASH_SECTOR_SIZE 65536
1397ec0effdSAtul Deshmukh #define QLA8044_DRV_LOCK_TIMEOUT 2000
1407ec0effdSAtul Deshmukh #define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
1417ec0effdSAtul Deshmukh #define QLA8044_FLASH_WRITE_CMD 0xdacdacda
1427ec0effdSAtul Deshmukh #define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
1437ec0effdSAtul Deshmukh #define QLA8044_FLASH_READ_RETRY_COUNT 2000
1447ec0effdSAtul Deshmukh #define QLA8044_FLASH_STATUS_READY 0x6
1457ec0effdSAtul Deshmukh #define QLA8044_FLASH_BUFFER_WRITE_MIN 2
1467ec0effdSAtul Deshmukh #define QLA8044_FLASH_BUFFER_WRITE_MAX 64
1477ec0effdSAtul Deshmukh #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
1487ec0effdSAtul Deshmukh #define QLA8044_ERASE_MODE 1
1497ec0effdSAtul Deshmukh #define QLA8044_WRITE_MODE 2
1507ec0effdSAtul Deshmukh #define QLA8044_DWORD_WRITE_MODE 3
1517ec0effdSAtul Deshmukh #define QLA8044_GLOBAL_RESET 0x38CC
1527ec0effdSAtul Deshmukh #define QLA8044_WILDCARD 0x38F0
1537ec0effdSAtul Deshmukh #define QLA8044_INFORMANT 0x38FC
1547ec0effdSAtul Deshmukh #define QLA8044_HOST_MBX_CTRL 0x3038
1557ec0effdSAtul Deshmukh #define QLA8044_FW_MBX_CTRL 0x303C
1567ec0effdSAtul Deshmukh #define QLA8044_BOOTLOADER_ADDR 0x355C
1577ec0effdSAtul Deshmukh #define QLA8044_BOOTLOADER_SIZE 0x3560
1587ec0effdSAtul Deshmukh #define QLA8044_FW_IMAGE_ADDR 0x3564
1597ec0effdSAtul Deshmukh #define QLA8044_MBX_INTR_ENABLE 0x1000
1607ec0effdSAtul Deshmukh #define QLA8044_MBX_INTR_MASK 0x1200
1617ec0effdSAtul Deshmukh
1627ec0effdSAtul Deshmukh /* IDC Control Register bit defines */
1637ec0effdSAtul Deshmukh #define DONTRESET_BIT0 0x1
1647ec0effdSAtul Deshmukh #define GRACEFUL_RESET_BIT1 0x2
1657ec0effdSAtul Deshmukh
1667ec0effdSAtul Deshmukh /* ISP8044 PEG_HALT_STATUS1 bits */
1677ec0effdSAtul Deshmukh #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
1687ec0effdSAtul Deshmukh #define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
1697ec0effdSAtul Deshmukh #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
1707ec0effdSAtul Deshmukh
1717ec0effdSAtul Deshmukh /* Firmware image definitions */
1727ec0effdSAtul Deshmukh #define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
1737ec0effdSAtul Deshmukh #define QLA8044_BOOT_FROM_FLASH 0
1747ec0effdSAtul Deshmukh #define QLA8044_IDC_PARAM_ADDR 0x3e8020
1757ec0effdSAtul Deshmukh
1767ec0effdSAtul Deshmukh /* FLASH related definitions */
1777ec0effdSAtul Deshmukh #define QLA8044_OPTROM_BURST_SIZE 0x100
1787ec0effdSAtul Deshmukh #define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
1797ec0effdSAtul Deshmukh #define QLA8044_MIN_OPTROM_BURST_DWORDS 2
1807ec0effdSAtul Deshmukh #define QLA8044_SECTOR_SIZE (64 * 1024)
1817ec0effdSAtul Deshmukh
1827ec0effdSAtul Deshmukh #define QLA8044_FLASH_SPI_CTL 0x4
1837ec0effdSAtul Deshmukh #define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
1847ec0effdSAtul Deshmukh #define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
1857ec0effdSAtul Deshmukh #define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
1867ec0effdSAtul Deshmukh #define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
1877ec0effdSAtul Deshmukh #define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
1887ec0effdSAtul Deshmukh #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
1897ec0effdSAtul Deshmukh #define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
1907ec0effdSAtul Deshmukh #define QLA8044_FLASH_ERASE_SIG 0xFD0300
1917ec0effdSAtul Deshmukh #define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
1927ec0effdSAtul Deshmukh
1937ec0effdSAtul Deshmukh /* Reset template definitions */
1947ec0effdSAtul Deshmukh #define QLA8044_MAX_RESET_SEQ_ENTRIES 16
1957ec0effdSAtul Deshmukh #define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
1967ec0effdSAtul Deshmukh #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
1977ec0effdSAtul Deshmukh #define QLA8044_RESET_SEQ_VERSION 0x0101
1987ec0effdSAtul Deshmukh
1997ec0effdSAtul Deshmukh /* Reset template entry opcodes */
2007ec0effdSAtul Deshmukh #define OPCODE_NOP 0x0000
2017ec0effdSAtul Deshmukh #define OPCODE_WRITE_LIST 0x0001
2027ec0effdSAtul Deshmukh #define OPCODE_READ_WRITE_LIST 0x0002
2037ec0effdSAtul Deshmukh #define OPCODE_POLL_LIST 0x0004
2047ec0effdSAtul Deshmukh #define OPCODE_POLL_WRITE_LIST 0x0008
2057ec0effdSAtul Deshmukh #define OPCODE_READ_MODIFY_WRITE 0x0010
2067ec0effdSAtul Deshmukh #define OPCODE_SEQ_PAUSE 0x0020
2077ec0effdSAtul Deshmukh #define OPCODE_SEQ_END 0x0040
2087ec0effdSAtul Deshmukh #define OPCODE_TMPL_END 0x0080
2097ec0effdSAtul Deshmukh #define OPCODE_POLL_READ_LIST 0x0100
2107ec0effdSAtul Deshmukh
2117ec0effdSAtul Deshmukh /* Template Header */
2127ec0effdSAtul Deshmukh #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
2137ec0effdSAtul Deshmukh #define QLA8044_IDC_DRV_CTRL 0x3790
2147ec0effdSAtul Deshmukh #define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
2157ec0effdSAtul Deshmukh
2167ec0effdSAtul Deshmukh #define MINIDUMP_SIZE_36K 36864
2177ec0effdSAtul Deshmukh
2187ec0effdSAtul Deshmukh struct qla8044_reset_template_hdr {
2197ec0effdSAtul Deshmukh uint16_t version;
2207ec0effdSAtul Deshmukh uint16_t signature;
2217ec0effdSAtul Deshmukh uint16_t size;
2227ec0effdSAtul Deshmukh uint16_t entries;
2237ec0effdSAtul Deshmukh uint16_t hdr_size;
2247ec0effdSAtul Deshmukh uint16_t checksum;
2257ec0effdSAtul Deshmukh uint16_t init_seq_offset;
2267ec0effdSAtul Deshmukh uint16_t start_seq_offset;
2277ec0effdSAtul Deshmukh } __packed;
2287ec0effdSAtul Deshmukh
2297ec0effdSAtul Deshmukh /* Common Entry Header. */
2307ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr {
2317ec0effdSAtul Deshmukh uint16_t cmd;
2327ec0effdSAtul Deshmukh uint16_t size;
2337ec0effdSAtul Deshmukh uint16_t count;
2347ec0effdSAtul Deshmukh uint16_t delay;
2357ec0effdSAtul Deshmukh } __packed;
2367ec0effdSAtul Deshmukh
2377ec0effdSAtul Deshmukh /* Generic poll entry type. */
2387ec0effdSAtul Deshmukh struct qla8044_poll {
2397ec0effdSAtul Deshmukh uint32_t test_mask;
2407ec0effdSAtul Deshmukh uint32_t test_value;
2417ec0effdSAtul Deshmukh } __packed;
2427ec0effdSAtul Deshmukh
2437ec0effdSAtul Deshmukh /* Read modify write entry type. */
2447ec0effdSAtul Deshmukh struct qla8044_rmw {
2457ec0effdSAtul Deshmukh uint32_t test_mask;
2467ec0effdSAtul Deshmukh uint32_t xor_value;
2477ec0effdSAtul Deshmukh uint32_t or_value;
2487ec0effdSAtul Deshmukh uint8_t shl;
2497ec0effdSAtul Deshmukh uint8_t shr;
2507ec0effdSAtul Deshmukh uint8_t index_a;
2517ec0effdSAtul Deshmukh uint8_t rsvd;
2527ec0effdSAtul Deshmukh } __packed;
2537ec0effdSAtul Deshmukh
2547ec0effdSAtul Deshmukh /* Generic Entry Item with 2 DWords. */
2557ec0effdSAtul Deshmukh struct qla8044_entry {
2567ec0effdSAtul Deshmukh uint32_t arg1;
2577ec0effdSAtul Deshmukh uint32_t arg2;
2587ec0effdSAtul Deshmukh } __packed;
2597ec0effdSAtul Deshmukh
2607ec0effdSAtul Deshmukh /* Generic Entry Item with 4 DWords.*/
2617ec0effdSAtul Deshmukh struct qla8044_quad_entry {
2627ec0effdSAtul Deshmukh uint32_t dr_addr;
2637ec0effdSAtul Deshmukh uint32_t dr_value;
2647ec0effdSAtul Deshmukh uint32_t ar_addr;
2657ec0effdSAtul Deshmukh uint32_t ar_value;
2667ec0effdSAtul Deshmukh } __packed;
2677ec0effdSAtul Deshmukh
2687ec0effdSAtul Deshmukh struct qla8044_reset_template {
2697ec0effdSAtul Deshmukh int seq_index;
2707ec0effdSAtul Deshmukh int seq_error;
2717ec0effdSAtul Deshmukh int array_index;
2727ec0effdSAtul Deshmukh uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
2737ec0effdSAtul Deshmukh uint8_t *buff;
2747ec0effdSAtul Deshmukh uint8_t *stop_offset;
2757ec0effdSAtul Deshmukh uint8_t *start_offset;
2767ec0effdSAtul Deshmukh uint8_t *init_offset;
2777ec0effdSAtul Deshmukh struct qla8044_reset_template_hdr *hdr;
2787ec0effdSAtul Deshmukh uint8_t seq_end;
2797ec0effdSAtul Deshmukh uint8_t template_end;
2807ec0effdSAtul Deshmukh };
2817ec0effdSAtul Deshmukh
2827ec0effdSAtul Deshmukh /* Driver_code is for driver to write some info about the entry
2837ec0effdSAtul Deshmukh * currently not used.
2847ec0effdSAtul Deshmukh */
2857ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr {
2867ec0effdSAtul Deshmukh uint32_t entry_type;
2877ec0effdSAtul Deshmukh uint32_t entry_size;
2887ec0effdSAtul Deshmukh uint32_t entry_capture_size;
2897ec0effdSAtul Deshmukh struct {
2907ec0effdSAtul Deshmukh uint8_t entry_capture_mask;
2917ec0effdSAtul Deshmukh uint8_t entry_code;
2927ec0effdSAtul Deshmukh uint8_t driver_code;
2937ec0effdSAtul Deshmukh uint8_t driver_flags;
2947ec0effdSAtul Deshmukh } d_ctrl;
2957ec0effdSAtul Deshmukh } __packed;
2967ec0effdSAtul Deshmukh
2977ec0effdSAtul Deshmukh /* Read CRB entry header */
2987ec0effdSAtul Deshmukh struct qla8044_minidump_entry_crb {
2997ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3007ec0effdSAtul Deshmukh uint32_t addr;
3017ec0effdSAtul Deshmukh struct {
3027ec0effdSAtul Deshmukh uint8_t addr_stride;
3037ec0effdSAtul Deshmukh uint8_t state_index_a;
3047ec0effdSAtul Deshmukh uint16_t poll_timeout;
3057ec0effdSAtul Deshmukh } crb_strd;
3067ec0effdSAtul Deshmukh uint32_t data_size;
3077ec0effdSAtul Deshmukh uint32_t op_count;
3087ec0effdSAtul Deshmukh
3097ec0effdSAtul Deshmukh struct {
3107ec0effdSAtul Deshmukh uint8_t opcode;
3117ec0effdSAtul Deshmukh uint8_t state_index_v;
3127ec0effdSAtul Deshmukh uint8_t shl;
3137ec0effdSAtul Deshmukh uint8_t shr;
3147ec0effdSAtul Deshmukh } crb_ctrl;
3157ec0effdSAtul Deshmukh
3167ec0effdSAtul Deshmukh uint32_t value_1;
3177ec0effdSAtul Deshmukh uint32_t value_2;
3187ec0effdSAtul Deshmukh uint32_t value_3;
3197ec0effdSAtul Deshmukh } __packed;
3207ec0effdSAtul Deshmukh
3217ec0effdSAtul Deshmukh struct qla8044_minidump_entry_cache {
3227ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3237ec0effdSAtul Deshmukh uint32_t tag_reg_addr;
3247ec0effdSAtul Deshmukh struct {
3257ec0effdSAtul Deshmukh uint16_t tag_value_stride;
3267ec0effdSAtul Deshmukh uint16_t init_tag_value;
3277ec0effdSAtul Deshmukh } addr_ctrl;
3287ec0effdSAtul Deshmukh uint32_t data_size;
3297ec0effdSAtul Deshmukh uint32_t op_count;
3307ec0effdSAtul Deshmukh uint32_t control_addr;
3317ec0effdSAtul Deshmukh struct {
3327ec0effdSAtul Deshmukh uint16_t write_value;
3337ec0effdSAtul Deshmukh uint8_t poll_mask;
3347ec0effdSAtul Deshmukh uint8_t poll_wait;
3357ec0effdSAtul Deshmukh } cache_ctrl;
3367ec0effdSAtul Deshmukh uint32_t read_addr;
3377ec0effdSAtul Deshmukh struct {
3387ec0effdSAtul Deshmukh uint8_t read_addr_stride;
3397ec0effdSAtul Deshmukh uint8_t read_addr_cnt;
3407ec0effdSAtul Deshmukh uint16_t rsvd_1;
3417ec0effdSAtul Deshmukh } read_ctrl;
3427ec0effdSAtul Deshmukh } __packed;
3437ec0effdSAtul Deshmukh
3447ec0effdSAtul Deshmukh /* Read OCM */
3457ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdocm {
3467ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3477ec0effdSAtul Deshmukh uint32_t rsvd_0;
3487ec0effdSAtul Deshmukh uint32_t rsvd_1;
3497ec0effdSAtul Deshmukh uint32_t data_size;
3507ec0effdSAtul Deshmukh uint32_t op_count;
3517ec0effdSAtul Deshmukh uint32_t rsvd_2;
3527ec0effdSAtul Deshmukh uint32_t rsvd_3;
3537ec0effdSAtul Deshmukh uint32_t read_addr;
3547ec0effdSAtul Deshmukh uint32_t read_addr_stride;
3557ec0effdSAtul Deshmukh } __packed;
3567ec0effdSAtul Deshmukh
3577ec0effdSAtul Deshmukh /* Read Memory */
3587ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem {
3597ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3607ec0effdSAtul Deshmukh uint32_t rsvd[6];
3617ec0effdSAtul Deshmukh uint32_t read_addr;
3627ec0effdSAtul Deshmukh uint32_t read_data_size;
3637ec0effdSAtul Deshmukh };
3647ec0effdSAtul Deshmukh
3657ec0effdSAtul Deshmukh /* Read Memory: For Pex-DMA */
3667ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem_pex_dma {
3677ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3687ec0effdSAtul Deshmukh uint32_t desc_card_addr;
3697ec0effdSAtul Deshmukh uint16_t dma_desc_cmd;
3707ec0effdSAtul Deshmukh uint8_t rsvd[2];
3717ec0effdSAtul Deshmukh uint32_t start_dma_cmd;
3727ec0effdSAtul Deshmukh uint8_t rsvd2[12];
3737ec0effdSAtul Deshmukh uint32_t read_addr;
3747ec0effdSAtul Deshmukh uint32_t read_data_size;
3757ec0effdSAtul Deshmukh } __packed;
3767ec0effdSAtul Deshmukh
3777ec0effdSAtul Deshmukh /* Read ROM */
3787ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdrom {
3797ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3807ec0effdSAtul Deshmukh uint32_t rsvd[6];
3817ec0effdSAtul Deshmukh uint32_t read_addr;
3827ec0effdSAtul Deshmukh uint32_t read_data_size;
3837ec0effdSAtul Deshmukh } __packed;
3847ec0effdSAtul Deshmukh
3857ec0effdSAtul Deshmukh /* Mux entry */
3867ec0effdSAtul Deshmukh struct qla8044_minidump_entry_mux {
3877ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
3887ec0effdSAtul Deshmukh uint32_t select_addr;
3897ec0effdSAtul Deshmukh uint32_t rsvd_0;
3907ec0effdSAtul Deshmukh uint32_t data_size;
3917ec0effdSAtul Deshmukh uint32_t op_count;
3927ec0effdSAtul Deshmukh uint32_t select_value;
3937ec0effdSAtul Deshmukh uint32_t select_value_stride;
3947ec0effdSAtul Deshmukh uint32_t read_addr;
3957ec0effdSAtul Deshmukh uint32_t rsvd_1;
3967ec0effdSAtul Deshmukh } __packed;
3977ec0effdSAtul Deshmukh
3987ec0effdSAtul Deshmukh /* Queue entry */
3997ec0effdSAtul Deshmukh struct qla8044_minidump_entry_queue {
4007ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
4017ec0effdSAtul Deshmukh uint32_t select_addr;
4027ec0effdSAtul Deshmukh struct {
4037ec0effdSAtul Deshmukh uint16_t queue_id_stride;
4047ec0effdSAtul Deshmukh uint16_t rsvd_0;
4057ec0effdSAtul Deshmukh } q_strd;
4067ec0effdSAtul Deshmukh uint32_t data_size;
4077ec0effdSAtul Deshmukh uint32_t op_count;
4087ec0effdSAtul Deshmukh uint32_t rsvd_1;
4097ec0effdSAtul Deshmukh uint32_t rsvd_2;
4107ec0effdSAtul Deshmukh uint32_t read_addr;
4117ec0effdSAtul Deshmukh struct {
4127ec0effdSAtul Deshmukh uint8_t read_addr_stride;
4137ec0effdSAtul Deshmukh uint8_t read_addr_cnt;
4147ec0effdSAtul Deshmukh uint16_t rsvd_3;
4157ec0effdSAtul Deshmukh } rd_strd;
4167ec0effdSAtul Deshmukh } __packed;
4177ec0effdSAtul Deshmukh
4187ec0effdSAtul Deshmukh /* POLLRD Entry */
4197ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrd {
4207ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
4217ec0effdSAtul Deshmukh uint32_t select_addr;
4227ec0effdSAtul Deshmukh uint32_t read_addr;
4237ec0effdSAtul Deshmukh uint32_t select_value;
4247ec0effdSAtul Deshmukh uint16_t select_value_stride;
4257ec0effdSAtul Deshmukh uint16_t op_count;
4267ec0effdSAtul Deshmukh uint32_t poll_wait;
4277ec0effdSAtul Deshmukh uint32_t poll_mask;
4287ec0effdSAtul Deshmukh uint32_t data_size;
4297ec0effdSAtul Deshmukh uint32_t rsvd_1;
4307ec0effdSAtul Deshmukh } __packed;
4317ec0effdSAtul Deshmukh
432804df800SPratik Mohanty struct qla8044_minidump_entry_rddfe {
433804df800SPratik Mohanty struct qla8044_minidump_entry_hdr h;
434804df800SPratik Mohanty uint32_t addr_1;
435804df800SPratik Mohanty uint32_t value;
436804df800SPratik Mohanty uint8_t stride;
437804df800SPratik Mohanty uint8_t stride2;
438804df800SPratik Mohanty uint16_t count;
439804df800SPratik Mohanty uint32_t poll;
440804df800SPratik Mohanty uint32_t mask;
441804df800SPratik Mohanty uint32_t modify_mask;
442804df800SPratik Mohanty uint32_t data_size;
443804df800SPratik Mohanty uint32_t rsvd;
444804df800SPratik Mohanty
445804df800SPratik Mohanty } __packed;
446804df800SPratik Mohanty
447804df800SPratik Mohanty struct qla8044_minidump_entry_rdmdio {
448804df800SPratik Mohanty struct qla8044_minidump_entry_hdr h;
449804df800SPratik Mohanty
450804df800SPratik Mohanty uint32_t addr_1;
451804df800SPratik Mohanty uint32_t addr_2;
452804df800SPratik Mohanty uint32_t value_1;
453804df800SPratik Mohanty uint8_t stride_1;
454804df800SPratik Mohanty uint8_t stride_2;
455804df800SPratik Mohanty uint16_t count;
456804df800SPratik Mohanty uint32_t poll;
457804df800SPratik Mohanty uint32_t mask;
458804df800SPratik Mohanty uint32_t value_2;
459804df800SPratik Mohanty uint32_t data_size;
460804df800SPratik Mohanty
461804df800SPratik Mohanty } __packed;
462804df800SPratik Mohanty
463804df800SPratik Mohanty struct qla8044_minidump_entry_pollwr {
464804df800SPratik Mohanty struct qla8044_minidump_entry_hdr h;
465804df800SPratik Mohanty uint32_t addr_1;
466804df800SPratik Mohanty uint32_t addr_2;
467804df800SPratik Mohanty uint32_t value_1;
468804df800SPratik Mohanty uint32_t value_2;
469804df800SPratik Mohanty uint32_t poll;
470804df800SPratik Mohanty uint32_t mask;
471804df800SPratik Mohanty uint32_t data_size;
472804df800SPratik Mohanty uint32_t rsvd;
473804df800SPratik Mohanty
474804df800SPratik Mohanty } __packed;
475804df800SPratik Mohanty
4767ec0effdSAtul Deshmukh /* RDMUX2 Entry */
4777ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmux2 {
4787ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
4797ec0effdSAtul Deshmukh uint32_t select_addr_1;
4807ec0effdSAtul Deshmukh uint32_t select_addr_2;
4817ec0effdSAtul Deshmukh uint32_t select_value_1;
4827ec0effdSAtul Deshmukh uint32_t select_value_2;
4837ec0effdSAtul Deshmukh uint32_t op_count;
4847ec0effdSAtul Deshmukh uint32_t select_value_mask;
4857ec0effdSAtul Deshmukh uint32_t read_addr;
4867ec0effdSAtul Deshmukh uint8_t select_value_stride;
4877ec0effdSAtul Deshmukh uint8_t data_size;
4887ec0effdSAtul Deshmukh uint8_t rsvd[2];
4897ec0effdSAtul Deshmukh } __packed;
4907ec0effdSAtul Deshmukh
4917ec0effdSAtul Deshmukh /* POLLRDMWR Entry */
4927ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrdmwr {
4937ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr h;
4947ec0effdSAtul Deshmukh uint32_t addr_1;
4957ec0effdSAtul Deshmukh uint32_t addr_2;
4967ec0effdSAtul Deshmukh uint32_t value_1;
4977ec0effdSAtul Deshmukh uint32_t value_2;
4987ec0effdSAtul Deshmukh uint32_t poll_wait;
4997ec0effdSAtul Deshmukh uint32_t poll_mask;
5007ec0effdSAtul Deshmukh uint32_t modify_mask;
5017ec0effdSAtul Deshmukh uint32_t data_size;
5027ec0effdSAtul Deshmukh } __packed;
5037ec0effdSAtul Deshmukh
5047ec0effdSAtul Deshmukh /* IDC additional information */
5057ec0effdSAtul Deshmukh struct qla8044_idc_information {
5067ec0effdSAtul Deshmukh uint32_t request_desc; /* IDC request descriptor */
5077ec0effdSAtul Deshmukh uint32_t info1; /* IDC additional info */
5087ec0effdSAtul Deshmukh uint32_t info2; /* IDC additional info */
5097ec0effdSAtul Deshmukh uint32_t info3; /* IDC additional info */
5107ec0effdSAtul Deshmukh } __packed;
5117ec0effdSAtul Deshmukh
5127ec0effdSAtul Deshmukh enum qla_regs {
5137ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS1_INDEX = 0,
5147ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS2_INDEX,
5157ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX,
5167ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX,
5177ec0effdSAtul Deshmukh QLA8044_CRB_DEV_STATE_INDEX,
5187ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX,
5197ec0effdSAtul Deshmukh QLA8044_CRB_DRV_SCRATCH_INDEX,
5207ec0effdSAtul Deshmukh QLA8044_CRB_DEV_PART_INFO_INDEX,
5217ec0effdSAtul Deshmukh QLA8044_CRB_DRV_IDC_VERSION_INDEX,
5227ec0effdSAtul Deshmukh QLA8044_FW_VERSION_MAJOR_INDEX,
5237ec0effdSAtul Deshmukh QLA8044_FW_VERSION_MINOR_INDEX,
5247ec0effdSAtul Deshmukh QLA8044_FW_VERSION_SUB_INDEX,
5257ec0effdSAtul Deshmukh QLA8044_CRB_CMDPEG_STATE_INDEX,
5267ec0effdSAtul Deshmukh QLA8044_CRB_TEMP_STATE_INDEX,
5277ec0effdSAtul Deshmukh } __packed;
5287ec0effdSAtul Deshmukh
5297ec0effdSAtul Deshmukh #define CRB_REG_INDEX_MAX 14
5307ec0effdSAtul Deshmukh #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
5317ec0effdSAtul Deshmukh #define CRB_CMDPEG_CHECK_DELAY 500
5327ec0effdSAtul Deshmukh
5337ec0effdSAtul Deshmukh /* MiniDump Structures */
5347ec0effdSAtul Deshmukh
5357ec0effdSAtul Deshmukh /* Driver_code is for driver to write some info about the entry
5367ec0effdSAtul Deshmukh * currently not used.
5377ec0effdSAtul Deshmukh */
5387ec0effdSAtul Deshmukh #define QLA8044_SS_OCM_WNDREG_INDEX 3
5397ec0effdSAtul Deshmukh #define QLA8044_DBG_STATE_ARRAY_LEN 16
5407ec0effdSAtul Deshmukh #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
5417ec0effdSAtul Deshmukh #define QLA8044_DBG_RSVD_ARRAY_LEN 8
5427ec0effdSAtul Deshmukh #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
5437ec0effdSAtul Deshmukh #define QLA8044_SS_PCI_INDEX 0
544804df800SPratik Mohanty #define QLA8044_RDDFE 38
545804df800SPratik Mohanty #define QLA8044_RDMDIO 39
546804df800SPratik Mohanty #define QLA8044_POLLWR 40
5477ec0effdSAtul Deshmukh
5487ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr {
5497ec0effdSAtul Deshmukh uint32_t entry_type;
5507ec0effdSAtul Deshmukh uint32_t first_entry_offset;
5517ec0effdSAtul Deshmukh uint32_t size_of_template;
5527ec0effdSAtul Deshmukh uint32_t capture_debug_level;
5537ec0effdSAtul Deshmukh uint32_t num_of_entries;
5547ec0effdSAtul Deshmukh uint32_t version;
5557ec0effdSAtul Deshmukh uint32_t driver_timestamp;
5567ec0effdSAtul Deshmukh uint32_t checksum;
5577ec0effdSAtul Deshmukh
5587ec0effdSAtul Deshmukh uint32_t driver_capture_mask;
5597ec0effdSAtul Deshmukh uint32_t driver_info_word2;
5607ec0effdSAtul Deshmukh uint32_t driver_info_word3;
5617ec0effdSAtul Deshmukh uint32_t driver_info_word4;
5627ec0effdSAtul Deshmukh
5637ec0effdSAtul Deshmukh uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
5647ec0effdSAtul Deshmukh uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
5657ec0effdSAtul Deshmukh uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
5667ec0effdSAtul Deshmukh };
5677ec0effdSAtul Deshmukh
5687ec0effdSAtul Deshmukh struct qla8044_pex_dma_descriptor {
5697ec0effdSAtul Deshmukh struct {
5707ec0effdSAtul Deshmukh uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
5717ec0effdSAtul Deshmukh uint8_t rsvd[2];
5727ec0effdSAtul Deshmukh uint16_t dma_desc_cmd;
5737ec0effdSAtul Deshmukh } cmd;
5747ec0effdSAtul Deshmukh uint64_t src_addr;
5757ec0effdSAtul Deshmukh uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
5767ec0effdSAtul Deshmukh uint8_t rsvd[24];
5777ec0effdSAtul Deshmukh } __packed;
5787ec0effdSAtul Deshmukh
5797ec0effdSAtul Deshmukh #endif
580