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Searched refs:ucode (Results 1 – 25 of 70) sorted by relevance

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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Ducode_loader.c40 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode) in brcms_ucode_data_init() argument
47 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0bsinitvals24, in brcms_ucode_data_init()
50 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0initvals24, in brcms_ucode_data_init()
53 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1bsinitvals24, in brcms_ucode_data_init()
56 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1initvals24, in brcms_ucode_data_init()
59 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2bsinitvals24, in brcms_ucode_data_init()
62 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2initvals24, in brcms_ucode_data_init()
65 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0absinitvals16, in brcms_ucode_data_init()
68 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0bsinitvals16, in brcms_ucode_data_init()
71 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0initvals16, in brcms_ucode_data_init()
[all …]
H A Ducode_loader.h46 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48 void brcms_ucode_data_free(struct brcms_ucode *ucode);
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ucode.c826 struct amdgpu_firmware_info *ucode, in amdgpu_ucode_init_single_fw() argument
842 if (!ucode->fw) in amdgpu_ucode_init_single_fw()
845 ucode->mc_addr = mc_addr; in amdgpu_ucode_init_single_fw()
846 ucode->kaddr = kptr; in amdgpu_ucode_init_single_fw()
848 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) in amdgpu_ucode_init_single_fw()
851 header = (const struct common_firmware_header *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
852 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
853 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
854 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
855 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
[all …]
H A Damdgpu_mes.c672 int ucode, ucode_data; in amdgpu_mes_init_microcode() local
675 ucode = AMDGPU_UCODE_ID_CP_MES; in amdgpu_mes_init_microcode()
678 ucode = AMDGPU_UCODE_ID_CP_MES1; in amdgpu_mes_init_microcode()
682 info = &adev->firmware.ucode[ucode]; in amdgpu_mes_init_microcode()
683 info->ucode_id = ucode; in amdgpu_mes_init_microcode()
689 info = &adev->firmware.ucode[ucode_data]; in amdgpu_mes_init_microcode()
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_ucode.c68 if (eng_grp->ucode[1].type) in is_2nd_ucode_used()
74 static void set_ucode_filename(struct otx2_cpt_ucode *ucode, in set_ucode_filename() argument
77 strscpy(ucode->filename, filename, OTX2_CPT_NAME_LENGTH); in set_ucode_filename()
191 dma_addr = engs->ucode->dma; in cptx_set_ucode_base()
395 set_ucode_filename(&uc_info->ucode, filename); in load_fw()
396 memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str, in load_fw()
398 uc_info->ucode.ver_str[OTX2_CPT_UCODE_VER_STR_SZ] = 0; in load_fw()
399 uc_info->ucode.ver_num = ucode_hdr->ver_num; in load_fw()
400 uc_info->ucode.type = ucode_type; in load_fw()
401 uc_info->ucode.size = ucode_size; in load_fw()
[all …]
/linux/Documentation/gpu/nova/core/
H A Dfalcon.rst6 The following sections describe the Falcon core and the ucode running on it.
18 The code running on the Falcon cores is also called 'ucode', and will be
33 HS ucode is the most trusted code and has access to pretty much everything on
38 (Write Protect Region), has to be done by the HS ucode and cannot be done by the
39 host CPU or LS ucode.
43 These modes are less secure than HS. Like HS, the LS or NS ucode binary also
47 ucode in HS mode on the SEC2 Falcon, which then authenticates and runs the
60 After nova-core driver reads the necessary ucode from VBIOS, it programs the
61 BROM and DMA registers to trigger the Falcon to load the HS ucode from the system
62 memory into the Falcon's IMEM/DMEM. Once the HS ucode is loaded, it is verified
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H A Dfwsec.rst15 before loading various ucode images onto other microcontrollers on the GPU,
21 reset and loading them with other non-FWSEC ucode). The kernel driver only needs
26 data required for power management. Once setup, only HS mode ucode can access it
30 various ucode images (also known as applications) -- one of them being FWSEC. For how
33 The Falcon data for each ucode images (including the FWSEC image) is a combination
35 ucode images are stored in the same ROM partition and the PMU table is used to look
H A Dvbios.rst14 are the ones that contain Falcon ucode and what we are mainly looking for.
29 of different functions. The FWSEC ucode is run in heavy-secure mode and
34 loads (see devinit.rst). The DEVINIT ucode is itself another ucode that is
42 region is only accessible to heavy-secure ucode.
173 used to find the required Falcon ucode based on an application ID.
/linux/drivers/soc/fsl/qe/
H A Dqe.c406 const struct qe_microcode *ucode) in qe_upload_microcode() argument
408 const __be32 *code = base + be32_to_cpu(ucode->code_offset); in qe_upload_microcode()
411 if (ucode->major || ucode->minor || ucode->revision) in qe_upload_microcode()
414 ucode->id, ucode->major, ucode->minor, ucode->revision); in qe_upload_microcode()
417 "uploading microcode '%s'\n", ucode->id); in qe_upload_microcode()
420 iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR, in qe_upload_microcode()
423 for (i = 0; i < be32_to_cpu(ucode->count); i++) in qe_upload_microcode()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware() local
538 if (ucode->code_offset) in qe_upload_firmware()
539 qe_upload_microcode(firmware, ucode); in qe_upload_firmware()
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_main.c59 struct ucode { struct
113 struct ucode *ucode; in nitrox_load_fw() local
131 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
133 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
140 ucode_data = ucode->code; in nitrox_load_fw()
143 memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
182 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
184 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
191 ucode_data = ucode->code; in nitrox_load_fw()
194 memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_mbox.c140 struct otx_cpt_ucode *ucode; in otx_cpt_bind_vq_to_grp() local
165 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in otx_cpt_bind_vq_to_grp()
167 ucode = &eng_grp->ucode[0]; in otx_cpt_bind_vq_to_grp()
169 if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_SE_TYPES)) in otx_cpt_bind_vq_to_grp()
171 else if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_AE_TYPES)) in otx_cpt_bind_vq_to_grp()
/linux/drivers/input/touchscreen/
H A Dhideep.c418 const __be32 *ucode, size_t xfer_count) in hideep_program_page() argument
444 val = be32_to_cpu(ucode[0]); in hideep_program_page()
448 ucode, xfer_count); in hideep_program_page()
450 val = be32_to_cpu(ucode[xfer_count - 1]); in hideep_program_page()
467 const __be32 *ucode, size_t ucode_len) in hideep_program_nvm() argument
482 xfer_count = xfer_len / sizeof(*ucode); in hideep_program_nvm()
494 if (memcmp(ucode, current_ucode, xfer_len)) { in hideep_program_nvm()
496 ucode, xfer_count); in hideep_program_nvm()
507 ucode += xfer_count; in hideep_program_nvm()
516 const __be32 *ucode, size_t ucode_len) in hideep_verify_nvm() argument
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/linux/Documentation/arch/x86/
H A Dmicrocode.rst72 if [ -d /lib/firmware/amd-ucode ]; then
73 cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
76 if [ -d /lib/firmware/intel-ucode ]; then
77 cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin
80 find . | cpio -o -H newc >../ucode.cpio
83 cat ucode.cpio $INITRD.orig > $INITRD
104 /lib/firmware/{intel-ucode,amd-ucode}. The default distro installation
220 CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
226 |-- amd-ucode
230 |-- intel-ucode
H A Dtsx_async_abort.rst46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
71 …0 1 0 HW default No Need ucode update Need ucode up…
86 …0 1 0 HW default No Need ucode update Need ucode up…
101 …0 1 0 HW default No Need ucode update Need ucode up…
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.h13 u32 *ucode; member
27 u32 *ctxprog = ctx->ucode; in cp_out()
61 u32 *ctxprog = ctx->ucode; in cp_name()
H A Dgf104.c135 .fecs.ucode = &gf100_gr_fecs_ucode,
137 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgf110.c107 .fecs.ucode = &gf100_gr_fecs_ucode,
109 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgk110b.c126 .fecs.ucode = &gk110_gr_fecs_ucode,
128 .gpccs.ucode = &gk110_gr_gpccs_ucode,
H A Dgf108.c133 .fecs.ucode = &gf100_gr_fecs_ucode,
135 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgf119.c198 .fecs.ucode = &gf100_gr_fecs_ucode,
200 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgk208.c184 .fecs.ucode = &gk208_gr_fecs_ucode,
186 .gpccs.ucode = &gk208_gr_gpccs_ucode,
H A Dgf117.c173 .fecs.ucode = &gf117_gr_fecs_ucode,
175 .gpccs.ucode = &gf117_gr_gpccs_ucode,
H A Dgk110.c374 .fecs.ucode = &gk110_gr_fecs_ucode,
376 .gpccs.ucode = &gk110_gr_gpccs_ucode,
H A Dgk104.c478 .fecs.ucode = &gk104_gr_fecs_ucode,
480 .gpccs.ucode = &gk104_gr_gpccs_ucode,
/linux/arch/x86/kernel/cpu/microcode/
H A Damd.c593 static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc) in parse_container() argument
597 u32 *hdr = (u32 *)ucode; in parse_container()
601 if (!verify_equivalence_table(ucode, size)) in parse_container()
604 buf = ucode; in parse_container()
664 desc->data = ucode; in parse_container()
677 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc) in scan_containers() argument
680 size_t s = parse_container(ucode, size, desc); in scan_containers()
686 ucode += s; in scan_containers()

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