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Searched refs:uclk (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c33 double *uclk, in get_minimum_clocks_for_latency() argument
46 …*uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_… in get_minimum_clocks_for_latency()
310 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.uclk_khz, &state_table->uclk); in map_soc_min_clocks_to_dpm_fine_grained()
317 …t = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch.uclk_khz, &state_table->uclk); in map_soc_min_clocks_to_dpm_fine_grained()
324 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.uclk_khz, &state_table->uclk); in map_soc_min_clocks_to_dpm_fine_grained()
330 …o_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz, &state_table->uclk)) { in map_soc_min_clocks_to_dpm_fine_grained()
346 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
349 display_cfg->min_clocks.dcn4x.active.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
352 display_cfg->min_clocks.dcn4x.active.uclk_khz = state_table->uclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
360 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_soc_parameter_types.h124 struct dml2_clk_table uclk; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0.c564 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v15_0_get_vbios_bootup_values()
578 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v15_0_get_vbios_bootup_values()
593 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v15_0_get_vbios_bootup_values()
987 clock_limit = smu->smu_table.boot_values.uclk; in smu_v15_0_get_dpm_ultimate_freq()
H A Dsmu_v15_0_0_ppt.c813 clock_limit = smu->smu_table.boot_values.uclk; in smu_v15_0_0_get_dpm_ultimate_freq()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c707 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
747 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
755 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c610 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
624 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
639 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
870 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_init_max_sustainable_clocks()
1793 *value = smu->smu_table.boot_values.uclk; in smu_v13_0_get_boot_freq_by_index()
H A Daldebaran_ppt.c445 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in aldebaran_set_default_dpm_table()
H A Dsmu_v13_0_7_ppt.c642 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
H A Dsmu_v13_0_0_ppt.c623 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_0_set_default_dpm_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c595 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
609 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
624 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
1103 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_get_dpm_ultimate_freq()
H A Dsmu_v14_0_0_ppt.c792 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_1_get_dpm_ultimate_freq()
914 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_0_get_dpm_ultimate_freq()
H A Dsmu_v14_0_2_ppt.c521 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v14_0_2_set_default_dpm_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c554 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()
571 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()
837 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1726 clock_limit = smu->smu_table.boot_values.uclk; in smu_v11_0_get_dpm_ultimate_freq()
H A Darcturus_ppt.c409 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
H A Dvangogh_ppt.c908 clock_limit = smu->smu_table.boot_values.uclk; in vangogh_get_dpm_ultimate_freq()
H A Dnavi10_ppt.c1015 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in navi10_set_default_dpm_table()
H A Dsienna_cichlid_ppt.c1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dt3_hw.c586 VPD_ENTRY(uclk, 6); /* uP clk */
671 ret = vpdstrtouint(vpd.uclk_data, vpd.uclk_len, 10, &p->uclk); in get_vpd_params()
3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h343 uint32_t uclk; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c286 clock_limit = smu->smu_table.boot_values.uclk; in renoir_get_dpm_ultimate_freq()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h380 uint8_t uclk : 1; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c7136 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index()
7137 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in get_active_min_uclk_dpm_index()
7139 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in get_active_min_uclk_dpm_index()
12038 …max_uclk_mhz = mode_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_va… in dml_core_mode_programming()