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Searched refs:topckgen (Results 1 – 24 of 24) sorted by relevance

/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
H A Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
H A Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
H A Dmt8135.dtsi127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
H A Dmt7623a.dtsi133 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
H A Dmt2701-evb.dts106 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
H A Dmt7623n.dtsi44 clocks = <&topckgen CLK_TOP_MMPLL>,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
296 topckgen: clock-controller@10210000 { label
297 compatible = "mediatek,mt7622-topckgen";
335 clocks = <&topckgen CLK_TOP_RTC>;
399 clocks = <&topckgen CLK_TOP_UART_SEL>,
410 clocks = <&topckgen CLK_TOP_UART_SEL>,
421 clocks = <&topckgen CLK_TOP_UART_SEL>,
432 clocks = <&topckgen CLK_TOP_UART_SEL>,
443 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
H A Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
H A Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
H A Dmt8365.dtsi336 topckgen: syscon@10000000 { label
337 compatible = "mediatek,mt8365-topckgen", "syscon";
373 clocks = <&topckgen CLK_TOP_MM_SEL>,
435 clocks = <&topckgen CLK_TOP_CONN_32K>,
436 <&topckgen CLK_TOP_CONN_26M>;
444 clocks = <&topckgen CLK_TOP_MFG_SEL>;
452 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
462 clocks = <&topckgen CLK_TOP_DSP_SEL>,
463 <&topckgen CLK_TOP_DSP_26M>;
660 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
[all …]
H A Dmt7622-rfb1.dts224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
240 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
H A Dmt7622-bananapi-bpi-r64.dts242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
243 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
258 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
259 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
H A Dmt8365-evk.dts366 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
367 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt8186-corsola.dtsi542 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>;
/linux/Documentation/devicetree/bindings/sound/
H A Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
/linux/drivers/clk/mediatek/
H A DMakefile5 …MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
27 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
63 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
67 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
71 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
83 clk-mt8173-pericfg.o clk-mt8173-topckgen.o
100 obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-topckgen.o \
113 obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
139 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
153 obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c648 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node, in mt8192_init_clock()
650 if (IS_ERR(afe_priv->topckgen)) { in mt8192_init_clock()
652 __func__, PTR_ERR(afe_priv->topckgen)); in mt8192_init_clock()
653 return PTR_ERR(afe_priv->topckgen); in mt8192_init_clock()
H A Dmt8192-afe-common.h132 struct regmap *topckgen; member
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-afe-common.h128 struct regmap *topckgen; member
H A Dmt8195-afe-pcm.c3115 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,topckgen"); in mt8195_afe_pcm_dev_probe()
3116 if (IS_ERR(afe_priv->topckgen)) in mt8195_afe_pcm_dev_probe()
3118 PTR_ERR(afe_priv->topckgen)); in mt8195_afe_pcm_dev_probe()
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-common.h144 struct regmap *topckgen; member
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-common.h334 struct regmap *topckgen; member
/linux/
H A DMAINTAINERS16267 F: drivers/clk/mediatek/clk-mt6735-topckgen.c
16275 F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h