1*22d9f809SKai Chieh ChuangMediatek AFE PCM controller for mt6797 2*22d9f809SKai Chieh Chuang 3*22d9f809SKai Chieh ChuangRequired properties: 4*22d9f809SKai Chieh Chuang- compatible = "mediatek,mt6797-audio"; 5*22d9f809SKai Chieh Chuang- reg: register location and size 6*22d9f809SKai Chieh Chuang- interrupts: should contain AFE interrupt 7*22d9f809SKai Chieh Chuang- power-domains: should define the power domain 8*22d9f809SKai Chieh Chuang- clocks: Must contain an entry for each entry in clock-names 9*22d9f809SKai Chieh Chuang- clock-names: should have these clock names: 10*22d9f809SKai Chieh Chuang "infra_sys_audio_clk", 11*22d9f809SKai Chieh Chuang "infra_sys_audio_26m", 12*22d9f809SKai Chieh Chuang "mtkaif_26m_clk", 13*22d9f809SKai Chieh Chuang "top_mux_audio", 14*22d9f809SKai Chieh Chuang "top_mux_aud_intbus", 15*22d9f809SKai Chieh Chuang "top_sys_pll3_d4", 16*22d9f809SKai Chieh Chuang "top_sys_pll1_d4", 17*22d9f809SKai Chieh Chuang "top_clk26m_clk"; 18*22d9f809SKai Chieh Chuang 19*22d9f809SKai Chieh ChuangExample: 20*22d9f809SKai Chieh Chuang 21*22d9f809SKai Chieh Chuang afe: mt6797-afe-pcm@11220000 { 22*22d9f809SKai Chieh Chuang compatible = "mediatek,mt6797-audio"; 23*22d9f809SKai Chieh Chuang reg = <0 0x11220000 0 0x1000>; 24*22d9f809SKai Chieh Chuang interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>; 25*22d9f809SKai Chieh Chuang power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>; 26*22d9f809SKai Chieh Chuang clocks = <&infrasys CLK_INFRA_AUDIO>, 27*22d9f809SKai Chieh Chuang <&infrasys CLK_INFRA_AUDIO_26M>, 28*22d9f809SKai Chieh Chuang <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>, 29*22d9f809SKai Chieh Chuang <&topckgen CLK_TOP_MUX_AUDIO>, 30*22d9f809SKai Chieh Chuang <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 31*22d9f809SKai Chieh Chuang <&topckgen CLK_TOP_SYSPLL3_D4>, 32*22d9f809SKai Chieh Chuang <&topckgen CLK_TOP_SYSPLL1_D4>, 33*22d9f809SKai Chieh Chuang <&clk26m>; 34*22d9f809SKai Chieh Chuang clock-names = "infra_sys_audio_clk", 35*22d9f809SKai Chieh Chuang "infra_sys_audio_26m", 36*22d9f809SKai Chieh Chuang "mtkaif_26m_clk", 37*22d9f809SKai Chieh Chuang "top_mux_audio", 38*22d9f809SKai Chieh Chuang "top_mux_aud_intbus", 39*22d9f809SKai Chieh Chuang "top_sys_pll3_d4", 40*22d9f809SKai Chieh Chuang "top_sys_pll1_d4", 41*22d9f809SKai Chieh Chuang "top_clk26m_clk"; 42*22d9f809SKai Chieh Chuang }; 43