| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | aldebaran.c | 157 struct amdgpu_device *tmp_adev = NULL; in aldebaran_mode2_perform_reset() local
171 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { in aldebaran_mode2_perform_reset()
172 mutex_lock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
173 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; in aldebaran_mode2_perform_reset()
179 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { in aldebaran_mode2_perform_reset()
181 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { in aldebaran_mode2_perform_reset()
183 &tmp_adev->reset_cntl->reset_work)) in aldebaran_mode2_perform_reset()
186 r = aldebaran_mode2_reset(tmp_adev); in aldebaran_mode2_perform_reset()
188 dev_err(tmp_adev->dev, in aldebaran_mode2_perform_reset()
190 r, adev_to_drm(tmp_adev)->unique); in aldebaran_mode2_perform_reset()
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| H A D | amdgpu_reset.c | 61 struct amdgpu_device *tmp_adev; in amdgpu_reset_xgmi_reset_on_init_prep_hwctxt() local
64 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { in amdgpu_reset_xgmi_reset_on_init_prep_hwctxt()
65 amdgpu_unregister_gpu_instance(tmp_adev); in amdgpu_reset_xgmi_reset_on_init_prep_hwctxt()
66 r = amdgpu_reset_xgmi_reset_on_init_suspend(tmp_adev); in amdgpu_reset_xgmi_reset_on_init_prep_hwctxt()
68 dev_err(tmp_adev->dev, in amdgpu_reset_xgmi_reset_on_init_prep_hwctxt()
82 struct amdgpu_device *tmp_adev = NULL; in amdgpu_reset_xgmi_reset_on_init_restore_hwctxt() local
88 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { in amdgpu_reset_xgmi_reset_on_init_restore_hwctxt()
89 if (!tmp_adev->kfd.init_complete) { in amdgpu_reset_xgmi_reset_on_init_restore_hwctxt()
90 kgd2kfd_init_zone_device(tmp_adev); in amdgpu_reset_xgmi_reset_on_init_restore_hwctxt()
91 amdgpu_amdkfd_device_init(tmp_adev); in amdgpu_reset_xgmi_reset_on_init_restore_hwctxt()
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| H A D | sienna_cichlid.c | 221 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle; in sienna_cichlid_mode2_restore_hwcontext() local
223 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY); in sienna_cichlid_mode2_restore_hwcontext()
224 dev_info(tmp_adev->dev, in sienna_cichlid_mode2_restore_hwcontext()
226 r = sienna_cichlid_mode2_restore_ip(tmp_adev); in sienna_cichlid_mode2_restore_hwcontext()
234 amdgpu_register_gpu_instance(tmp_adev); in sienna_cichlid_mode2_restore_hwcontext()
237 amdgpu_ras_resume(tmp_adev); in sienna_cichlid_mode2_restore_hwcontext()
239 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); in sienna_cichlid_mode2_restore_hwcontext()
241 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT); in sienna_cichlid_mode2_restore_hwcontext()
242 r = amdgpu_ib_ring_tests(tmp_adev); in sienna_cichlid_mode2_restore_hwcontext()
244 dev_err(tmp_adev->dev, in sienna_cichlid_mode2_restore_hwcontext()
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| H A D | smu_v13_0_10.c | 222 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle; in smu_v13_0_10_mode2_restore_hwcontext() local
224 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY); in smu_v13_0_10_mode2_restore_hwcontext()
225 dev_info(tmp_adev->dev, in smu_v13_0_10_mode2_restore_hwcontext()
227 r = smu_v13_0_10_mode2_restore_ip(tmp_adev); in smu_v13_0_10_mode2_restore_hwcontext()
231 amdgpu_register_gpu_instance(tmp_adev); in smu_v13_0_10_mode2_restore_hwcontext()
234 amdgpu_ras_resume(tmp_adev); in smu_v13_0_10_mode2_restore_hwcontext()
236 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); in smu_v13_0_10_mode2_restore_hwcontext()
238 amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT); in smu_v13_0_10_mode2_restore_hwcontext()
239 r = amdgpu_ib_ring_tests(tmp_adev); in smu_v13_0_10_mode2_restore_hwcontext()
241 dev_err(tmp_adev->dev, in smu_v13_0_10_mode2_restore_hwcontext()
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| H A D | amdgpu_xgmi.c | 952 struct amdgpu_device *tmp_adev; in amdgpu_xgmi_initialize_hive_get_data_partition() local
955 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { in amdgpu_xgmi_initialize_hive_get_data_partition()
956 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); in amdgpu_xgmi_initialize_hive_get_data_partition()
958 dev_err(tmp_adev->dev, in amdgpu_xgmi_initialize_hive_get_data_partition()
974 struct amdgpu_device *tmp_adev = NULL; in amdgpu_xgmi_add_device() local
1028 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { in amdgpu_xgmi_add_device()
1030 if (tmp_adev != adev) { in amdgpu_xgmi_add_device()
1031 top_info = &tmp_adev->psp.xgmi_context.top_info; in amdgpu_xgmi_add_device()
1036 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); in amdgpu_xgmi_add_device()
1056 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { in amdgpu_xgmi_add_device()
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| H A D | amdgpu_device.c | 5794 struct amdgpu_device *tmp_adev = reset_context->reset_req_dev; in amdgpu_device_pre_asic_reset() local
5847 dev_info(tmp_adev->dev, "Dumping IP State\n"); in amdgpu_device_pre_asic_reset()
5849 for (i = 0; i < tmp_adev->num_ip_blocks; i++) in amdgpu_device_pre_asic_reset()
5850 if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state) in amdgpu_device_pre_asic_reset()
5851 tmp_adev->ip_blocks[i].version->funcs in amdgpu_device_pre_asic_reset()
5852 ->dump_ip_state((void *)&tmp_adev->ip_blocks[i]); in amdgpu_device_pre_asic_reset()
5853 dev_info(tmp_adev->dev, "Dumping IP State Completed\n"); in amdgpu_device_pre_asic_reset()
5872 struct amdgpu_device *tmp_adev; in amdgpu_device_reinit_after_reset() local
5892 list_for_each_entry(tmp_adev, device_list_handle, reset_list) { in amdgpu_device_reinit_after_reset()
5893 amdgpu_set_init_level(tmp_adev, init_level); in amdgpu_device_reinit_after_reset()
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| H A D | amdgpu_job.c | 55 struct amdgpu_device *tmp_adev = NULL; in amdgpu_job_core_dump() local
68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) in amdgpu_job_core_dump()
69 list_add_tail(&tmp_adev->reset_list, &device_list); in amdgpu_job_core_dump()
79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) in amdgpu_job_core_dump()
80 amdgpu_job_do_core_dump(tmp_adev, job); in amdgpu_job_core_dump()
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| H A D | amdgpu_ras.c | 2855 struct amdgpu_device *tmp_adev; in amdgpu_ras_set_fed_all() local
2858 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) in amdgpu_ras_set_fed_all()
2859 amdgpu_ras_set_fed(tmp_adev, status); in amdgpu_ras_set_fed_all()
5742 struct amdgpu_device *tmp_adev = NULL; in amdgpu_ras_pre_reset() local
5744 list_for_each_entry(tmp_adev, device_list, reset_list) { in amdgpu_ras_pre_reset()
5745 if (amdgpu_uniras_enabled(tmp_adev)) in amdgpu_ras_pre_reset()
5746 amdgpu_ras_mgr_pre_reset(tmp_adev); in amdgpu_ras_pre_reset()
5753 struct amdgpu_device *tmp_adev = NULL; in amdgpu_ras_post_reset() local
5755 list_for_each_entry(tmp_adev, device_list, reset_list) { in amdgpu_ras_post_reset()
5756 if (amdgpu_uniras_enabled(tmp_adev)) in amdgpu_ras_post_reset()
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