1230dd6bbSKenneth Feng /*
2230dd6bbSKenneth Feng * Copyright 2023 Advanced Micro Devices, Inc.
3230dd6bbSKenneth Feng *
4230dd6bbSKenneth Feng * Permission is hereby granted, free of charge, to any person obtaining a
5230dd6bbSKenneth Feng * copy of this software and associated documentation files (the "Software"),
6230dd6bbSKenneth Feng * to deal in the Software without restriction, including without limitation
7230dd6bbSKenneth Feng * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8230dd6bbSKenneth Feng * and/or sell copies of the Software, and to permit persons to whom the
9230dd6bbSKenneth Feng * Software is furnished to do so, subject to the following conditions:
10230dd6bbSKenneth Feng *
11230dd6bbSKenneth Feng * The above copyright notice and this permission notice shall be included in
12230dd6bbSKenneth Feng * all copies or substantial portions of the Software.
13230dd6bbSKenneth Feng *
14230dd6bbSKenneth Feng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15230dd6bbSKenneth Feng * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16230dd6bbSKenneth Feng * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17230dd6bbSKenneth Feng * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18230dd6bbSKenneth Feng * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19230dd6bbSKenneth Feng * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20230dd6bbSKenneth Feng * OTHER DEALINGS IN THE SOFTWARE.
21230dd6bbSKenneth Feng *
22230dd6bbSKenneth Feng */
23230dd6bbSKenneth Feng
24230dd6bbSKenneth Feng #include "smu_v13_0_10.h"
25230dd6bbSKenneth Feng #include "amdgpu_reset.h"
26230dd6bbSKenneth Feng #include "amdgpu_dpm.h"
27230dd6bbSKenneth Feng #include "amdgpu_job.h"
28230dd6bbSKenneth Feng #include "amdgpu_ring.h"
29230dd6bbSKenneth Feng #include "amdgpu_ras.h"
30230dd6bbSKenneth Feng #include "amdgpu_psp.h"
31230dd6bbSKenneth Feng
smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control * reset_ctl)32230dd6bbSKenneth Feng static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
33230dd6bbSKenneth Feng {
34230dd6bbSKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
35230dd6bbSKenneth Feng if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))
36230dd6bbSKenneth Feng return true;
37230dd6bbSKenneth Feng
38230dd6bbSKenneth Feng return false;
39230dd6bbSKenneth Feng }
40230dd6bbSKenneth Feng
41230dd6bbSKenneth Feng static struct amdgpu_reset_handler *
smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)42230dd6bbSKenneth Feng smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
43230dd6bbSKenneth Feng struct amdgpu_reset_context *reset_context)
44230dd6bbSKenneth Feng {
45230dd6bbSKenneth Feng struct amdgpu_reset_handler *handler;
46230dd6bbSKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
47f8a499aeSLijo Lazar int i;
48230dd6bbSKenneth Feng
49230dd6bbSKenneth Feng if (reset_context->method != AMD_RESET_METHOD_NONE) {
50f8a499aeSLijo Lazar for_each_handler(i, handler, reset_ctl) {
51230dd6bbSKenneth Feng if (handler->reset_method == reset_context->method)
52230dd6bbSKenneth Feng return handler;
53230dd6bbSKenneth Feng }
54230dd6bbSKenneth Feng }
55230dd6bbSKenneth Feng
56230dd6bbSKenneth Feng if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
57230dd6bbSKenneth Feng amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) {
58f8a499aeSLijo Lazar for_each_handler(i, handler, reset_ctl) {
59230dd6bbSKenneth Feng if (handler->reset_method == AMD_RESET_METHOD_MODE2)
60230dd6bbSKenneth Feng return handler;
61230dd6bbSKenneth Feng }
62230dd6bbSKenneth Feng }
63230dd6bbSKenneth Feng
64230dd6bbSKenneth Feng return NULL;
65230dd6bbSKenneth Feng }
66230dd6bbSKenneth Feng
smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device * adev)67230dd6bbSKenneth Feng static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)
68230dd6bbSKenneth Feng {
69230dd6bbSKenneth Feng int r, i;
70230dd6bbSKenneth Feng
71230dd6bbSKenneth Feng amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
72230dd6bbSKenneth Feng amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
73230dd6bbSKenneth Feng
74230dd6bbSKenneth Feng for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
75230dd6bbSKenneth Feng if (!(adev->ip_blocks[i].version->type ==
76230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_GFX ||
77230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
78230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_SDMA ||
79230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
80230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_MES))
81230dd6bbSKenneth Feng continue;
82230dd6bbSKenneth Feng
83230dd6bbSKenneth Feng r = adev->ip_blocks[i].version->funcs->suspend(adev);
84230dd6bbSKenneth Feng
85230dd6bbSKenneth Feng if (r) {
86230dd6bbSKenneth Feng dev_err(adev->dev,
87230dd6bbSKenneth Feng "suspend of IP block <%s> failed %d\n",
88230dd6bbSKenneth Feng adev->ip_blocks[i].version->funcs->name, r);
89230dd6bbSKenneth Feng return r;
90230dd6bbSKenneth Feng }
91230dd6bbSKenneth Feng adev->ip_blocks[i].status.hw = false;
92230dd6bbSKenneth Feng }
93230dd6bbSKenneth Feng
94*df65aabeSMa Ke return 0;
95230dd6bbSKenneth Feng }
96230dd6bbSKenneth Feng
97230dd6bbSKenneth Feng static int
smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)98230dd6bbSKenneth Feng smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
99230dd6bbSKenneth Feng struct amdgpu_reset_context *reset_context)
100230dd6bbSKenneth Feng {
101230dd6bbSKenneth Feng int r = 0;
102230dd6bbSKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
103230dd6bbSKenneth Feng
104230dd6bbSKenneth Feng if (!amdgpu_sriov_vf(adev))
105230dd6bbSKenneth Feng r = smu_v13_0_10_mode2_suspend_ip(adev);
106230dd6bbSKenneth Feng
107230dd6bbSKenneth Feng return r;
108230dd6bbSKenneth Feng }
109230dd6bbSKenneth Feng
smu_v13_0_10_mode2_reset(struct amdgpu_device * adev)110230dd6bbSKenneth Feng static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)
111230dd6bbSKenneth Feng {
112230dd6bbSKenneth Feng return amdgpu_dpm_mode2_reset(adev);
113230dd6bbSKenneth Feng }
114230dd6bbSKenneth Feng
smu_v13_0_10_async_reset(struct work_struct * work)115230dd6bbSKenneth Feng static void smu_v13_0_10_async_reset(struct work_struct *work)
116230dd6bbSKenneth Feng {
117230dd6bbSKenneth Feng struct amdgpu_reset_handler *handler;
118230dd6bbSKenneth Feng struct amdgpu_reset_control *reset_ctl =
119230dd6bbSKenneth Feng container_of(work, struct amdgpu_reset_control, reset_work);
120230dd6bbSKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
121f8a499aeSLijo Lazar int i;
122230dd6bbSKenneth Feng
123f8a499aeSLijo Lazar for_each_handler(i, handler, reset_ctl) {
124230dd6bbSKenneth Feng if (handler->reset_method == reset_ctl->active_reset) {
125230dd6bbSKenneth Feng dev_dbg(adev->dev, "Resetting device\n");
126230dd6bbSKenneth Feng handler->do_reset(adev);
127230dd6bbSKenneth Feng break;
128230dd6bbSKenneth Feng }
129230dd6bbSKenneth Feng }
130230dd6bbSKenneth Feng }
131230dd6bbSKenneth Feng static int
smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)132230dd6bbSKenneth Feng smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
133230dd6bbSKenneth Feng struct amdgpu_reset_context *reset_context)
134230dd6bbSKenneth Feng {
135230dd6bbSKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
136230dd6bbSKenneth Feng int r;
137230dd6bbSKenneth Feng
138230dd6bbSKenneth Feng r = smu_v13_0_10_mode2_reset(adev);
139230dd6bbSKenneth Feng if (r) {
140230dd6bbSKenneth Feng dev_err(adev->dev,
141230dd6bbSKenneth Feng "ASIC reset failed with error, %d ", r);
142230dd6bbSKenneth Feng }
143230dd6bbSKenneth Feng return r;
144230dd6bbSKenneth Feng }
145230dd6bbSKenneth Feng
smu_v13_0_10_mode2_restore_ip(struct amdgpu_device * adev)146230dd6bbSKenneth Feng static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)
147230dd6bbSKenneth Feng {
148230dd6bbSKenneth Feng int i, r;
149230dd6bbSKenneth Feng struct psp_context *psp = &adev->psp;
150230dd6bbSKenneth Feng struct amdgpu_firmware_info *ucode;
151230dd6bbSKenneth Feng struct amdgpu_firmware_info *ucode_list[2];
152230dd6bbSKenneth Feng int ucode_count = 0;
153230dd6bbSKenneth Feng
154230dd6bbSKenneth Feng for (i = 0; i < adev->firmware.max_ucodes; i++) {
155230dd6bbSKenneth Feng ucode = &adev->firmware.ucode[i];
156230dd6bbSKenneth Feng
157230dd6bbSKenneth Feng switch (ucode->ucode_id) {
158230dd6bbSKenneth Feng case AMDGPU_UCODE_ID_IMU_I:
159230dd6bbSKenneth Feng case AMDGPU_UCODE_ID_IMU_D:
160230dd6bbSKenneth Feng ucode_list[ucode_count++] = ucode;
161230dd6bbSKenneth Feng break;
162230dd6bbSKenneth Feng default:
163230dd6bbSKenneth Feng break;
164230dd6bbSKenneth Feng }
165230dd6bbSKenneth Feng }
166230dd6bbSKenneth Feng
167230dd6bbSKenneth Feng r = psp_load_fw_list(psp, ucode_list, ucode_count);
168230dd6bbSKenneth Feng if (r) {
169230dd6bbSKenneth Feng dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n");
170230dd6bbSKenneth Feng return r;
171230dd6bbSKenneth Feng }
172230dd6bbSKenneth Feng
173230dd6bbSKenneth Feng r = psp_rlc_autoload_start(psp);
174230dd6bbSKenneth Feng if (r) {
175230dd6bbSKenneth Feng DRM_ERROR("Failed to start rlc autoload after mode2 reset\n");
176230dd6bbSKenneth Feng return r;
177230dd6bbSKenneth Feng }
178230dd6bbSKenneth Feng
179230dd6bbSKenneth Feng amdgpu_dpm_enable_gfx_features(adev);
180230dd6bbSKenneth Feng
181230dd6bbSKenneth Feng for (i = 0; i < adev->num_ip_blocks; i++) {
182230dd6bbSKenneth Feng if (!(adev->ip_blocks[i].version->type ==
183230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_GFX ||
184230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
185230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_MES ||
186230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
187230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_SDMA))
188230dd6bbSKenneth Feng continue;
189230dd6bbSKenneth Feng r = adev->ip_blocks[i].version->funcs->resume(adev);
190230dd6bbSKenneth Feng if (r) {
191230dd6bbSKenneth Feng dev_err(adev->dev,
192230dd6bbSKenneth Feng "resume of IP block <%s> failed %d\n",
193230dd6bbSKenneth Feng adev->ip_blocks[i].version->funcs->name, r);
194230dd6bbSKenneth Feng return r;
195230dd6bbSKenneth Feng }
196230dd6bbSKenneth Feng
197230dd6bbSKenneth Feng adev->ip_blocks[i].status.hw = true;
198230dd6bbSKenneth Feng }
199230dd6bbSKenneth Feng
200230dd6bbSKenneth Feng for (i = 0; i < adev->num_ip_blocks; i++) {
201230dd6bbSKenneth Feng if (!(adev->ip_blocks[i].version->type ==
202230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_GFX ||
203230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
204230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_MES ||
205230dd6bbSKenneth Feng adev->ip_blocks[i].version->type ==
206230dd6bbSKenneth Feng AMD_IP_BLOCK_TYPE_SDMA))
207230dd6bbSKenneth Feng continue;
208230dd6bbSKenneth Feng
209230dd6bbSKenneth Feng if (adev->ip_blocks[i].version->funcs->late_init) {
210230dd6bbSKenneth Feng r = adev->ip_blocks[i].version->funcs->late_init(
211230dd6bbSKenneth Feng (void *)adev);
212230dd6bbSKenneth Feng if (r) {
213230dd6bbSKenneth Feng dev_err(adev->dev,
214230dd6bbSKenneth Feng "late_init of IP block <%s> failed %d after reset\n",
215230dd6bbSKenneth Feng adev->ip_blocks[i].version->funcs->name,
216230dd6bbSKenneth Feng r);
217230dd6bbSKenneth Feng return r;
218230dd6bbSKenneth Feng }
219230dd6bbSKenneth Feng }
220230dd6bbSKenneth Feng adev->ip_blocks[i].status.late_initialized = true;
221230dd6bbSKenneth Feng }
222230dd6bbSKenneth Feng
223230dd6bbSKenneth Feng amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
224230dd6bbSKenneth Feng amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
225230dd6bbSKenneth Feng
226230dd6bbSKenneth Feng return r;
227230dd6bbSKenneth Feng }
228230dd6bbSKenneth Feng
229230dd6bbSKenneth Feng static int
smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)230230dd6bbSKenneth Feng smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
231230dd6bbSKenneth Feng struct amdgpu_reset_context *reset_context)
232230dd6bbSKenneth Feng {
233230dd6bbSKenneth Feng int r;
234230dd6bbSKenneth Feng struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
235230dd6bbSKenneth Feng
236230dd6bbSKenneth Feng dev_info(tmp_adev->dev,
237230dd6bbSKenneth Feng "GPU reset succeeded, trying to resume\n");
238230dd6bbSKenneth Feng r = smu_v13_0_10_mode2_restore_ip(tmp_adev);
239230dd6bbSKenneth Feng if (r)
240230dd6bbSKenneth Feng goto end;
241230dd6bbSKenneth Feng
242230dd6bbSKenneth Feng amdgpu_register_gpu_instance(tmp_adev);
243230dd6bbSKenneth Feng
244230dd6bbSKenneth Feng /* Resume RAS */
245230dd6bbSKenneth Feng amdgpu_ras_resume(tmp_adev);
246230dd6bbSKenneth Feng
247230dd6bbSKenneth Feng amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
248230dd6bbSKenneth Feng
249230dd6bbSKenneth Feng r = amdgpu_ib_ring_tests(tmp_adev);
250230dd6bbSKenneth Feng if (r) {
251230dd6bbSKenneth Feng dev_err(tmp_adev->dev,
252230dd6bbSKenneth Feng "ib ring test failed (%d).\n", r);
253230dd6bbSKenneth Feng r = -EAGAIN;
254230dd6bbSKenneth Feng goto end;
255230dd6bbSKenneth Feng }
256230dd6bbSKenneth Feng
257230dd6bbSKenneth Feng end:
258230dd6bbSKenneth Feng if (r)
259230dd6bbSKenneth Feng return -EAGAIN;
260230dd6bbSKenneth Feng else
261230dd6bbSKenneth Feng return r;
262230dd6bbSKenneth Feng }
263230dd6bbSKenneth Feng
264230dd6bbSKenneth Feng static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = {
265230dd6bbSKenneth Feng .reset_method = AMD_RESET_METHOD_MODE2,
266230dd6bbSKenneth Feng .prepare_env = NULL,
267230dd6bbSKenneth Feng .prepare_hwcontext = smu_v13_0_10_mode2_prepare_hwcontext,
268230dd6bbSKenneth Feng .perform_reset = smu_v13_0_10_mode2_perform_reset,
269230dd6bbSKenneth Feng .restore_hwcontext = smu_v13_0_10_mode2_restore_hwcontext,
270230dd6bbSKenneth Feng .restore_env = NULL,
271230dd6bbSKenneth Feng .do_reset = smu_v13_0_10_mode2_reset,
272230dd6bbSKenneth Feng };
273230dd6bbSKenneth Feng
274f8a499aeSLijo Lazar static struct amdgpu_reset_handler
275f8a499aeSLijo Lazar *smu_v13_0_10_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
276f8a499aeSLijo Lazar &smu_v13_0_10_mode2_handler,
277f8a499aeSLijo Lazar };
278f8a499aeSLijo Lazar
smu_v13_0_10_reset_init(struct amdgpu_device * adev)279230dd6bbSKenneth Feng int smu_v13_0_10_reset_init(struct amdgpu_device *adev)
280230dd6bbSKenneth Feng {
281230dd6bbSKenneth Feng struct amdgpu_reset_control *reset_ctl;
282230dd6bbSKenneth Feng
283230dd6bbSKenneth Feng reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
284230dd6bbSKenneth Feng if (!reset_ctl)
285230dd6bbSKenneth Feng return -ENOMEM;
286230dd6bbSKenneth Feng
287230dd6bbSKenneth Feng reset_ctl->handle = adev;
288230dd6bbSKenneth Feng reset_ctl->async_reset = smu_v13_0_10_async_reset;
289230dd6bbSKenneth Feng reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
290230dd6bbSKenneth Feng reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler;
291230dd6bbSKenneth Feng
292230dd6bbSKenneth Feng INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
293230dd6bbSKenneth Feng /* Only mode2 is handled through reset control now */
294f8a499aeSLijo Lazar reset_ctl->reset_handlers = &smu_v13_0_10_rst_handlers;
295230dd6bbSKenneth Feng
296230dd6bbSKenneth Feng adev->reset_cntl = reset_ctl;
297230dd6bbSKenneth Feng
298230dd6bbSKenneth Feng return 0;
299230dd6bbSKenneth Feng }
300230dd6bbSKenneth Feng
smu_v13_0_10_reset_fini(struct amdgpu_device * adev)301230dd6bbSKenneth Feng int smu_v13_0_10_reset_fini(struct amdgpu_device *adev)
302230dd6bbSKenneth Feng {
303230dd6bbSKenneth Feng kfree(adev->reset_cntl);
304230dd6bbSKenneth Feng adev->reset_cntl = NULL;
305230dd6bbSKenneth Feng return 0;
306230dd6bbSKenneth Feng }
307