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Searched refs:timing (Results 1 – 25 of 321) sorted by relevance

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/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
210 struct emc_timing *timing) in emc_set_timing() argument
221 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, in emc_set_timing()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
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/linux/drivers/video/fbdev/
H A Dgbefb.c38 struct gbe_timing_info timing; member
411 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
417 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
419 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
427 timing->pll_m = 4; in gbefb_setup_flatpanel()
428 timing->pll_n = 1; in gbefb_setup_flatpanel()
429 timing->pll_p = 0; in gbefb_setup_flatpanel()
456 struct gbe_timing_info *timing) in compute_gbe_timing() argument
504 if (timing) { in compute_gbe_timing()
505 timing->width = var->xres; in compute_gbe_timing()
[all …]
/linux/drivers/video/fbdev/via/
H A Dvia_modesetting.c18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
83 timing->h_border_right - in optc201_validate_timing()
84 timing->h_border_left); in optc201_validate_timing()
86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && in optc201_validate_timing()
88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc201_validate_timing()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
[all …]
H A Dramgt215.c348 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) in gt215_ram_timing_calc() argument
374 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
383 timing[3] = (cur3 & 0x00ff0000) | in gt215_ram_timing_calc()
387 timing[4] = T(20) << 24 | in gt215_ram_timing_calc()
391 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
398 timing[7] = (cur7 & 0xff000000) | in gt215_ram_timing_calc()
401 timing[8] = cur8 & 0xffffff00; in gt215_ram_timing_calc()
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
[all …]
/linux/drivers/ata/
H A Dpata_triflex.c76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
106 timing = 0x0808;break; in triflex_load_timing()
[all …]
H A Dpata_cs5530.c76 u32 tuning, timing = 0; in cs5530_set_dmamode() local
84 timing = 0x00921250;break; in cs5530_set_dmamode()
86 timing = 0x00911140;break; in cs5530_set_dmamode()
88 timing = 0x00911030;break; in cs5530_set_dmamode()
90 timing = 0x00077771;break; in cs5530_set_dmamode()
92 timing = 0x00012121;break; in cs5530_set_dmamode()
94 timing = 0x00002020;break; in cs5530_set_dmamode()
99 timing |= (tuning & 0x80000000UL); in cs5530_set_dmamode()
101 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
103 if (timing & 0x00100000) in cs5530_set_dmamode()
[all …]
/linux/drivers/memory/samsung/
H A Dexynos-srom.c71 u32 timing[6]; in exynos_srom_configure_bank() local
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
81 ARRAY_SIZE(timing))) in exynos_srom_configure_bank()
94 writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) | in exynos_srom_configure_bank()
95 (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) | in exynos_srom_configure_bank()
96 (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) | in exynos_srom_configure_bank()
97 (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) | in exynos_srom_configure_bank()
98 (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) | in exynos_srom_configure_bank()
99 (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT), in exynos_srom_configure_bank()
/linux/drivers/pcmcia/
H A Dsa11xx_base.c81 struct soc_pcmcia_timing timing; in sa1100_pcmcia_set_mecr() local
86 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_set_mecr()
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); in sa1100_pcmcia_set_mecr()
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); in sa1100_pcmcia_set_mecr()
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); in sa1100_pcmcia_set_mecr()
146 struct soc_pcmcia_timing timing; in sa1100_pcmcia_show_timing() local
151 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_show_timing()
153 p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io, in sa1100_pcmcia_show_timing()
156 p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr, in sa1100_pcmcia_show_timing()
159 p+=sprintf(p, "common : %uns (%uns)\n", timing.mem, in sa1100_pcmcia_show_timing()
/linux/drivers/nvmem/
H A Dvf610-ocotp.c94 int timing; member
118 u32 timing; in vf610_ocotp_calculate_timing() local
127 timing = BF(relax, OCOTP_TIMING_RELAX); in vf610_ocotp_calculate_timing()
128 timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); in vf610_ocotp_calculate_timing()
129 timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); in vf610_ocotp_calculate_timing()
131 return timing; in vf610_ocotp_calculate_timing()
158 writel(ocotp->timing, base + OCOTP_TIMING); in vf610_ocotp_read()
233 ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev); in vf610_ocotp_probe()
/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.c340 …(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc; in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed… in dml2_core_utils_get_stream_output_bpp()
364 …display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable); in dml2_core_utils_get_stream_output_bpp()
580 phantom->timing.v_total = meta->v_total; in create_phantom_stream_from_main_stream()
581 phantom->timing.v_active = meta->v_active; in create_phantom_stream_from_main_stream()
582 phantom->timing.v_front_porch = meta->v_front_porch; in create_phantom_stream_from_main_stream()
583 …phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->t… in create_phantom_stream_from_main_stream()
584 phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; in create_phantom_stream_from_main_stream()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-tx6-lvds.dtsi94 timing-hsd100pxn1 {
108 timing-vga {
124 timing-nl12880bc20 {
140 timing-et0700 {
156 timing-etv570 {
187 timing-hsd100pxn1 {
201 timing-vga {
217 timing-nl12880bc20 {
H A Dimx6qdl-tx6-lcd.dtsi76 timing-vga {
92 timing-etv570 {
108 timing-et0350 {
124 timing-et0430 {
140 timing-et0500 {
156 timing-et0700 { /* same as ET0500 */
172 timing-etq570 {
188 timing-comtft { /* same as ET0700 but with inverted pixel clock */
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/linux/drivers/leds/
H A Dleds-sun50i-a100.c90 struct sun50i_a100_ledc_timing timing; member
287 struct sun50i_a100_ledc_timing *timing = &priv->timing; in sun50i_a100_ledc_parse_timing() local
289 *timing = sun50i_a100_ledc_default_timing; in sun50i_a100_ledc_parse_timing()
291 device_property_read_u32(dev, "allwinner,t0h-ns", &timing->t0h_ns); in sun50i_a100_ledc_parse_timing()
292 device_property_read_u32(dev, "allwinner,t0l-ns", &timing->t0l_ns); in sun50i_a100_ledc_parse_timing()
293 device_property_read_u32(dev, "allwinner,t1h-ns", &timing->t1h_ns); in sun50i_a100_ledc_parse_timing()
294 device_property_read_u32(dev, "allwinner,t1l-ns", &timing->t1l_ns); in sun50i_a100_ledc_parse_timing()
295 device_property_read_u32(dev, "allwinner,treset-ns", &timing->treset_ns); in sun50i_a100_ledc_parse_timing()
302 const struct sun50i_a100_ledc_timing *timing = &priv->timing; in sun50i_a100_ledc_set_timing() local
311 control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing->t1h_ns / cycle_ns) | in sun50i_a100_ledc_set_timing()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.c178 struct dw_mipi_dsi_dphy_timing *timing) in dw_mipi_dsi_phy_get_timing() argument
187 timing->clk_lp2hs = 23; in dw_mipi_dsi_phy_get_timing()
188 timing->clk_hs2lp = 38; in dw_mipi_dsi_phy_get_timing()
189 timing->data_lp2hs = 15; in dw_mipi_dsi_phy_get_timing()
190 timing->data_hs2lp = 9; in dw_mipi_dsi_phy_get_timing()
194 timing->clk_lp2hs = 37; in dw_mipi_dsi_phy_get_timing()
195 timing->clk_hs2lp = 135; in dw_mipi_dsi_phy_get_timing()
196 timing->data_lp2hs = 50; in dw_mipi_dsi_phy_get_timing()
197 timing->data_hs2lp = 3; in dw_mipi_dsi_phy_get_timing()
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,v-tc.txt4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-jsl-phy.c171 const struct ipu6_isys_csi2_timing *timing, in ipu6_isys_csi2_set_timing() argument
187 writel(timing->ctermen, reg); in ipu6_isys_csi2_set_timing()
191 writel(timing->csettle, reg); in ipu6_isys_csi2_set_timing()
196 writel(timing->dtermen, reg); in ipu6_isys_csi2_set_timing()
200 writel(timing->dsettle, reg); in ipu6_isys_csi2_set_timing()
207 const struct ipu6_isys_csi2_timing *timing, in ipu6_isys_jsl_phy_set_power() argument
233 ipu6_isys_csi2_set_timing(isys, timing, port, nlanes); in ipu6_isys_jsl_phy_set_power()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h129 const struct dc_crtc_timing *timing,
203 const struct dc_crtc_timing *timing);
247 const struct dc_crtc_timing *timing);
259 const struct dc_crtc_timing *timing,
274 const struct dc_crtc_timing *timing);
292 bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);

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