| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy.c | 30 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
37 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
48 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
49 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
52 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
74 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
78 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
80 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
83 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
88 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
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| H A D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
210 struct emc_timing *timing) in emc_set_timing() argument
221 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, in emc_set_timing()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
[all …]
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_vid.c | 46 struct dpu_hw_intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
48 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
75 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
76 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
77 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
78 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
79 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
80 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
81 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
82 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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| /linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 38 struct gbe_timing_info timing; member
411 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
417 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
419 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
427 timing->pll_m = 4; in gbefb_setup_flatpanel()
428 timing->pll_n = 1; in gbefb_setup_flatpanel()
429 timing->pll_p = 0; in gbefb_setup_flatpanel()
456 struct gbe_timing_info *timing) in compute_gbe_timing() argument
504 if (timing) { in compute_gbe_timing()
505 timing->width = var->xres; in compute_gbe_timing()
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| /linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
83 timing->h_border_right - in optc201_validate_timing()
84 timing->h_border_left); in optc201_validate_timing()
86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && in optc201_validate_timing()
88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc201_validate_timing()
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
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| /linux/drivers/memory/tegra/ |
| H A D | tegra124-emc.c | 577 struct emc_timing *timing = NULL; in tegra124_emc_find_timing() local
582 timing = &emc->timings[i]; in tegra124_emc_find_timing()
587 if (!timing) { in tegra124_emc_find_timing()
592 return timing; in tegra124_emc_find_timing()
598 struct emc_timing *timing = tegra124_emc_find_timing(emc, rate); in tegra124_emc_prepare_timing_change() local
606 if (!timing) in tegra124_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra124_emc_prepare_timing_change()
611 else if (timing->emc_mode_1 & 0x1) in tegra124_emc_prepare_timing_change()
643 if (!(timing->emc_bgbias_ctl0 & in tegra124_emc_prepare_timing_change()
663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra124_emc_prepare_timing_change()
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| H A D | tegra30-emc.c | 440 struct emc_timing *timing = NULL; in emc_find_timing() local
445 timing = &emc->timings[i]; in emc_find_timing()
450 if (!timing) { in emc_find_timing()
455 return timing; in emc_find_timing()
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
525 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change() local
538 if (!timing || emc->bad_state) in emc_prepare_timing_change()
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| /linux/drivers/media/i2c/ |
| H A D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
184 init[0x06 * 2 - 1] = timing->hdelay & 0xff; in bt819_init()
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| /linux/drivers/leds/ |
| H A D | leds-expresswire.c | 19 usleep_range(props->timing.poweroff_us, props->timing.poweroff_us * 2); in expresswire_power_off()
26 udelay(props->timing.detect_delay_us); in expresswire_enable()
28 udelay(props->timing.detect_us); in expresswire_enable()
36 udelay(props->timing.data_start_us); in expresswire_start()
43 udelay(props->timing.end_of_data_low_us); in expresswire_end()
45 udelay(props->timing.end_of_data_high_us); in expresswire_end()
53 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
55 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
58 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
60 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator_v.c | 243 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
245 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
279 tmp = timing->h_total - in dce110_timing_generator_v_program_blanking()
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| H A D | dce110_timing_generator.c | 67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
256 const struct dc_crtc_timing *timing) in program_horz_count_by_2() argument
267 if (timing->flags.HORZ_COUNT_BY_TWO) in program_horz_count_by_2()
602 const struct dc_crtc_timing *timing) in dce110_timing_generator_program_blanking() argument
604 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_program_blanking()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 217 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height || in dcn32_is_center_timing()
218 pipe->stream->timing.v_addressable != pipe->stream->src.height) { in dcn32_is_center_timing()
223 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height && in dcn32_is_center_timing()
224 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) { in dcn32_is_center_timing()
265 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
278 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
430 struct dc_crtc_timing *timing = NULL; in get_frame_rate_at_max_stretch_100hz() local
444 timing = &fpo_candidate_stream->timing; in get_frame_rate_at_max_stretch_100hz()
445 if (timing == NULL) in get_frame_rate_at_max_stretch_100hz()
450 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1; in get_frame_rate_at_max_stretch_100hz()
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| /linux/drivers/ata/ |
| H A D | pata_triflex.c | 76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
106 timing = 0x0808;break; in triflex_load_timing()
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| H A D | pata_sis.c | 341 u16 timing; in sis_old_set_dmamode() local
346 pci_read_config_word(pdev, drive_pci, &timing); in sis_old_set_dmamode()
351 timing &= ~0x870F; in sis_old_set_dmamode()
352 timing |= mwdma_bits[speed]; in sis_old_set_dmamode()
356 timing &= ~0x6000; in sis_old_set_dmamode()
357 timing |= udma_bits[speed]; in sis_old_set_dmamode()
359 pci_write_config_word(pdev, drive_pci, timing); in sis_old_set_dmamode()
380 u16 timing; in sis_66_set_dmamode() local
386 pci_read_config_word(pdev, drive_pci, &timing); in sis_66_set_dmamode()
391 timing &= ~0x870F; in sis_66_set_dmamode()
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| H A D | pata_cs5530.c | 76 u32 tuning, timing = 0; in cs5530_set_dmamode() local
84 timing = 0x00921250;break; in cs5530_set_dmamode()
86 timing = 0x00911140;break; in cs5530_set_dmamode()
88 timing = 0x00911030;break; in cs5530_set_dmamode()
90 timing = 0x00077771;break; in cs5530_set_dmamode()
92 timing = 0x00012121;break; in cs5530_set_dmamode()
94 timing = 0x00002020;break; in cs5530_set_dmamode()
99 timing |= (tuning & 0x80000000UL); in cs5530_set_dmamode()
101 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
103 if (timing & 0x00100000) in cs5530_set_dmamode()
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| H A D | pata_cmd640.c | 54 struct cmd640_reg *timing = ap->private_data; in cmd640_set_piomode() local
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover; in cmd640_set_piomode()
134 struct cmd640_reg *timing = ap->private_data; in cmd640_qc_issue() local
136 if (ap->port_no != 0 && adev->devno != timing->last) { in cmd640_qc_issue()
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); in cmd640_qc_issue()
138 timing->last = adev->devno; in cmd640_qc_issue()
154 struct cmd640_reg *timing; in cmd640_port_start() local
156 timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); in cmd640_port_start()
157 if (timing == NULL) in cmd640_port_start()
159 timing->last = -1; /* Force a load */ in cmd640_port_start()
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| /linux/drivers/gpu/drm/amd/display/modules/freesync/ |
| H A D | freesync.c | 119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
130 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
144 return stream->timing.v_total; in mod_freesync_calc_v_total_from_refresh()
150 if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
156 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
157 stream->timing.h_total), 1000000); in mod_freesync_calc_v_total_from_refresh()
158 } else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
164 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
165 stream->timing.h_total) + (1000000 - 1), 1000000); in mod_freesync_calc_v_total_from_refresh()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_timing_generator.c | 103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
129 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
430 const struct dc_crtc_timing *timing) in dce120_timing_generator_program_blanking() argument
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dsi.c | 249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig() local
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
252 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
253 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
254 timing->da_hs_prepare; in mtk_dsi_phy_timconfig()
255 timing->da_hs_trail = timing->da_hs_prepare + 1; in mtk_dsi_phy_timconfig()
257 timing->ta_go = 4 * timing->lpx - 2; in mtk_dsi_phy_timconfig()
258 timing->ta_sure = timing->lpx + 2; in mtk_dsi_phy_timconfig()
259 timing->ta_get = 4 * timing->lpx; in mtk_dsi_phy_timconfig()
260 timing->da_hs_exit = 2 * timing->lpx + 1; in mtk_dsi_phy_timconfig()
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