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Searched refs:timer_of_base (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/clocksource/
H A Dtimer-npcm7xx.c61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
88 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
98 writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); in npcm7xx_timer_periodic()
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
103 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
114 writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0); in npcm7xx_clockevent_set_next_event()
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H A Dtimer-sun4i.c87 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_shutdown()
96 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_oneshot()
97 sun4i_clkevt_time_start(timer_of_base(to), 0, false); in sun4i_clkevt_set_oneshot()
106 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_periodic()
107 sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to)); in sun4i_clkevt_set_periodic()
108 sun4i_clkevt_time_start(timer_of_base(to), 0, true); in sun4i_clkevt_set_periodic()
118 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_next_event()
119 sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS); in sun4i_clkevt_next_event()
120 sun4i_clkevt_time_start(timer_of_base(to), 0, false); in sun4i_clkevt_next_event()
135 sun4i_timer_clear_interrupt(timer_of_base(to)); in sun4i_timer_interrupt()
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H A Dtimer-mediatek.c56 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
143 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_stop()
144 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + in mtk_gpt_clkevt_time_stop()
151 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer)); in mtk_gpt_clkevt_time_setup()
160 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); in mtk_gpt_clkevt_time_start()
162 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_start()
173 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_start()
212 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); in mtk_gpt_interrupt()
222 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_setup()
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H A Dtimer-sprd.c84 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_next_event()
85 sprd_timer_update_counter(timer_of_base(to), cycles); in sprd_timer_set_next_event()
86 sprd_timer_enable(timer_of_base(to), 0); in sprd_timer_set_next_event()
95 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_periodic()
96 sprd_timer_update_counter(timer_of_base(to), timer_of_period(to)); in sprd_timer_set_periodic()
97 sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE); in sprd_timer_set_periodic()
106 sprd_timer_disable(timer_of_base(to)); in sprd_timer_shutdown()
115 sprd_timer_clear_interrupt(timer_of_base(to)); in sprd_timer_interrupt()
118 sprd_timer_disable(timer_of_base(to)); in sprd_timer_interrupt()
152 sprd_timer_enable_interrupt(timer_of_base(&to)); in sprd_timer_init()
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H A Drenesas-ostm.c48 if (readb(timer_of_base(to) + OSTM_TE) & TE) { in ostm_timer_stop()
49 writeb(TT, timer_of_base(to) + OSTM_TT); in ostm_timer_stop()
56 while (readb(timer_of_base(to) + OSTM_TE) & TE) in ostm_timer_stop()
65 writel(0, timer_of_base(to) + OSTM_CMP); in ostm_init_clksrc()
66 writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL); in ostm_init_clksrc()
67 writeb(TS, timer_of_base(to) + OSTM_TS); in ostm_init_clksrc()
69 return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT, in ostm_init_clksrc()
81 system_clock = timer_of_base(to) + OSTM_CNT; in ostm_init_sched_clock()
92 writel(delta, timer_of_base(to) + OSTM_CMP); in ostm_clock_event_next()
93 writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL); in ostm_clock_event_next()
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H A Dtimer-milbeaut.c55 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_start()
76 u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_stop()
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_stop()
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); in mlb_evt_timer_register_count()
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); in mlb_config_clock_source()
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); in mlb_config_clock_source()
133 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
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H A Dtimer-msc313e.c95 msc313e_timer_stop(timer_of_base(timer)); in msc313e_timer_clkevt_shutdown()
104 msc313e_timer_stop(timer_of_base(timer)); in msc313e_timer_clkevt_set_oneshot()
105 msc313e_timer_start(timer_of_base(timer), false); in msc313e_timer_clkevt_set_oneshot()
114 msc313e_timer_stop(timer_of_base(timer)); in msc313e_timer_clkevt_set_periodic()
115 msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer)); in msc313e_timer_clkevt_set_periodic()
116 msc313e_timer_start(timer_of_base(timer), true); in msc313e_timer_clkevt_set_periodic()
125 msc313e_timer_stop(timer_of_base(timer)); in msc313e_timer_clkevt_next_event()
126 msc313e_timer_setup(timer_of_base(timer), evt); in msc313e_timer_clkevt_next_event()
127 msc313e_timer_start(timer_of_base(timer), false); in msc313e_timer_clkevt_next_event()
187 writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); in msc313e_clkevt_init()
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H A Dtimer-stm32.c101 writel_relaxed(0, timer_of_base(to) + TIM_DIER); in stm32_clock_event_disable()
114 writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); in stm32_timer_start()
132 next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; in stm32_clock_event_set_next_event()
133 writel_relaxed(next, timer_of_base(to) + TIM_CCR1); in stm32_clock_event_set_next_event()
134 now = readl_relaxed(timer_of_base(to) + TIM_CNT); in stm32_clock_event_set_next_event()
139 writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); in stm32_clock_event_set_next_event()
167 writel_relaxed(0, timer_of_base(to) + TIM_SR); in stm32_clock_event_handler()
192 writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
194 width = readl_relaxed(timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
222 writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); in stm32_timer_set_prescaler()
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H A Dtimer-gx6605s.c28 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_interrupt()
40 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_oneshot()
55 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_next_event()
69 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_shutdown()
98 base = timer_of_base(&to) + CLKSRC_OFFSET; in gx6605s_sched_clock_read()
151 gx6605s_clkevt_init(timer_of_base(&to)); in gx6605s_timer_init()
153 return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET); in gx6605s_timer_init()
H A Dtimer-loongson1-pwm.c47 writel(period, timer_of_base(to) + PWM_LRC); in ls1x_pwmtimer_set_period()
48 writel(period, timer_of_base(to) + PWM_HRC); in ls1x_pwmtimer_set_period()
53 writel(0, timer_of_base(to) + PWM_CNTR); in ls1x_pwmtimer_clear()
58 writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL); in ls1x_pwmtimer_start()
63 writel(0, timer_of_base(to) + PWM_CTRL); in ls1x_pwmtimer_stop()
70 val = readl(timer_of_base(to) + PWM_CTRL); in ls1x_pwmtimer_irq_ack()
72 writel(val, timer_of_base(to) + PWM_CTRL); in ls1x_pwmtimer_irq_ack()
228 ls1x_clocksource.reg_base = timer_of_base(to); in ls1x_pwm_clocksource_init()
H A Dtimer-rda.c71 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_shutdown()
80 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_oneshot()
90 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_periodic()
94 rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); in rda_ostimer_set_state_periodic()
109 rda_ostimer_start(timer_of_base(to), false, evt); in rda_ostimer_set_next_event()
121 timer_of_base(to) + RDA_TIMER_IRQ_CLR); in rda_ostimer_interrupt()
158 void __iomem *base = timer_of_base(&rda_ostimer_of); in rda_hwtimer_read()
H A Dtimer-mediatek-cpux.c39 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_readl()
40 return readl(timer_of_base(to) + CPUX_CON_REG); in mtk_cpux_readl()
45 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_writel()
46 writel(val, timer_of_base(to) + CPUX_CON_REG); in mtk_cpux_writel()
H A Dtimer-imx-sysctr.c37 void __iomem *base = timer_of_base(to); in sysctr_timer_enable()
56 void __iomem *base = timer_of_base(to); in sysctr_read_counter()
72 void __iomem *base = timer_of_base(to); in sysctr_set_next_event()
160 base = timer_of_base(&to_sysctr); in __sysctr_timer_init()
H A Dtimer-of.h48 static inline void __iomem *timer_of_base(struct timer_of *to) in timer_of_base() function
H A Dtimer-imx-tpm.c205 timer_base = timer_of_base(&to_tpm); in tpm_timer_init()