56 #define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)
143 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_stop()
144 	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +  in mtk_gpt_clkevt_time_stop()
151 	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_clkevt_time_setup()
160 	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_clkevt_time_start()
162 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
173 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
212 	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_interrupt()
222 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
225 	       timer_of_base(to) + GPT_CLK_REG(timer));  in mtk_gpt_setup()
227 	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_setup()
230 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
238 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
241 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_enable_irq()
243 	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
245 	       timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
260 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_suspend()
267 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_suspend()
325 	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),  in mtk_gpt_init()
328 	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);  in mtk_gpt_init()