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Searched refs:tile (Results 1 – 25 of 104) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
[all …]
H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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H A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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H A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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H A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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H A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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H A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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H A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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H A Dnv49.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
H A Dnv47.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
H A Dnv1a.c31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
H A Dnv4e.c32 .tile.regions = 12,
33 .tile.init = nv46_fb_tile_init,
34 .tile.fini = nv20_fb_tile_fini,
35 .tile.prog = nv44_fb_tile_prog,
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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H A Dnv40.c173 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv40_gr_tile() argument
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
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/linux/drivers/gpu/drm/xe/
H A Dxe_mem_pool.c57 return pool->bo->tile; in pool_to_tile()
72 struct xe_tile *tile = pool->bo->tile; in pool_shadow_init() local
73 struct xe_device *xe = tile_to_xe(tile); in pool_shadow_init()
88 shadow = xe_managed_bo_create_pin_map(xe, tile, in pool_shadow_init()
90 XE_BO_FLAG_VRAM_IF_DGFX(tile) | in pool_shadow_init()
117 struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size, in xe_mem_pool_init() argument
120 struct xe_device *xe = tile_to_xe(tile); in xe_mem_pool_init()
126 xe_tile_assert(tile, size > guard); in xe_mem_pool_init()
133 bo = xe_managed_bo_create_pin_map(xe, tile, size, in xe_mem_pool_init()
134 XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_mem_pool_init()
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H A Dxe_pt.c62 static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, in __xe_pt_empty_pte() argument
65 struct xe_device *xe = tile_to_xe(tile); in __xe_pt_empty_pte()
67 u8 id = tile->id; in __xe_pt_empty_pte()
104 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, in xe_pt_create() argument
122 bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_pt_create()
131 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K, in xe_pt_create()
144 xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL); in xe_pt_create()
164 void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm, in xe_pt_populate_empty() argument
178 empty = __xe_pt_empty_pte(tile, vm, pt->level); in xe_pt_populate_empty()
291 struct xe_tile *tile; member
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H A Dxe_bo_evict.c162 struct xe_tile *tile; in xe_bo_evict_all() local
181 for_each_tile(tile, xe, id) in xe_bo_evict_all()
182 xe_tile_migrate_wait(tile); in xe_bo_evict_all()
201 struct xe_tile *tile; in xe_bo_restore_and_map_ggtt() local
204 for_each_tile(tile, xe_bo_device(bo), id) { in xe_bo_restore_and_map_ggtt()
205 if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile))) in xe_bo_restore_and_map_ggtt()
208 xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo); in xe_bo_restore_and_map_ggtt()
245 struct xe_tile *tile; in xe_bo_restore_late() local
252 for_each_tile(tile, xe, id) in xe_bo_restore_late()
253 xe_tile_migrate_wait(tile); in xe_bo_restore_late()
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H A Dxe_vram.c143 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, in tile_vram_size() argument
146 struct xe_device *xe = tile_to_xe(tile); in tile_vram_size()
147 struct xe_gt *gt = tile->primary_gt; in tile_vram_size()
157 for_each_if(t->id < tile->id) in tile_vram_size()
160 *tile_size = xe_tile_sriov_vf_lmem(tile); in tile_vram_size()
172 reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); in tile_vram_size()
184 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); in tile_vram_size()
196 struct xe_tile *tile; in vram_fini() local
201 for_each_tile(tile, xe, id) { in vram_fini()
202 tile->mem.vram->mapping = NULL; in vram_fini()
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H A Dxe_bo.h33 #define XE_BO_FLAG_VRAM_IF_DGFX(tile) (IS_DGFX(tile_to_xe(tile)) ? \ argument
34 XE_BO_FLAG_VRAM((tile)->mem.vram) : \
69 #define XE_BO_FLAG_GGTTx(tile) \ argument
70 (XE_BO_FLAG_GGTT0 << (tile)->id)
122 struct xe_tile *tile, struct dma_resv *resv,
127 struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
133 struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
137 struct xe_bo *xe_bo_create_pin_map_novm(struct xe_device *xe, struct xe_tile *tile,
140 struct xe_bo *xe_bo_create_pin_range_novm(struct xe_device *xe, struct xe_tile *tile,
144 xe_bo_create_pin_map_at_novm(struct xe_device *xe, struct xe_tile *tile,
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H A Dxe_gsc.c131 struct xe_tile *tile = gt_to_tile(gt); in query_compatibility_version() local
139 bo = xe_bo_create_pin_map_novm(xe, tile, GSC_VER_PKT_SZ * 2, in query_compatibility_version()
265 struct xe_tile *tile = gt_to_tile(gt); in gsc_upload_and_init() local
269 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691)) { in gsc_upload_and_init()
270 fw_ref = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL); in gsc_upload_and_init()
277 xe_gt_mcr_multicast_write(tile->primary_gt, in gsc_upload_and_init()
284 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691)) in gsc_upload_and_init()
285 xe_force_wake_put(gt_to_fw(tile->primary_gt), fw_ref); in gsc_upload_and_init()
403 struct xe_tile *tile = gt_to_tile(gt); in xe_gsc_init() local
411 if (tile->media_gt && (gt != tile->media_gt)) { in xe_gsc_init()
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/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c126 struct ipu_image_tile tile[MAX_TILES]; member
663 in_tile = &in->tile[tile_idx]; in fill_tile_column()
664 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; in fill_tile_column()
695 in_tile = &in->tile[tile_idx]; in fill_tile_row()
696 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; in fill_tile_row()
856 struct ipu_image_tile *tile; in calc_tile_dimensions() local
861 tile = &image->tile[ctx->out_tile_map[i]]; in calc_tile_dimensions()
863 tile = &image->tile[i]; in calc_tile_dimensions()
865 tile->size = ((tile->height * image->fmt->bpp) >> 3) * in calc_tile_dimensions()
866 tile->width; in calc_tile_dimensions()
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_migrate.c76 struct xe_device *xe = tile_to_xe(m->tile); in test_copy()
83 struct xe_bo *remote = xe_bo_create_locked(xe, m->tile, NULL, in test_copy()
189 struct xe_tile *tile = m->tile; in xe_migrate_sanity_test() local
190 struct xe_device *xe = tile_to_xe(tile); in xe_migrate_sanity_test()
197 u8 id = tile->id; in xe_migrate_sanity_test()
205 big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M, in xe_migrate_sanity_test()
207 XE_BO_FLAG_VRAM_IF_DGFX(tile), in xe_migrate_sanity_test()
214 pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE, in xe_migrate_sanity_test()
216 XE_BO_FLAG_VRAM_IF_DGFX(tile), in xe_migrate_sanity_test()
224 tiny = xe_bo_create_pin_map(xe, tile, m->q->vm, in xe_migrate_sanity_test()
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