Lines Matching refs:tile
32 struct xe_tile *tile;
35 for_each_remote_tile(tile, xe, id)
36 tile->mmio.regs = NULL;
40 * On multi-tile devices, partition the BAR space for MMIO on each tile,
42 * tile_mmio_size contains both the tile's 4MB register space, as well as
60 struct xe_tile *tile;
65 * Nothing to be done as tile 0 has already been setup earlier with the
71 /* Possibly override number of tile based on configuration register */
78 * Although the per-tile mmio regs are not yet initialized, this
79 * is fine as it's going to the root tile's mmio, that's
92 * tile count. Re-calculate it to only include the GTs
93 * that belong to the remaining tile(s).
103 for_each_remote_tile(tile, xe, id)
104 xe_mmio_init(&tile->mmio, tile, xe->mmio.regs + id * tile_mmio_size, SZ_4M);
133 * The first 16MB of the BAR, belong to the root tile, and include:
143 /* Setup first tile; other tiles (if present) will be setup later. */
153 * @tile: The tile to which the MMIO region belongs
159 void xe_mmio_init(struct xe_mmio *mmio, struct xe_tile *tile, void __iomem *ptr, u32 size)
161 xe_tile_assert(tile, size <= XE_REG_ADDR_MAX);
165 mmio->tile = tile;
173 if (!XE_DEVICE_WA(mmio->tile->xe, 15015404425))
213 if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))
215 mmio->tile->primary_gt, reg, val);
227 if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))
229 mmio->tile->primary_gt, reg);
300 xe_tile_assert(mmio->tile, reg_udw.addr == reg.addr + 0x4);
313 drm_WARN(&mmio->tile->xe->drm, retries == 0,