| /linux/drivers/soc/qcom/ |
| H A D | qcom_gsbi.c | 114 struct regmap *tcsr; member
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
198 regmap_update_bits(gsbi->tcsr, in gsbi_probe()
201 regmap_update_bits(gsbi->tcsr, in gsbi_probe()
|
| /linux/include/clocksource/ |
| H A D | timer-xilinx.h | 59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
71 u32 tlr, u32 tcsr);
|
| /linux/drivers/pwm/ |
| H A D | pwm-xilinx.c | 34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
|
| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_tai.c | 242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
|
| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qusb2.c | 462 struct regmap *tcsr; member
831 if (qphy->tcsr) { in qusb2_phy_init()
832 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1039 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1041 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1043 qphy->tcsr = NULL; in qusb2_phy_probe()
|
| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-sdx65.dtsi | 317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
389 compatible = "qcom,tcsr-mutex";
394 tcsr: syscon@1fcb000 { label
395 compatible = "qcom,sdx65-tcsr", "syscon";
|
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | eliza.dtsi | 9 #include <dt-bindings/clock/qcom,eliza-tcsr.h>
322 qcom,dload-mode = <&tcsr 0x1a000>;
1796 <&tcsr TCSR_UFS_CLKREF_EN>;
1956 compatible = "qcom,tcsr-mutex";
1961 tcsr: clock-controller@1fbf000 {
1962 compatible = "qcom,eliza-tcsr", "syscon";
2093 clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
2107 <&tcsr TCSR_USB3_CLKREF_EN>,
859 tcsr: clock-controller@1fbf000 { global() label
|
| H A D | glymur.dtsi | 9 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
380 qcom,dload-mode = <&tcsr 0x4000>;
2306 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2321 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2336 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
2349 <&tcsr TCSR_USB3_0_CLKREF_EN>,
2376 <&tcsr TCSR_USB3_1_CLKREF_EN>,
2408 <&tcsr TCSR_EDP_CLKREF_EN>;
2514 <&tcsr TCSR_USB4_1_CLKREF_EN>,
2934 <&tcsr TCSR_PCIE_2_CLKREF_E
3679 tcsr: clock-controller@1fd5000 { global() label
[all...] |
| H A D | hamoa.dtsi | 12 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
325 qcom,dload-mode = <&tcsr 0x19000>;
2871 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2942 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2955 <&tcsr TCSR_USB4_1_CLKREF_EN>,
3013 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
3026 <&tcsr TCSR_USB4_2_CLKREF_EN>,
3436 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
3577 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
3598 qcom,4ln-config-sel = <&tcsr
4032 tcsr: clock-controller@1fc0000 { global() label
[all...] |
| H A D | milos.dtsi | 11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
375 qcom,dload-mode = <&tcsr 0x19000>;
1164 <&tcsr TCSR_UFS_CLKREF_EN>;
1190 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1318 compatible = "qcom,tcsr-mutex";
1324 tcsr: clock-controller@1fc0000 {
1325 compatible = "qcom,milos-tcsr", "syscon";
1292 tcsr: clock-controller@1fc0000 { global() label
|
| H A D | agatti.dtsi | 458 compatible = "qcom,tcsr-mutex";
464 compatible = "qcom,qcm2290-tcsr", "syscon";
824 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
|
| H A D | monaco.dtsi | 636 qcom,dload-mode = <&tcsr 0x13000>;
2760 compatible = "qcom,tcsr-mutex";
2765 tcsr: syscon@1fc0000 {
2766 compatible = "qcom,qcs8300-tcsr", "syscon";
2761 tcsr: syscon@1fc0000 { global() label
|
| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-stm.c | 632 coresight_simple_reg32(tcsr, STMTCSR),
|