xref: /linux/arch/arm64/boot/dts/qcom/purwa.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6/* X1P42100 is heavily based on hamoa, with some meaningful differences */
7#include "hamoa.dtsi"
8
9/delete-node/ &bwmon_cluster0;
10/delete-node/ &cluster_pd2;
11/delete-node/ &cpu_map_cluster2;
12/delete-node/ &cpu8;
13/delete-node/ &cpu9;
14/delete-node/ &cpu10;
15/delete-node/ &cpu11;
16/delete-node/ &cpu_pd8;
17/delete-node/ &cpu_pd9;
18/delete-node/ &cpu_pd10;
19/delete-node/ &cpu_pd11;
20/delete-node/ &gpu_opp_table;
21/delete-node/ &gpu_speed_bin;
22/delete-node/ &pcie3_phy;
23/delete-node/ &thermal_zones;
24
25&gcc {
26	compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
27};
28
29&gmu {
30	compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
31};
32
33&gpu {
34	compatible = "qcom,adreno-43030c00", "qcom,adreno";
35
36	nvmem-cells = <&gpu_speed_bin>;
37	nvmem-cell-names = "speed_bin";
38
39	gpu_opp_table: opp-table {
40		compatible = "operating-points-v2-adreno", "operating-points-v2";
41
42		opp-1400000000 {
43			opp-hz = /bits/ 64 <1400000000>;
44			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
45			opp-peak-kBps = <16500000>;
46			qcom,opp-acd-level = <0xa8295ffd>;
47			opp-supported-hw = <0x3>;
48		};
49
50		opp-1250000000 {
51			opp-hz = /bits/ 64 <1250000000>;
52			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
53			opp-peak-kBps = <16500000>;
54			qcom,opp-acd-level = <0x882a5ffd>;
55			opp-supported-hw = <0x7>;
56		};
57
58		opp-1107000000 {
59			opp-hz = /bits/ 64 <1107000000>;
60			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
61			opp-peak-kBps = <16500000>;
62			qcom,opp-acd-level = <0x882a5ffd>;
63			opp-supported-hw = <0xf>;
64		};
65
66		opp-1014000000 {
67			opp-hz = /bits/ 64 <1014000000>;
68			opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
69			opp-peak-kBps = <14398438>;
70			qcom,opp-acd-level = <0xa82a5ffd>;
71			opp-supported-hw = <0xf>;
72		};
73
74		opp-940000000 {
75			opp-hz = /bits/ 64 <940000000>;
76			opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
77			opp-peak-kBps = <14398438>;
78			qcom,opp-acd-level = <0xa82a5ffd>;
79			opp-supported-hw = <0xf>;
80		};
81
82		opp-825000000 {
83			opp-hz = /bits/ 64 <825000000>;
84			opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
85			opp-peak-kBps = <12449219>;
86			qcom,opp-acd-level = <0x882b5ffd>;
87			opp-supported-hw = <0xf>;
88		};
89
90		opp-720000000 {
91			opp-hz = /bits/ 64 <720000000>;
92			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
93			opp-peak-kBps = <10687500>;
94			qcom,opp-acd-level = <0xa82c5ffd>;
95			opp-supported-hw = <0xf>;
96		};
97
98		opp-666000000-0 {
99			opp-hz = /bits/ 64 <666000000>;
100			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
101			opp-peak-kBps = <8171875>;
102			qcom,opp-acd-level = <0xa82d5ffd>;
103			opp-supported-hw = <0xf>;
104		};
105
106		/* Only applicable for SKUs which has 666Mhz as Fmax */
107		opp-666000000-1 {
108			opp-hz = /bits/ 64 <666000000>;
109			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
110			opp-peak-kBps = <16500000>;
111			qcom,opp-acd-level = <0xa82d5ffd>;
112			opp-supported-hw = <0x10>;
113		};
114
115		opp-550000000 {
116			opp-hz = /bits/ 64 <550000000>;
117			opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
118			opp-peak-kBps = <6074219>;
119			qcom,opp-acd-level = <0x882e5ffd>;
120			opp-supported-hw = <0x1f>;
121		};
122
123		opp-380000000 {
124			opp-hz = /bits/ 64 <380000000>;
125			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
126			opp-peak-kBps = <3000000>;
127			qcom,opp-acd-level = <0xc82f5ffd>;
128			opp-supported-hw = <0x1f>;
129		};
130
131		opp-280000000 {
132			opp-hz = /bits/ 64 <280000000>;
133			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
134			opp-peak-kBps = <2136719>;
135			qcom,opp-acd-level = <0xc82f5ffd>;
136			opp-supported-hw = <0x1f>;
137		};
138	};
139
140};
141
142&gpucc {
143	compatible = "qcom,x1p42100-gpucc";
144};
145
146/* PCIe3 has half the lanes compared to X1E80100 */
147&pcie3 {
148	num-lanes = <4>;
149};
150
151&pcie6a_phy {
152	compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
153};
154
155&qfprom {
156	gpu_speed_bin: gpu-speed-bin@119 {
157		reg = <0x119 0x2>;
158		bits = <7 9>;
159	};
160};
161
162&soc {
163	/* The PCIe3 PHY on X1P42100 uses a different IP block */
164	pcie3_phy: phy@1bd4000 {
165		compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
166		reg = <0x0 0x01bd4000 0x0 0x2000>,
167		      <0x0 0x01bd6000 0x0 0x2000>;
168
169		clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
170			 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
171			 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
172			 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
173			 <&gcc GCC_PCIE_3_PIPE_CLK>,
174			 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
175		clock-names = "aux",
176			      "cfg_ahb",
177			      "ref",
178			      "rchng",
179			      "pipe",
180			      "pipediv2";
181
182		resets = <&gcc GCC_PCIE_3_PHY_BCR>,
183			 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
184		reset-names = "phy",
185			      "phy_nocsr";
186
187		assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
188		assigned-clock-rates = <100000000>;
189
190		power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
191
192		#clock-cells = <0>;
193		clock-output-names = "pcie3_pipe_clk";
194
195		#phy-cells = <0>;
196
197		status = "disabled";
198	};
199};
200
201/* While physically present, this controller is left unconfigured and unused */
202&tsens3 {
203	status = "disabled";
204};
205
206/ {
207	thermal-zones {
208		aoss0-thermal {
209			thermal-sensors = <&tsens0 0>;
210
211			trips {
212				trip-point0 {
213					temperature = <90000>;
214					hysteresis = <2000>;
215					type = "hot";
216				};
217
218				trip-point1 {
219					temperature = <115000>;
220					hysteresis = <1000>;
221					type = "critical";
222				};
223			};
224		};
225
226		cpu0-0-top-thermal {
227			thermal-sensors = <&tsens0 1>;
228
229			trips {
230				trip-point0 {
231					temperature = <115000>;
232					hysteresis = <1000>;
233					type = "critical";
234				};
235			};
236		};
237
238		cpu0-0-btm-thermal {
239			thermal-sensors = <&tsens0 2>;
240
241			trips {
242				trip-point0 {
243					temperature = <115000>;
244					hysteresis = <1000>;
245					type = "critical";
246				};
247			};
248		};
249
250		cpu0-1-top-thermal {
251			thermal-sensors = <&tsens0 3>;
252
253			trips {
254				trip-point0 {
255					temperature = <115000>;
256					hysteresis = <1000>;
257					type = "critical";
258				};
259			};
260		};
261
262		cpu0-1-btm-thermal {
263			thermal-sensors = <&tsens0 4>;
264
265			trips {
266				trip-point0 {
267					temperature = <115000>;
268					hysteresis = <1000>;
269					type = "critical";
270				};
271			};
272		};
273
274		cpu0-2-top-thermal {
275			thermal-sensors = <&tsens0 5>;
276
277			trips {
278				trip-point0 {
279					temperature = <115000>;
280					hysteresis = <1000>;
281					type = "critical";
282				};
283			};
284		};
285
286		cpu0-2-btm-thermal {
287			thermal-sensors = <&tsens0 6>;
288
289			trips {
290				trip-point0 {
291					temperature = <115000>;
292					hysteresis = <1000>;
293					type = "critical";
294				};
295			};
296		};
297
298		cpu0-3-top-thermal {
299			thermal-sensors = <&tsens0 7>;
300
301			trips {
302				trip-point0 {
303					temperature = <115000>;
304					hysteresis = <1000>;
305					type = "critical";
306				};
307			};
308		};
309
310		cpu0-3-btm-thermal {
311			thermal-sensors = <&tsens0 8>;
312
313			trips {
314				trip-point0 {
315					temperature = <115000>;
316					hysteresis = <1000>;
317					type = "critical";
318				};
319			};
320		};
321
322		cpuss0-top-thermal {
323			thermal-sensors = <&tsens0 9>;
324
325			trips {
326				trip-point0 {
327					temperature = <115000>;
328					hysteresis = <1000>;
329					type = "critical";
330				};
331			};
332		};
333
334		cpuss0-btm-thermal {
335			thermal-sensors = <&tsens0 10>;
336
337			trips {
338				trip-point0 {
339					temperature = <115000>;
340					hysteresis = <1000>;
341					type = "critical";
342				};
343			};
344		};
345
346		mem-thermal {
347			thermal-sensors = <&tsens0 11>;
348
349			trips {
350				trip-point0 {
351					temperature = <90000>;
352					hysteresis = <2000>;
353					type = "hot";
354				};
355
356				trip-point1 {
357					temperature = <115000>;
358					hysteresis = <0>;
359					type = "critical";
360				};
361			};
362		};
363
364		video-thermal {
365			thermal-sensors = <&tsens0 12>;
366
367			trips {
368				trip-point0 {
369					temperature = <90000>;
370					hysteresis = <2000>;
371					type = "hot";
372				};
373
374				trip-point1 {
375					temperature = <115000>;
376					hysteresis = <1000>;
377					type = "critical";
378				};
379			};
380		};
381
382		aoss1-thermal {
383			thermal-sensors = <&tsens1 0>;
384
385			trips {
386				trip-point0 {
387					temperature = <90000>;
388					hysteresis = <2000>;
389					type = "hot";
390				};
391
392				trip-point1 {
393					temperature = <115000>;
394					hysteresis = <1000>;
395					type = "critical";
396				};
397			};
398		};
399
400		cpu1-0-top-thermal {
401			thermal-sensors = <&tsens1 1>;
402
403			trips {
404				trip-point0 {
405					temperature = <115000>;
406					hysteresis = <1000>;
407					type = "critical";
408				};
409			};
410		};
411
412		cpu1-0-btm-thermal {
413			thermal-sensors = <&tsens1 2>;
414
415			trips {
416				trip-point0 {
417					temperature = <115000>;
418					hysteresis = <1000>;
419					type = "critical";
420				};
421			};
422		};
423
424		cpu1-1-top-thermal {
425			thermal-sensors = <&tsens1 3>;
426
427			trips {
428				trip-point0 {
429					temperature = <115000>;
430					hysteresis = <1000>;
431					type = "critical";
432				};
433			};
434		};
435
436		cpu1-1-btm-thermal {
437			thermal-sensors = <&tsens1 4>;
438
439			trips {
440				trip-point0 {
441					temperature = <115000>;
442					hysteresis = <1000>;
443					type = "critical";
444				};
445			};
446		};
447
448		cpu1-2-top-thermal {
449			thermal-sensors = <&tsens1 5>;
450
451			trips {
452				trip-point0 {
453					temperature = <115000>;
454					hysteresis = <1000>;
455					type = "critical";
456				};
457			};
458		};
459
460		cpu1-2-btm-thermal {
461			thermal-sensors = <&tsens1 6>;
462
463			trips {
464				trip-point0 {
465					temperature = <115000>;
466					hysteresis = <1000>;
467					type = "critical";
468				};
469			};
470		};
471
472		cpu1-3-top-thermal {
473			thermal-sensors = <&tsens1 7>;
474
475			trips {
476				trip-point0 {
477					temperature = <115000>;
478					hysteresis = <1000>;
479					type = "critical";
480				};
481			};
482		};
483
484		cpu1-3-btm-thermal {
485			thermal-sensors = <&tsens1 8>;
486
487			trips {
488				trip-point0 {
489					temperature = <115000>;
490					hysteresis = <1000>;
491					type = "critical";
492				};
493			};
494		};
495
496		cpuss1-top-thermal {
497			thermal-sensors = <&tsens1 9>;
498
499			trips {
500				trip-point0 {
501					temperature = <115000>;
502					hysteresis = <1000>;
503					type = "critical";
504				};
505			};
506		};
507
508		cpuss1-btm-thermal {
509			thermal-sensors = <&tsens1 10>;
510
511			trips {
512				trip-point0 {
513					temperature = <115000>;
514					hysteresis = <1000>;
515					type = "critical";
516				};
517			};
518		};
519
520		aoss2-thermal {
521			thermal-sensors = <&tsens2 0>;
522
523			trips {
524				trip-point0 {
525					temperature = <90000>;
526					hysteresis = <2000>;
527					type = "hot";
528				};
529
530				trip-point1 {
531					temperature = <115000>;
532					hysteresis = <1000>;
533					type = "critical";
534				};
535			};
536		};
537
538		nsp0-thermal {
539			thermal-sensors = <&tsens2 1>;
540
541			trips {
542				trip-point0 {
543					temperature = <90000>;
544					hysteresis = <2000>;
545					type = "hot";
546				};
547
548				trip-point1 {
549					temperature = <115000>;
550					hysteresis = <1000>;
551					type = "critical";
552				};
553			};
554		};
555
556		nsp1-thermal {
557			thermal-sensors = <&tsens2 2>;
558
559			trips {
560				trip-point0 {
561					temperature = <90000>;
562					hysteresis = <2000>;
563					type = "hot";
564				};
565
566				trip-point1 {
567					temperature = <115000>;
568					hysteresis = <1000>;
569					type = "critical";
570				};
571			};
572		};
573
574		nsp2-thermal {
575			thermal-sensors = <&tsens2 3>;
576
577			trips {
578				trip-point0 {
579					temperature = <90000>;
580					hysteresis = <2000>;
581					type = "hot";
582				};
583
584				trip-point1 {
585					temperature = <115000>;
586					hysteresis = <1000>;
587					type = "critical";
588				};
589			};
590		};
591
592		nsp3-thermal {
593			thermal-sensors = <&tsens2 4>;
594
595			trips {
596				trip-point0 {
597					temperature = <90000>;
598					hysteresis = <2000>;
599					type = "hot";
600				};
601
602				trip-point1 {
603					temperature = <115000>;
604					hysteresis = <1000>;
605					type = "critical";
606				};
607			};
608		};
609
610		gpuss-0-thermal {
611			polling-delay-passive = <200>;
612
613			thermal-sensors = <&tsens2 5>;
614
615			cooling-maps {
616				map0 {
617					trip = <&gpuss0_alert0>;
618					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
619				};
620			};
621
622			trips {
623				gpuss0_alert0: trip-point0 {
624					temperature = <95000>;
625					hysteresis = <1000>;
626					type = "passive";
627				};
628
629				trip-point1 {
630					temperature = <115000>;
631					hysteresis = <1000>;
632					type = "critical";
633				};
634			};
635		};
636
637		gpuss-1-thermal {
638			polling-delay-passive = <200>;
639
640			thermal-sensors = <&tsens2 6>;
641
642			cooling-maps {
643				map0 {
644					trip = <&gpuss1_alert0>;
645					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
646				};
647			};
648
649			trips {
650				gpuss1_alert0: trip-point0 {
651					temperature = <95000>;
652					hysteresis = <1000>;
653					type = "passive";
654				};
655
656				trip-point1 {
657					temperature = <115000>;
658					hysteresis = <1000>;
659					type = "critical";
660				};
661			};
662		};
663
664		gpuss-2-thermal {
665			polling-delay-passive = <200>;
666
667			thermal-sensors = <&tsens2 7>;
668
669			cooling-maps {
670				map0 {
671					trip = <&gpuss2_alert0>;
672					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
673				};
674			};
675
676			trips {
677				gpuss2_alert0: trip-point0 {
678					temperature = <95000>;
679					hysteresis = <1000>;
680					type = "passive";
681				};
682
683				trip-point1 {
684					temperature = <115000>;
685					hysteresis = <1000>;
686					type = "critical";
687				};
688			};
689		};
690
691		gpuss-3-thermal {
692			polling-delay-passive = <200>;
693
694			thermal-sensors = <&tsens2 8>;
695
696			cooling-maps {
697				map0 {
698					trip = <&gpuss3_alert0>;
699					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
700				};
701			};
702
703			trips {
704				gpuss3_alert0: trip-point0 {
705					temperature = <95000>;
706					hysteresis = <1000>;
707					type = "passive";
708				};
709
710				trip-point1 {
711					temperature = <115000>;
712					hysteresis = <1000>;
713					type = "critical";
714				};
715			};
716		};
717
718		camera0-thermal {
719			thermal-sensors = <&tsens2 9>;
720
721			trips {
722				trip-point0 {
723					temperature = <90000>;
724					hysteresis = <2000>;
725					type = "hot";
726				};
727
728				trip-point1 {
729					temperature = <115000>;
730					hysteresis = <1000>;
731					type = "critical";
732				};
733			};
734		};
735
736		camera1-thermal {
737			thermal-sensors = <&tsens2 10>;
738
739			trips {
740				trip-point0 {
741					temperature = <90000>;
742					hysteresis = <2000>;
743					type = "hot";
744				};
745
746				trip-point1 {
747					temperature = <115000>;
748					hysteresis = <1000>;
749					type = "critical";
750				};
751			};
752		};
753	};
754};
755