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Searched refs:syscfg (Results 1 – 25 of 54) sorted by relevance

123

/linux/drivers/bus/
H A Dvexpress-config.c54 struct vexpress_syscfg *syscfg; member
161 struct vexpress_syscfg *syscfg = func->syscfg; in vexpress_syscfg_exec() local
169 command = readl(syscfg->base + SYS_CFGCTRL); in vexpress_syscfg_exec()
181 dev_dbg(syscfg->dev, "func %p, command %x, data %x\n", in vexpress_syscfg_exec()
183 writel(*data, syscfg->base + SYS_CFGDATA); in vexpress_syscfg_exec()
184 writel(0, syscfg->base + SYS_CFGSTAT); in vexpress_syscfg_exec()
185 writel(command, syscfg->base + SYS_CFGCTRL); in vexpress_syscfg_exec()
201 status = readl(syscfg->base + SYS_CFGSTAT); in vexpress_syscfg_exec()
212 *data = readl(syscfg->base + SYS_CFGDATA); in vexpress_syscfg_exec()
213 dev_dbg(syscfg->dev, "func %p, read data %x\n", func, *data); in vexpress_syscfg_exec()
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c43 struct regmap *syscfg; member
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
123 ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT, in keembay_emmc_phy_power()
132 ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK, in keembay_emmc_phy_power()
140 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
173 ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT, in keembay_emmc_phy_power()
218 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK, in keembay_emmc_phy_power_on()
226 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK, in keembay_emmc_phy_power_on()
[all …]
H A Dphy-intel-lgm-emmc.c47 struct regmap *syscfg; member
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
111 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK, in intel_emmc_phy_power()
119 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK, in intel_emmc_phy_power()
140 ret = regmap_read_poll_timeout(priv->syscfg, in intel_emmc_phy_power()
193 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK, in intel_emmc_phy_power_on()
201 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA, in intel_emmc_phy_power_on()
209 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, in intel_emmc_phy_power_on()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi54 st,syscfg = <&syscfg_core 0x8e0>;
121 st,syscfg = <&syscfg_sbc_reg>;
140 irq-syscfg {
141 compatible = "st,stih407-irq-syscfg";
142 st,syscfg = <&syscfg_core>;
152 st,syscfg = <&syscfg_core 0x100 0xf4>;
160 st,syscfg = <&syscfg_core>;
173 st,syscfg = <0x114 0x818 0xe0 0xec>;
188 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
202 st,syscfg = <0x11c 0x820>;
[all …]
H A Dstm32h743.dtsi408 syscfg: syscon@58000400 { label
409 compatible = "st,stm32-syscfg", "syscon";
531 st,syscfg = <&pwrcfg 0x00 0x100>;
541 st,syscfg = <&pwrcfg>;
579 st,syscon = <&syscfg 0x4>;
590 st,syscfg = <&syscfg 0x8>;
H A Dstih418.dtsi35 st,syscfg = <&syscfg_core 0xf8 0xf4>;
44 st,syscfg = <&syscfg_core 0xfc 0xf4>;
/linux/drivers/watchdog/
H A Dst_lpc_wdt.c44 const struct st_wdog_syscfg *syscfg; member
67 if (st_wdog->syscfg->reset_type_reg) in st_wdog_setup()
69 st_wdog->syscfg->reset_type_reg, in st_wdog_setup()
70 st_wdog->syscfg->reset_type_mask, in st_wdog_setup()
75 st_wdog->syscfg->enable_reg, in st_wdog_setup()
76 st_wdog->syscfg->enable_mask, in st_wdog_setup()
77 enable ? 0 : st_wdog->syscfg->enable_mask); in st_wdog_setup()
174 st_wdog->syscfg = (struct st_wdog_syscfg *)device_get_match_data(dev); in st_wdog_probe()
/linux/Documentation/devicetree/bindings/power/reset/
H A Dst-reset.txt5 - st,syscfg: should be a phandle of the syscfg node.
10 st,syscfg = <&syscfg_sbc_reg>;
/linux/drivers/cpufreq/
H A Dsti-cpufreq.c52 struct regmap *syscfg; member
70 ret = regmap_read(ddata.syscfg, major_offset, &socid); in sti_cpufreq_fetch_major()
240 ddata.syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in sti_cpufreq_fetch_syscon_registers()
241 if (IS_ERR(ddata.syscfg)) { in sti_cpufreq_fetch_syscon_registers()
243 return PTR_ERR(ddata.syscfg); in sti_cpufreq_fetch_syscon_registers()
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt9 - st,syscfg : Should be a phandle of the system configuration register group
29 - st,syscfg : Offset of the parent configuration register.
50 st,syscfg = <&syscfg_core>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
92 st,syscfg = <0x11c 0x820>;
H A Dphy-miphy365x.txt9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
43 st,syscfg = <&syscfg_rear 0x824 0x828>;
57 reg-names = "sata", "pcie", "syscfg";
/linux/drivers/mtd/nand/onenand/
H A Donenand_omap2.c149 u32 syscfg; in omap2_onenand_wait() local
188 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
189 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) { in omap2_onenand_wait()
190 syscfg |= ONENAND_SYS_CFG1_IOBE; in omap2_onenand_wait()
191 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
193 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
233 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
234 syscfg &= ~ONENAND_SYS_CFG1_IOBE; in omap2_onenand_wait()
235 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
/linux/drivers/irqchip/
H A Dirq-st.c38 unsigned int syscfg; member
134 return regmap_update_bits(ddata->regmap, ddata->syscfg, in st_irq_syscfg_enable()
147 ddata->syscfg = (unsigned int) device_get_match_data(&pdev->dev); in st_irq_syscfg_probe()
164 return regmap_update_bits(ddata->regmap, ddata->syscfg, in st_irq_syscfg_resume()
/linux/Documentation/devicetree/bindings/sound/
H A Dst,sti-asoc-card.txt18 - st,syscfg: phandle to boot-device system configuration registers
57 st,syscfg = <&syscfg_core>;
69 st,syscfg = <&syscfg_core>;
80 st,syscfg = <&syscfg_core>;
91 st,syscfg = <&syscfg_core>;
105 - st,syscfg: phandle to boot-device system configuration registers.
/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
37 st,syscfg = <&syscfg_core>;
/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-st.txt9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
47 reg-names = "reg-glue", "syscfg-reg";
48 st,syscfg = <&syscfg_core>;
/linux/tools/testing/selftests/arm64/fp/
H A DMakefile12 vec-syscfg \
41 $(OUTPUT)/vec-syscfg: vec-syscfg.c $(OUTPUT)/rdvl.o
H A D.gitignore12 vec-syscfg
/linux/Documentation/devicetree/bindings/mtd/
H A Dst-fsm.txt11 - st,syscfg : Phandle to boot-device system configuration registers
21 st,syscfg = <&syscfg_rear>;
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst-rproc.txt20 - st,syscfg System configuration register which holds the boot vector
40 st,syscfg = <&syscfg_core 0x228>;
/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32h7-rcc.txt26 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
38 st,syscfg = <&pwrcfg>;
/linux/drivers/hwtracing/coresight/
H A DMakefile27 coresight-sysfs.o coresight-syscfg.o coresight-config.o \
29 coresight-syscfg-configfs.o coresight-trace-id.o
/linux/drivers/reset/sti/
H A DMakefile2 obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt34 - st,syscfg : Should be a phandle of the syscfg node.
85 st,syscfg = <&syscfg_sbc>;
/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi.h70 void __iomem *syscfg; member

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