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Searched refs:snb_pcode_write (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Dintel_pcode.h16 #define snb_pcode_write(uncore, mbox, val) \ macro
H A Dintel_pcode.c272 err = snb_pcode_write(uncore, mbox, val); in snb_pcode_write_p()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_pcode.h21 snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val) in snb_pcode_write() function
/linux/drivers/gpu/drm/i915/display/
H A Dhsw_ips.c38 snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, in hsw_ips_enable()
72 snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0)); in hsw_ips_disable()
H A Dintel_cdclk.c849 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
877 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
1180 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
2126 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
H A Dintel_display_power.c1238 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) in hsw_write_dcomp()
H A Dintel_hdcp.c388 ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); in intel_hdcp_load_keys()
H A Dskl_watermark.c164 ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, in skl_sagv_enable()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_llc.c143 snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, in gen6_update_ring_freq()
H A Dintel_rc6.c284 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_rc6_enable()