| /linux/drivers/clk/imx/ |
| H A D | clk-pll14xx.c | 111 int sdiv, int kdiv, unsigned long prate) in pll14xx_calc_rate() argument
119 do_div(fout, pdiv << sdiv); in pll14xx_calc_rate()
124 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, in pll1443x_calc_kdiv() argument
130 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
139 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
164 t->sdiv = tt->sdiv; in imx_pll14xx_calc_settings()
178 sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
181 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); in imx_pll14xx_calc_settings()
182 rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); in imx_pll14xx_calc_settings()
185 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); in imx_pll14xx_calc_settings()
[all …]
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| H A D | clk.h | 61 unsigned int sdiv; member
268 .sdiv = (_s), \
276 .sdiv = (_s), \
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| /linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 137 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
143 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; in samsung_pll2126_recalc_rate()
146 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
170 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
176 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; in samsung_pll3000_recalc_rate()
179 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
211 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
222 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; in samsung_pll35xx_recalc_rate()
225 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
270 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
[all …]
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| /linux/drivers/clk/st/ |
| H A D | clkgen-fsyn.c | 37 unsigned long sdiv; member
60 struct clkgen_field sdiv[QUADFS_MAX_CHAN]; member
115 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
151 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
525 u32 sdiv; member
555 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); in quadfs_fsynth_program_rate()
624 unsigned long s = (1 << fs->sdiv); in clk_fs660c32_dig_get_rate()
664 fs_tmp.sdiv = si; in clk_fs660c32_get_pe()
674 fs->sdiv = si; in clk_fs660c32_get_pe()
719 fs_tmp.sdiv = fs->sdiv; in clk_fs660c32_dig_get_params()
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| /linux/arch/mips/cavium-octeon/ |
| H A D | csrc-octeon.c | 27 static u64 sdiv; variable
47 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ in octeon_setup_delays()
48 f = (0x8000000000000000ull / sdiv) * 2; in octeon_setup_delays()
54 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ in octeon_setup_delays()
55 f = (0x8000000000000000ull / sdiv) * 2; in octeon_setup_delays()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gk104.c | 122 u32 sdiv = (sctl & 0x0000003f) + 2; in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
155 sdiv = 1; in read_clk()
158 sdiv = 0; in read_clk()
167 sdiv = 1; in read_clk()
169 sdiv = 0; in read_clk()
173 sdiv = 0; in read_clk()
178 if (sdiv) in read_clk()
179 sdiv = ((sctl & 0x00003f00) >> 8) + 2; in read_clk()
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| H A D | gt215.c | 64 u32 sctl, sdiv, sclk; in read_clk() local
100 sdiv = ((sctl & 0x003f0000) >> 16) + 2; in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
209 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
215 sdiv++; in gt215_clk_info()
216 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
223 if (sdiv > 4) { in gt215_clk_info()
224 info->clk = (((sdiv - 2) << 16) | 0x00003100); in gt215_clk_info()
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| H A D | gf100.c | 102 u32 sclk, sctl, sdiv = 2; in read_div() local
122 sdiv = (sctl & 0x3f) + 2; in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
145 sdiv = ((sctl & 0x00003f00) >> 8) + 2; in read_clk()
148 sdiv = ((sctl & 0x0000003f) >> 0) + 2; in read_clk()
152 return (sclk * 2) / sdiv; in read_clk()
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| /linux/sound/soc/cirrus/ |
| H A D | ep93xx-i2s.c | 304 unsigned word_len, div, sdiv, lrdiv; in ep93xx_i2s_hw_params() local
338 sdiv = 4; in ep93xx_i2s_hw_params()
344 sdiv = 2; in ep93xx_i2s_hw_params()
347 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-hdptx.c | 1060 u32 mdiv, sdiv, n = 8; in rk_hdptx_phy_clk_pll_calc() local
1065 for (sdiv = 16; sdiv >= 1; sdiv--) { in rk_hdptx_phy_clk_pll_calc()
1066 if (sdiv % 2 && sdiv != 1) in rk_hdptx_phy_clk_pll_calc()
1069 fvco = fout * sdiv; in rk_hdptx_phy_clk_pll_calc()
1102 if (sdiv < 1) in rk_hdptx_phy_clk_pll_calc()
1110 cfg->pms_sdiv = sdiv - 1; in rk_hdptx_phy_clk_pll_calc()
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| /linux/drivers/clk/renesas/ |
| H A D | r9a09g077-cpg.c | 587 u8 pdiv, sdiv; in r9a09g077_cpg_pll3_clk_recalc_rate() local
598 sdiv = FIELD_GET(CPG_PLL3_VCO_CTR1_SDIV, ctr1); in r9a09g077_cpg_pll3_clk_recalc_rate()
600 rate = mul_u64_u32_shr(parent_rate, (mdiv << 16) + kdiv, 16 + sdiv); in r9a09g077_cpg_pll3_clk_recalc_rate()
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| /linux/arch/arm64/include/asm/ |
| H A D | insn.h | 400 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
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| /linux/arch/arm/ |
| H A D | Kconfig | 1150 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1156 and unsigned integers. Some v7 CPUs have support for the sdiv
1162 with the sdiv or udiv plus "bx lr" instructions when the CPU
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