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Searched refs:sclk_table (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
909 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
913 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
922 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
947 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1287 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1374 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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H A Dpolaris10_smumgr.c1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1098 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1100 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1111 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1136 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1498 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
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H A Dfiji_smumgr.c1022 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1038 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1042 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1044 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1051 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1076 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1532 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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H A Dtonga_smumgr.c710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
726 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
731 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
770 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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H A Diceland_smumgr.c980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
H A Dci_smumgr.c486 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
494 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1668 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1671 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1704 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.c2512 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2515 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3247 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3249 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3256 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3262 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3264 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3420 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3435 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3438 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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H A Dci_dpm.h69 struct ci_single_dpm_table sclk_table; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c2704 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2707 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
H A Dvega20_hwmgr.c1480 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1484 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()