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Searched refs:reg_layout (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/soundwire/
H A Dqcom.c193 const unsigned int *reg_layout; member
232 const unsigned int *reg_layout; member
258 .reg_layout = swrm_v1_3_reg_layout,
265 .reg_layout = swrm_v1_3_reg_layout,
273 .reg_layout = swrm_v1_3_reg_layout,
300 .reg_layout = swrm_v2_0_reg_layout,
327 .reg_layout = swrm_v3_0_reg_layout,
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
436 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
461 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
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/linux/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c202 enum clk_reg_layout reg_layout; member
272 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
284 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mstp_clock_endisable()
304 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
307 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mstp_clock_endisable()
345 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
347 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mstp_clock_is_enabled()
386 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
732 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) in cpg_mssr_reset()
865 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_reset_controller_register()
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H A Dr8a779f0-cpg-mssr.c237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
H A Dr8a779a0-cpg-mssr.c317 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
/linux/drivers/tty/serial/8250/
H A D8250_dfl.c55 u64 fifo_len, clk_freq, reg_layout; in dfl_uart_get_params() local
86 ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, &reg_layout); in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
91 reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); in dfl_uart_get_params()
/linux/drivers/dma/
H A Dhisi_dma.c164 enum hisi_dma_reg_layout reg_layout; member
369 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_mask_irq()
385 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_unmask_irq()
638 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_init_hw_qp()
803 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_set_mode()
813 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) { in hisi_dma_init_hw()
851 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
862 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
928 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_create_debugfs()
952 enum hisi_dma_reg_layout reg_layout; in hisi_dma_probe() local
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/linux/sound/soc/codecs/
H A Dlpass-wsa-macro.c406 const struct wsa_reg_layout *reg_layout; member
1180 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1182 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1184 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1220 wsa->reg_layout->rx_intx_2_sel_mask); in wsa_macro_set_mix_interpolator_rate()
1614 (comp * wsa->reg_layout->compander1_reg_offset); in wsa_macro_config_compander()
1660 u16 softclip_clk_reg = wsa->reg_layout->softclip0_reg_base + in wsa_macro_enable_softclip_clk()
1661 (path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_enable_softclip_clk()
1706 (softclip_path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_config_softclip()
2726 wsa->reg_layout = &wsa_codec_v2_1; in wsa_macro_probe()
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/linux/drivers/clk/samsung/
H A Dclk-cpu.c681 cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; in exynos_register_cpu_clock()