193 	const unsigned int *reg_layout;  member
232 	const unsigned int *reg_layout;  member
258 	.reg_layout = swrm_v1_3_reg_layout,
265 	.reg_layout = swrm_v1_3_reg_layout,
273 	.reg_layout = swrm_v1_3_reg_layout,
300 	.reg_layout = swrm_v2_0_reg_layout,
327 	.reg_layout = swrm_v3_0_reg_layout,
410 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in swrm_wait_for_rd_fifo_avail()
436 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in swrm_wait_for_wr_fifo_avail()
461 	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);  in swrm_wait_for_wr_fifo_done()
467 			ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);  in swrm_wait_for_wr_fifo_done()
505 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);  in qcom_swrm_cmd_fifo_wr_cmd()
545 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);  in qcom_swrm_cmd_fifo_rd_cmd()
553 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],  in qcom_swrm_cmd_fifo_rd_cmd()
565 						ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],  in qcom_swrm_cmd_fifo_rd_cmd()
725 	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],  in qcom_swrm_irq_handler()
765 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
770 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
778 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
786 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
795 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
808 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
818 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
832 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
849 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_irq_handler()
851 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],  in qcom_swrm_irq_handler()
866 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],  in swrm_wait_for_frame_gen_enabled()
898 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],  in qcom_swrm_init()
935 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_init()
940 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_init()
1023 	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];  in qcom_swrm_port_params()
1036 	int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];  in qcom_swrm_transport_params()
1052 		offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];  in qcom_swrm_transport_params()
1062 		offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];  in qcom_swrm_transport_params()
1072 		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];  in qcom_swrm_transport_params()
1082 	offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];  in qcom_swrm_transport_params()
1097 		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];  in qcom_swrm_transport_params()
1113 	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];  in qcom_swrm_port_enable()
1549 	ctrl->reg_layout = data->reg_layout;
1746 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1752 					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1754 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1780 					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1782 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],