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Searched refs:readl_relaxed (Results 1 – 25 of 412) sorted by relevance

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/linux/arch/arm/mach-mv78xx0/
H A Dirq.c31 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); in mv78xx0_legacy_handle_irq()
32 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); in mv78xx0_legacy_handle_irq()
38 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); in mv78xx0_legacy_handle_irq()
39 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); in mv78xx0_legacy_handle_irq()
45 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); in mv78xx0_legacy_handle_irq()
46 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); in mv78xx0_legacy_handle_irq()
/linux/drivers/clk/berlin/
H A Dberlin2-avpll.c118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
145 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
163 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate()
220 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_is_enabled()
231 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
243 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
258 reg = readl_relaxed(ch->base + VCO_CTRL30); in berlin2_avpll_channel_recalc_rate()
267 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); in berlin2_avpll_channel_recalc_rate()
273 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); in berlin2_avpll_channel_recalc_rate()
[all …]
H A Dberlin2-div.c74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
92 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_enable()
111 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_disable()
129 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_set_parent()
138 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_set_parent()
161 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_get_parent()
164 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_get_parent()
186 divsw = readl_relaxed(div->base + map->div_switch_offs) & in berlin2_div_recalc_rate()
188 div3sw = readl_relaxed(div->base + map->div3_switch_offs) & in berlin2_div_recalc_rate()
200 reg = readl_relaxed(div->base + map->div_select_offs); in berlin2_div_recalc_rate()
/linux/drivers/irqchip/
H A Dirq-sa11x0.c38 reg = readl_relaxed(iobase + ICMR); in sa1100_mask_irq()
47 reg = readl_relaxed(iobase + ICMR); in sa1100_unmask_irq()
93 st->icmr = readl_relaxed(iobase + ICMR); in sa1100irq_suspend()
94 st->iclr = readl_relaxed(iobase + ICLR); in sa1100irq_suspend()
95 st->iccr = readl_relaxed(iobase + ICCR); in sa1100irq_suspend()
139 icip = readl_relaxed(iobase + ICIP); in sa1100_handle_irq()
140 icmr = readl_relaxed(iobase + ICMR); in sa1100_handle_irq()
H A Dirq-mmp.c76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
110 r = readl_relaxed(mmp_icu2_base + (hwirq << 2)); in icu_mask_irq()
115 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_irq()
129 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_unmask_irq()
134 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); in icu_unmask_irq()
169 mask = readl_relaxed(data->reg_mask); in icu_mux_irq_demux()
171 status = readl_relaxed(data->reg_status) & ~mask; in icu_mux_irq_demux()
229 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); in mmp_handle_irq()
[all …]
/linux/drivers/clk/imx/
H A Dclk-frac-pll.c57 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) in clk_wait_ack()
70 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_prepare()
82 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_unprepare()
92 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_is_prepared()
104 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_recalc_rate()
106 val = readl_relaxed(pll->base + PLL_CFG1); in clk_pll_recalc_rate()
174 val = readl_relaxed(pll->base + PLL_CFG1); in clk_pll_set_rate()
179 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_set_rate()
184 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_set_rate()
191 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_set_rate()
H A Dclk-pllv3.c63 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
78 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
93 val = readl_relaxed(pll->base); in clk_pllv3_unprepare()
105 if (readl_relaxed(pll->base) & BM_PLL_LOCK) in clk_pllv3_is_prepared()
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
143 val = readl_relaxed(pll->base); in clk_pllv3_set_rate()
164 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
200 val = readl_relaxed(pll->base); in clk_pllv3_sys_set_rate()
221 u32 mfn = readl_relaxed(pll->base + pll->num_offset); in clk_pllv3_av_recalc_rate()
222 u32 mfd = readl_relaxed(pll->base + pll->denom_offset); in clk_pllv3_av_recalc_rate()
[all …]
/linux/drivers/watchdog/
H A Domap_wdt.c76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
83 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
94 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
98 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
108 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
112 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
123 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
127 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
150 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
154 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
[all …]
/linux/arch/arm/mach-hisi/
H A Dhotplug.c104 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
114 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
200 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
205 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
210 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
216 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
237 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
244 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
/linux/drivers/rtc/
H A Drtc-rtd119x.c59 val = readl_relaxed(data->base + RTD_RTCCR); in rtd119x_rtc_reset()
72 val = readl_relaxed(data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
91 tm->tm_sec = (readl_relaxed(data->base + RTD_RTCSEC) & RTD_RTCSEC_RTCSEC_MASK) >> 1; in rtd119x_rtc_read_time()
92 tm->tm_min = readl_relaxed(data->base + RTD_RTCMIN) & RTD_RTCMIN_RTCMIN_MASK; in rtd119x_rtc_read_time()
93 tm->tm_hour = readl_relaxed(data->base + RTD_RTCHR) & RTD_RTCHR_RTCHR_MASK; in rtd119x_rtc_read_time()
94 day = readl_relaxed(data->base + RTD_RTCDATE1) & RTD_RTCDATE1_RTCDATE1_MASK; in rtd119x_rtc_read_time()
95 day |= (readl_relaxed(data->base + RTD_RTCDATE2) & RTD_RTCDATE2_RTCDATE2_MASK) << 8; in rtd119x_rtc_read_time()
96 sec = (readl_relaxed(data->base + RTD_RTCSEC) & RTD_RTCSEC_RTCSEC_MASK) >> 1; in rtd119x_rtc_read_time()
193 val = readl_relaxed(data->base + RTD_RTCACR); in rtd119x_rtc_probe()
H A Drtc-sa1100.c53 rtsr = readl_relaxed(info->rtsr); in sa1100_rtc_interrupt()
98 rtsr = readl_relaxed(info->rtsr); in sa1100_rtc_alarm_irq_enable()
112 rtc_time64_to_tm(readl_relaxed(info->rcnr), tm); in sa1100_rtc_read_time()
130 rtsr = readl_relaxed(info->rtsr); in sa1100_rtc_read_alarm()
141 writel_relaxed(readl_relaxed(info->rtsr) & in sa1100_rtc_set_alarm()
145 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
147 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
157 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr)); in sa1100_rtc_proc()
158 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr)); in sa1100_rtc_proc()
194 if (readl_relaxed(info->rttr) == 0) { in sa1100_rtc_init()
H A Drtc-digicolor.c69 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_read()
70 time1 = readl_relaxed(rtc->regs + DC_RTC_TIME); in dc_rtc_read()
73 time2 = readl_relaxed(rtc->regs + DC_RTC_TIME); in dc_rtc_read()
119 alarm_reg = readl_relaxed(rtc->regs + DC_RTC_ALARM); in dc_rtc_read_alarm()
120 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_read_alarm()
128 alarm->enabled = readl_relaxed(rtc->regs + DC_RTC_INTENABLE); in dc_rtc_read_alarm()
141 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_set_alarm()
/linux/arch/arm/mach-dove/
H A Dirq.c47 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); in dove_legacy_handle_irq()
48 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); in dove_legacy_handle_irq()
54 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); in dove_legacy_handle_irq()
55 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); in dove_legacy_handle_irq()
/linux/drivers/thermal/
H A Ddove_thermal.c48 reg = readl_relaxed(priv->control); in dove_init_sensor()
64 reg = readl_relaxed(priv->control); in dove_init_sensor()
69 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
75 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
93 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); in dove_get_temp()
102 reg = readl_relaxed(priv->sensor); in dove_get_temp()
/linux/drivers/clk/ti/
H A Dfapll.c81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
102 u32 v = readl_relaxed(fd->base); in ti_fapll_clear_bypass()
116 while ((v = readl_relaxed(fd->base))) { in ti_fapll_wait_lock()
134 u32 v = readl_relaxed(fd->base); in ti_fapll_enable()
146 u32 v = readl_relaxed(fd->base); in ti_fapll_disable()
155 u32 v = readl_relaxed(fd->base); in ti_fapll_is_enabled()
173 v = readl_relaxed(fd->base); in ti_fapll_recalc_rate()
256 v = readl_relaxed(fd->base); in ti_fapll_set_rate()
281 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_enable()
[all …]
/linux/drivers/edac/
H A Dal_mc_edac.c83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ce()
88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); in handle_ce()
89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); in handle_ce()
90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); in handle_ce()
91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); in handle_ce()
92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); in handle_ce()
128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ue()
133 eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0); in handle_ue()
134 eccuaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR1); in handle_ue()
135 eccusyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND0); in handle_ue()
[all …]
/linux/drivers/soc/dove/
H A Dpmu.c55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
70 val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_assert()
84 val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_deassert()
157 val &= readl_relaxed(pmu_base + PMU_ISO); in pmu_domain_power_off()
164 val &= readl_relaxed(pmc_base + PMC_SW_RST); in pmu_domain_power_off()
169 val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask; in pmu_domain_power_off()
189 val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR); in pmu_domain_power_on()
195 val |= readl_relaxed(pmc_base + PMC_SW_RST); in pmu_domain_power_on()
202 val |= readl_relaxed(pmu_base + PMU_ISO); in pmu_domain_power_on()
214 unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR); in __pmu_domain_register()
[all …]
/linux/drivers/gpio/
H A Dgpio-omap.c97 u32 val = readl_relaxed(reg); in omap_gpio_rmw()
295 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
297 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
299 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
301 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
330 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); in omap_toggle_gpio_edge_triggering()
345 l = readl_relaxed(reg); in omap_set_gpio_triggering()
363 l = readl_relaxed(reg); in omap_set_gpio_triggering()
380 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); in omap_enable_gpio_module()
387 ctrl = readl_relaxed(reg); in omap_enable_gpio_module()
[all …]
/linux/arch/arm/mach-omap2/
H A Domap4-common.c118 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_interconnect_sync()
119 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_interconnect_sync()
188 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); in gic_dist_disabled()
193 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
194 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); in gic_timer_retrigger()
195 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c60 return readl_relaxed(reg); in nvidia_smmu_read_reg()
116 val |= readl_relaxed(reg); in nvidia_smmu_tlb_sync()
143 val = readl_relaxed(reg); in nvidia_smmu_reset()
157 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); in nvidia_smmu_global_fault_inst()
161 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); in nvidia_smmu_global_fault_inst()
162 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); in nvidia_smmu_global_fault_inst()
163 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); in nvidia_smmu_global_fault_inst()
202 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); in nvidia_smmu_context_fault_bank()
206 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); in nvidia_smmu_context_fault_bank()
208 cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(idx)); in nvidia_smmu_context_fault_bank()
/linux/drivers/mmc/host/
H A Dsdhci-msm.c335 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
341 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
427 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
438 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
463 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
477 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
482 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
491 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
641 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
669 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.c84 std_err_main = readl_relaxed(l3_targ_stderr); in l3_handle_target()
91 readl_relaxed(l3_targ_slvofslsb)); in l3_handle_target()
113 masterid = (readl_relaxed(l3_targ_mstaddr) & in l3_handle_target()
124 op_code = readl_relaxed(l3_targ_hdr) & 0x7; in l3_handle_target()
126 m_req_info = readl_relaxed(l3_targ_info) & 0xF; in l3_handle_target()
178 err_reg = readl_relaxed(base + flag_mux->offset + in l3_interrupt_handler()
205 mask_val = readl_relaxed(mask_reg); in l3_interrupt_handler()
322 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
328 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
/linux/drivers/clocksource/
H A Dtimer-imx-gpt.c98 tmp = readl_relaxed(imxtm->base + MXC_TCTL); in imx1_gpt_irq_disable()
111 tmp = readl_relaxed(imxtm->base + MXC_TCTL); in imx1_gpt_irq_enable()
140 return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; in mxc_read_sched_clock()
148 return readl_relaxed(sched_clock_reg); in imx_read_current_timer()
178 tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; in mx1_2_set_next_event()
182 return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? in mx1_2_set_next_event()
192 tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; in v2_set_next_event()
197 (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? in v2_set_next_event()
209 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_shutdown()
231 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_set_oneshot()
[all …]
/linux/drivers/soc/imx/
H A Dsoc-imx8m.c65 *socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); in imx8m_soc_uid()
67 *socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); in imx8m_soc_uid()
85 magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1); in imx8mq_soc_revision()
100 socuid[0] = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + IMX8MP_OCOTP_UID_OFFSET); in imx8mp_soc_uid()
102 socuid[0] |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + IMX8MP_OCOTP_UID_OFFSET); in imx8mp_soc_uid()
104 socuid[1] = readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH + 0x10); in imx8mp_soc_uid()
106 socuid[1] |= readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH); in imx8mp_soc_uid()
124 *socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); in imx8mm_soc_revision()
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled()
520 value = readl_relaxed(clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
560 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
570 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
582 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
592 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
633 val = readl_relaxed(clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
647 csi_src = readl_relaxed(clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
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