13fed0955SLad Prabhakar // SPDX-License-Identifier: GPL-2.0
23fed0955SLad Prabhakar /*
33fed0955SLad Prabhakar * Renesas RZ/G2L IRQC Driver
43fed0955SLad Prabhakar *
53fed0955SLad Prabhakar * Copyright (C) 2022 Renesas Electronics Corporation.
63fed0955SLad Prabhakar *
73fed0955SLad Prabhakar * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
83fed0955SLad Prabhakar */
93fed0955SLad Prabhakar
103fed0955SLad Prabhakar #include <linux/bitfield.h>
113fed0955SLad Prabhakar #include <linux/clk.h>
123fed0955SLad Prabhakar #include <linux/err.h>
133fed0955SLad Prabhakar #include <linux/io.h>
143fed0955SLad Prabhakar #include <linux/irqchip.h>
153fed0955SLad Prabhakar #include <linux/irqdomain.h>
163fed0955SLad Prabhakar #include <linux/of_address.h>
173fed0955SLad Prabhakar #include <linux/of_platform.h>
183fed0955SLad Prabhakar #include <linux/pm_runtime.h>
193fed0955SLad Prabhakar #include <linux/reset.h>
203fed0955SLad Prabhakar #include <linux/spinlock.h>
2174d2ef5fSClaudiu Beznea #include <linux/syscore_ops.h>
223fed0955SLad Prabhakar
233fed0955SLad Prabhakar #define IRQC_IRQ_START 1
243fed0955SLad Prabhakar #define IRQC_IRQ_COUNT 8
253fed0955SLad Prabhakar #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
263fed0955SLad Prabhakar #define IRQC_TINT_COUNT 32
273fed0955SLad Prabhakar #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
283fed0955SLad Prabhakar
293fed0955SLad Prabhakar #define ISCR 0x10
303fed0955SLad Prabhakar #define IITSR 0x14
313fed0955SLad Prabhakar #define TSCR 0x20
322eca4731SClaudiu Beznea #define TITSR(n) (0x24 + (n) * 4)
333fed0955SLad Prabhakar #define TITSR0_MAX_INT 16
343fed0955SLad Prabhakar #define TITSEL_WIDTH 0x2
353fed0955SLad Prabhakar #define TSSR(n) (0x30 + ((n) * 4))
363fed0955SLad Prabhakar #define TIEN BIT(7)
373fed0955SLad Prabhakar #define TSSEL_SHIFT(n) (8 * (n))
383fed0955SLad Prabhakar #define TSSEL_MASK GENMASK(7, 0)
393fed0955SLad Prabhakar #define IRQ_MASK 0x3
40d011c022SLad Prabhakar #define IMSK 0x10010
41d011c022SLad Prabhakar #define TMSK 0x10020
423fed0955SLad Prabhakar
433fed0955SLad Prabhakar #define TSSR_OFFSET(n) ((n) % 4)
443fed0955SLad Prabhakar #define TSSR_INDEX(n) ((n) / 4)
453fed0955SLad Prabhakar
463fed0955SLad Prabhakar #define TITSR_TITSEL_EDGE_RISING 0
473fed0955SLad Prabhakar #define TITSR_TITSEL_EDGE_FALLING 1
483fed0955SLad Prabhakar #define TITSR_TITSEL_LEVEL_HIGH 2
493fed0955SLad Prabhakar #define TITSR_TITSEL_LEVEL_LOW 3
503fed0955SLad Prabhakar
513fed0955SLad Prabhakar #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2))
523fed0955SLad Prabhakar #define IITSR_IITSEL_LEVEL_LOW 0
533fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_FALLING 1
543fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_RISING 2
553fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_BOTH 3
563fed0955SLad Prabhakar #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
573fed0955SLad Prabhakar
583fed0955SLad Prabhakar #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
593fed0955SLad Prabhakar #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
603fed0955SLad Prabhakar
61b94f4553SClaudiu Beznea /**
6274d2ef5fSClaudiu Beznea * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
6374d2ef5fSClaudiu Beznea * @iitsr: IITSR register
6474d2ef5fSClaudiu Beznea * @titsr: TITSR registers
6574d2ef5fSClaudiu Beznea */
6674d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache {
6774d2ef5fSClaudiu Beznea u32 iitsr;
6874d2ef5fSClaudiu Beznea u32 titsr[2];
6974d2ef5fSClaudiu Beznea };
7074d2ef5fSClaudiu Beznea
7174d2ef5fSClaudiu Beznea /**
72b94f4553SClaudiu Beznea * struct rzg2l_irqc_priv - IRQ controller private data structure
73b94f4553SClaudiu Beznea * @base: Controller's base address
74d011c022SLad Prabhakar * @irqchip: Pointer to struct irq_chip
75b94f4553SClaudiu Beznea * @fwspec: IRQ firmware specific data
76b94f4553SClaudiu Beznea * @lock: Lock to serialize access to hardware registers
7774d2ef5fSClaudiu Beznea * @cache: Registers cache for suspend/resume
78b94f4553SClaudiu Beznea */
7974d2ef5fSClaudiu Beznea static struct rzg2l_irqc_priv {
803fed0955SLad Prabhakar void __iomem *base;
81d011c022SLad Prabhakar const struct irq_chip *irqchip;
823fed0955SLad Prabhakar struct irq_fwspec fwspec[IRQC_NUM_IRQ];
833fed0955SLad Prabhakar raw_spinlock_t lock;
8474d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache cache;
8574d2ef5fSClaudiu Beznea } *rzg2l_irqc_data;
863fed0955SLad Prabhakar
irq_data_to_priv(struct irq_data * data)873fed0955SLad Prabhakar static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
883fed0955SLad Prabhakar {
893fed0955SLad Prabhakar return data->domain->host_data;
903fed0955SLad Prabhakar }
913fed0955SLad Prabhakar
rzg2l_clear_irq_int(struct rzg2l_irqc_priv * priv,unsigned int hwirq)92b4b5cd61SBiju Das static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
933fed0955SLad Prabhakar {
94b4b5cd61SBiju Das unsigned int hw_irq = hwirq - IRQC_IRQ_START;
953fed0955SLad Prabhakar u32 bit = BIT(hw_irq);
96ef88eefbSClaudiu Beznea u32 iitsr, iscr;
973fed0955SLad Prabhakar
98ef88eefbSClaudiu Beznea iscr = readl_relaxed(priv->base + ISCR);
99ef88eefbSClaudiu Beznea iitsr = readl_relaxed(priv->base + IITSR);
100ef88eefbSClaudiu Beznea
101ef88eefbSClaudiu Beznea /*
102ef88eefbSClaudiu Beznea * ISCR can only be cleared if the type is falling-edge, rising-edge or
103ef88eefbSClaudiu Beznea * falling/rising-edge.
104ef88eefbSClaudiu Beznea */
1059eec61dfSBiju Das if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) {
106ef88eefbSClaudiu Beznea writel_relaxed(iscr & ~bit, priv->base + ISCR);
1079eec61dfSBiju Das /*
1089eec61dfSBiju Das * Enforce that the posted write is flushed to prevent that the
1099eec61dfSBiju Das * just handled interrupt is raised again.
1109eec61dfSBiju Das */
1119eec61dfSBiju Das readl_relaxed(priv->base + ISCR);
1129eec61dfSBiju Das }
1133fed0955SLad Prabhakar }
1143fed0955SLad Prabhakar
rzg2l_clear_tint_int(struct rzg2l_irqc_priv * priv,unsigned int hwirq)1157cb6362cSBiju Das static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
1163fed0955SLad Prabhakar {
1177cb6362cSBiju Das u32 bit = BIT(hwirq - IRQC_TINT_START);
1183fed0955SLad Prabhakar u32 reg;
1193fed0955SLad Prabhakar
1203fed0955SLad Prabhakar reg = readl_relaxed(priv->base + TSCR);
1219eec61dfSBiju Das if (reg & bit) {
1223fed0955SLad Prabhakar writel_relaxed(reg & ~bit, priv->base + TSCR);
1239eec61dfSBiju Das /*
1249eec61dfSBiju Das * Enforce that the posted write is flushed to prevent that the
1259eec61dfSBiju Das * just handled interrupt is raised again.
1269eec61dfSBiju Das */
1279eec61dfSBiju Das readl_relaxed(priv->base + TSCR);
1289eec61dfSBiju Das }
1293fed0955SLad Prabhakar }
1303fed0955SLad Prabhakar
rzg2l_irqc_eoi(struct irq_data * d)1313fed0955SLad Prabhakar static void rzg2l_irqc_eoi(struct irq_data *d)
1323fed0955SLad Prabhakar {
1333fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
1343fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d);
1353fed0955SLad Prabhakar
1363fed0955SLad Prabhakar raw_spin_lock(&priv->lock);
1373fed0955SLad Prabhakar if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
138b4b5cd61SBiju Das rzg2l_clear_irq_int(priv, hw_irq);
1393fed0955SLad Prabhakar else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
1407cb6362cSBiju Das rzg2l_clear_tint_int(priv, hw_irq);
1413fed0955SLad Prabhakar raw_spin_unlock(&priv->lock);
1423fed0955SLad Prabhakar irq_chip_eoi_parent(d);
1433fed0955SLad Prabhakar }
1443fed0955SLad Prabhakar
rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv * priv,unsigned int hwirq)145d011c022SLad Prabhakar static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
146d011c022SLad Prabhakar unsigned int hwirq)
147d011c022SLad Prabhakar {
148d011c022SLad Prabhakar u32 bit = BIT(hwirq - IRQC_IRQ_START);
149d011c022SLad Prabhakar
150d011c022SLad Prabhakar writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK);
151d011c022SLad Prabhakar }
152d011c022SLad Prabhakar
rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv * priv,unsigned int hwirq)153d011c022SLad Prabhakar static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
154d011c022SLad Prabhakar unsigned int hwirq)
155d011c022SLad Prabhakar {
156d011c022SLad Prabhakar u32 bit = BIT(hwirq - IRQC_IRQ_START);
157d011c022SLad Prabhakar
158d011c022SLad Prabhakar writel_relaxed(readl_relaxed(priv->base + IMSK) & ~bit, priv->base + IMSK);
159d011c022SLad Prabhakar }
160d011c022SLad Prabhakar
rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv * priv,unsigned int hwirq)161d011c022SLad Prabhakar static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
162d011c022SLad Prabhakar unsigned int hwirq)
163d011c022SLad Prabhakar {
164d011c022SLad Prabhakar u32 bit = BIT(hwirq - IRQC_TINT_START);
165d011c022SLad Prabhakar
166d011c022SLad Prabhakar writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK);
167d011c022SLad Prabhakar }
168d011c022SLad Prabhakar
rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv * priv,unsigned int hwirq)169d011c022SLad Prabhakar static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
170d011c022SLad Prabhakar unsigned int hwirq)
171d011c022SLad Prabhakar {
172d011c022SLad Prabhakar u32 bit = BIT(hwirq - IRQC_TINT_START);
173d011c022SLad Prabhakar
174d011c022SLad Prabhakar writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK);
175d011c022SLad Prabhakar }
176d011c022SLad Prabhakar
rzfive_irqc_mask(struct irq_data * d)177d011c022SLad Prabhakar static void rzfive_irqc_mask(struct irq_data *d)
178d011c022SLad Prabhakar {
179d011c022SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
180d011c022SLad Prabhakar unsigned int hwirq = irqd_to_hwirq(d);
181d011c022SLad Prabhakar
182d011c022SLad Prabhakar raw_spin_lock(&priv->lock);
183d011c022SLad Prabhakar if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
184d011c022SLad Prabhakar rzfive_irqc_mask_irq_interrupt(priv, hwirq);
185d011c022SLad Prabhakar else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
186d011c022SLad Prabhakar rzfive_irqc_mask_tint_interrupt(priv, hwirq);
187d011c022SLad Prabhakar raw_spin_unlock(&priv->lock);
188d011c022SLad Prabhakar irq_chip_mask_parent(d);
189d011c022SLad Prabhakar }
190d011c022SLad Prabhakar
rzfive_irqc_unmask(struct irq_data * d)191d011c022SLad Prabhakar static void rzfive_irqc_unmask(struct irq_data *d)
192d011c022SLad Prabhakar {
193d011c022SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
194d011c022SLad Prabhakar unsigned int hwirq = irqd_to_hwirq(d);
195d011c022SLad Prabhakar
196d011c022SLad Prabhakar raw_spin_lock(&priv->lock);
197d011c022SLad Prabhakar if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
198d011c022SLad Prabhakar rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
199d011c022SLad Prabhakar else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
200d011c022SLad Prabhakar rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
201d011c022SLad Prabhakar raw_spin_unlock(&priv->lock);
202d011c022SLad Prabhakar irq_chip_unmask_parent(d);
203d011c022SLad Prabhakar }
204d011c022SLad Prabhakar
rzfive_tint_irq_endisable(struct irq_data * d,bool enable)205d011c022SLad Prabhakar static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
206d011c022SLad Prabhakar {
207d011c022SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
208d011c022SLad Prabhakar unsigned int hwirq = irqd_to_hwirq(d);
209d011c022SLad Prabhakar
210d011c022SLad Prabhakar if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) {
211d011c022SLad Prabhakar u32 offset = hwirq - IRQC_TINT_START;
212d011c022SLad Prabhakar u32 tssr_offset = TSSR_OFFSET(offset);
213d011c022SLad Prabhakar u8 tssr_index = TSSR_INDEX(offset);
214d011c022SLad Prabhakar u32 reg;
215d011c022SLad Prabhakar
216d011c022SLad Prabhakar raw_spin_lock(&priv->lock);
217d011c022SLad Prabhakar if (enable)
218d011c022SLad Prabhakar rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
219d011c022SLad Prabhakar else
220d011c022SLad Prabhakar rzfive_irqc_mask_tint_interrupt(priv, hwirq);
221d011c022SLad Prabhakar reg = readl_relaxed(priv->base + TSSR(tssr_index));
222d011c022SLad Prabhakar if (enable)
223d011c022SLad Prabhakar reg |= TIEN << TSSEL_SHIFT(tssr_offset);
224d011c022SLad Prabhakar else
225d011c022SLad Prabhakar reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
226d011c022SLad Prabhakar writel_relaxed(reg, priv->base + TSSR(tssr_index));
227d011c022SLad Prabhakar raw_spin_unlock(&priv->lock);
228d011c022SLad Prabhakar } else {
229d011c022SLad Prabhakar raw_spin_lock(&priv->lock);
230d011c022SLad Prabhakar if (enable)
231d011c022SLad Prabhakar rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
232d011c022SLad Prabhakar else
233d011c022SLad Prabhakar rzfive_irqc_mask_irq_interrupt(priv, hwirq);
234d011c022SLad Prabhakar raw_spin_unlock(&priv->lock);
235d011c022SLad Prabhakar }
236d011c022SLad Prabhakar }
237d011c022SLad Prabhakar
rzfive_irqc_irq_disable(struct irq_data * d)238d011c022SLad Prabhakar static void rzfive_irqc_irq_disable(struct irq_data *d)
239d011c022SLad Prabhakar {
240d011c022SLad Prabhakar irq_chip_disable_parent(d);
241d011c022SLad Prabhakar rzfive_tint_irq_endisable(d, false);
242d011c022SLad Prabhakar }
243d011c022SLad Prabhakar
rzfive_irqc_irq_enable(struct irq_data * d)244d011c022SLad Prabhakar static void rzfive_irqc_irq_enable(struct irq_data *d)
245d011c022SLad Prabhakar {
246d011c022SLad Prabhakar rzfive_tint_irq_endisable(d, true);
247d011c022SLad Prabhakar irq_chip_enable_parent(d);
248d011c022SLad Prabhakar }
249d011c022SLad Prabhakar
rzg2l_tint_irq_endisable(struct irq_data * d,bool enable)25046efb305SBiju Das static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
2513fed0955SLad Prabhakar {
2523fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d);
2533fed0955SLad Prabhakar
2543fed0955SLad Prabhakar if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
2553fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
2563fed0955SLad Prabhakar u32 offset = hw_irq - IRQC_TINT_START;
2573fed0955SLad Prabhakar u32 tssr_offset = TSSR_OFFSET(offset);
2583fed0955SLad Prabhakar u8 tssr_index = TSSR_INDEX(offset);
2593fed0955SLad Prabhakar u32 reg;
2603fed0955SLad Prabhakar
2613fed0955SLad Prabhakar raw_spin_lock(&priv->lock);
2623fed0955SLad Prabhakar reg = readl_relaxed(priv->base + TSSR(tssr_index));
26346efb305SBiju Das if (enable)
26446efb305SBiju Das reg |= TIEN << TSSEL_SHIFT(tssr_offset);
26546efb305SBiju Das else
266dce0919cSBiju Das reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
2673fed0955SLad Prabhakar writel_relaxed(reg, priv->base + TSSR(tssr_index));
2683fed0955SLad Prabhakar raw_spin_unlock(&priv->lock);
2693fed0955SLad Prabhakar }
27046efb305SBiju Das }
27146efb305SBiju Das
rzg2l_irqc_irq_disable(struct irq_data * d)27246efb305SBiju Das static void rzg2l_irqc_irq_disable(struct irq_data *d)
27346efb305SBiju Das {
2743fed0955SLad Prabhakar irq_chip_disable_parent(d);
275*492eee82SLad Prabhakar rzg2l_tint_irq_endisable(d, false);
2763fed0955SLad Prabhakar }
2773fed0955SLad Prabhakar
rzg2l_irqc_irq_enable(struct irq_data * d)2783fed0955SLad Prabhakar static void rzg2l_irqc_irq_enable(struct irq_data *d)
2793fed0955SLad Prabhakar {
28046efb305SBiju Das rzg2l_tint_irq_endisable(d, true);
2813fed0955SLad Prabhakar irq_chip_enable_parent(d);
2823fed0955SLad Prabhakar }
2833fed0955SLad Prabhakar
rzg2l_irq_set_type(struct irq_data * d,unsigned int type)2843fed0955SLad Prabhakar static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
2853fed0955SLad Prabhakar {
2863fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
287853a6030SBiju Das unsigned int hwirq = irqd_to_hwirq(d);
288853a6030SBiju Das u32 iitseln = hwirq - IRQC_IRQ_START;
289853a6030SBiju Das bool clear_irq_int = false;
2903fed0955SLad Prabhakar u16 sense, tmp;
2913fed0955SLad Prabhakar
2923fed0955SLad Prabhakar switch (type & IRQ_TYPE_SENSE_MASK) {
2933fed0955SLad Prabhakar case IRQ_TYPE_LEVEL_LOW:
2943fed0955SLad Prabhakar sense = IITSR_IITSEL_LEVEL_LOW;
2953fed0955SLad Prabhakar break;
2963fed0955SLad Prabhakar
2973fed0955SLad Prabhakar case IRQ_TYPE_EDGE_FALLING:
2983fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_FALLING;
299853a6030SBiju Das clear_irq_int = true;
3003fed0955SLad Prabhakar break;
3013fed0955SLad Prabhakar
3023fed0955SLad Prabhakar case IRQ_TYPE_EDGE_RISING:
3033fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_RISING;
304853a6030SBiju Das clear_irq_int = true;
3053fed0955SLad Prabhakar break;
3063fed0955SLad Prabhakar
3073fed0955SLad Prabhakar case IRQ_TYPE_EDGE_BOTH:
3083fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_BOTH;
309853a6030SBiju Das clear_irq_int = true;
3103fed0955SLad Prabhakar break;
3113fed0955SLad Prabhakar
3123fed0955SLad Prabhakar default:
3133fed0955SLad Prabhakar return -EINVAL;
3143fed0955SLad Prabhakar }
3153fed0955SLad Prabhakar
3163fed0955SLad Prabhakar raw_spin_lock(&priv->lock);
3173fed0955SLad Prabhakar tmp = readl_relaxed(priv->base + IITSR);
318853a6030SBiju Das tmp &= ~IITSR_IITSEL_MASK(iitseln);
319853a6030SBiju Das tmp |= IITSR_IITSEL(iitseln, sense);
320853a6030SBiju Das if (clear_irq_int)
321853a6030SBiju Das rzg2l_clear_irq_int(priv, hwirq);
3223fed0955SLad Prabhakar writel_relaxed(tmp, priv->base + IITSR);
3233fed0955SLad Prabhakar raw_spin_unlock(&priv->lock);
3243fed0955SLad Prabhakar
3253fed0955SLad Prabhakar return 0;
3263fed0955SLad Prabhakar }
3273fed0955SLad Prabhakar
rzg2l_disable_tint_and_set_tint_source(struct irq_data * d,struct rzg2l_irqc_priv * priv,u32 reg,u32 tssr_offset,u8 tssr_index)328853a6030SBiju Das static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv,
329853a6030SBiju Das u32 reg, u32 tssr_offset, u8 tssr_index)
330853a6030SBiju Das {
331853a6030SBiju Das u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
332853a6030SBiju Das u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
333853a6030SBiju Das
334853a6030SBiju Das /* Clear the relevant byte in reg */
335853a6030SBiju Das reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
336853a6030SBiju Das /* Set TINT and leave TIEN clear */
337853a6030SBiju Das reg |= tint << TSSEL_SHIFT(tssr_offset);
338853a6030SBiju Das writel_relaxed(reg, priv->base + TSSR(tssr_index));
339853a6030SBiju Das
340853a6030SBiju Das return reg | tien;
341853a6030SBiju Das }
342853a6030SBiju Das
rzg2l_tint_set_edge(struct irq_data * d,unsigned int type)3433fed0955SLad Prabhakar static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
3443fed0955SLad Prabhakar {
3453fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
3463fed0955SLad Prabhakar unsigned int hwirq = irqd_to_hwirq(d);
3473fed0955SLad Prabhakar u32 titseln = hwirq - IRQC_TINT_START;
348853a6030SBiju Das u32 tssr_offset = TSSR_OFFSET(titseln);
349853a6030SBiju Das u8 tssr_index = TSSR_INDEX(titseln);
3502eca4731SClaudiu Beznea u8 index, sense;
351853a6030SBiju Das u32 reg, tssr;
3523fed0955SLad Prabhakar
3533fed0955SLad Prabhakar switch (type & IRQ_TYPE_SENSE_MASK) {
3543fed0955SLad Prabhakar case IRQ_TYPE_EDGE_RISING:
3553fed0955SLad Prabhakar sense = TITSR_TITSEL_EDGE_RISING;
3563fed0955SLad Prabhakar break;
3573fed0955SLad Prabhakar
3583fed0955SLad Prabhakar case IRQ_TYPE_EDGE_FALLING:
3593fed0955SLad Prabhakar sense = TITSR_TITSEL_EDGE_FALLING;
3603fed0955SLad Prabhakar break;
3613fed0955SLad Prabhakar
3623fed0955SLad Prabhakar default:
3633fed0955SLad Prabhakar return -EINVAL;
3643fed0955SLad Prabhakar }
3653fed0955SLad Prabhakar
3662eca4731SClaudiu Beznea index = 0;
3673fed0955SLad Prabhakar if (titseln >= TITSR0_MAX_INT) {
3683fed0955SLad Prabhakar titseln -= TITSR0_MAX_INT;
3692eca4731SClaudiu Beznea index = 1;
3703fed0955SLad Prabhakar }
3713fed0955SLad Prabhakar
3723fed0955SLad Prabhakar raw_spin_lock(&priv->lock);
373853a6030SBiju Das tssr = readl_relaxed(priv->base + TSSR(tssr_index));
374853a6030SBiju Das tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index);
3752eca4731SClaudiu Beznea reg = readl_relaxed(priv->base + TITSR(index));
3763fed0955SLad Prabhakar reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
3773fed0955SLad Prabhakar reg |= sense << (titseln * TITSEL_WIDTH);
3782eca4731SClaudiu Beznea writel_relaxed(reg, priv->base + TITSR(index));
379853a6030SBiju Das rzg2l_clear_tint_int(priv, hwirq);
380853a6030SBiju Das writel_relaxed(tssr, priv->base + TSSR(tssr_index));
3813fed0955SLad Prabhakar raw_spin_unlock(&priv->lock);
3823fed0955SLad Prabhakar
3833fed0955SLad Prabhakar return 0;
3843fed0955SLad Prabhakar }
3853fed0955SLad Prabhakar
rzg2l_irqc_set_type(struct irq_data * d,unsigned int type)3863fed0955SLad Prabhakar static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
3873fed0955SLad Prabhakar {
3883fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d);
3893fed0955SLad Prabhakar int ret = -EINVAL;
3903fed0955SLad Prabhakar
3913fed0955SLad Prabhakar if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
3923fed0955SLad Prabhakar ret = rzg2l_irq_set_type(d, type);
3933fed0955SLad Prabhakar else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
3943fed0955SLad Prabhakar ret = rzg2l_tint_set_edge(d, type);
3953fed0955SLad Prabhakar if (ret)
3963fed0955SLad Prabhakar return ret;
3973fed0955SLad Prabhakar
3983fed0955SLad Prabhakar return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
3993fed0955SLad Prabhakar }
4003fed0955SLad Prabhakar
rzg2l_irqc_irq_suspend(void)40174d2ef5fSClaudiu Beznea static int rzg2l_irqc_irq_suspend(void)
40274d2ef5fSClaudiu Beznea {
40374d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
40474d2ef5fSClaudiu Beznea void __iomem *base = rzg2l_irqc_data->base;
40574d2ef5fSClaudiu Beznea
40674d2ef5fSClaudiu Beznea cache->iitsr = readl_relaxed(base + IITSR);
40774d2ef5fSClaudiu Beznea for (u8 i = 0; i < 2; i++)
40874d2ef5fSClaudiu Beznea cache->titsr[i] = readl_relaxed(base + TITSR(i));
40974d2ef5fSClaudiu Beznea
41074d2ef5fSClaudiu Beznea return 0;
41174d2ef5fSClaudiu Beznea }
41274d2ef5fSClaudiu Beznea
rzg2l_irqc_irq_resume(void)41374d2ef5fSClaudiu Beznea static void rzg2l_irqc_irq_resume(void)
41474d2ef5fSClaudiu Beznea {
41574d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
41674d2ef5fSClaudiu Beznea void __iomem *base = rzg2l_irqc_data->base;
41774d2ef5fSClaudiu Beznea
41874d2ef5fSClaudiu Beznea /*
41974d2ef5fSClaudiu Beznea * Restore only interrupt type. TSSRx will be restored at the
42074d2ef5fSClaudiu Beznea * request of pin controller to avoid spurious interrupts due
42174d2ef5fSClaudiu Beznea * to invalid PIN states.
42274d2ef5fSClaudiu Beznea */
42374d2ef5fSClaudiu Beznea for (u8 i = 0; i < 2; i++)
42474d2ef5fSClaudiu Beznea writel_relaxed(cache->titsr[i], base + TITSR(i));
42574d2ef5fSClaudiu Beznea writel_relaxed(cache->iitsr, base + IITSR);
42674d2ef5fSClaudiu Beznea }
42774d2ef5fSClaudiu Beznea
42874d2ef5fSClaudiu Beznea static struct syscore_ops rzg2l_irqc_syscore_ops = {
42974d2ef5fSClaudiu Beznea .suspend = rzg2l_irqc_irq_suspend,
43074d2ef5fSClaudiu Beznea .resume = rzg2l_irqc_irq_resume,
43174d2ef5fSClaudiu Beznea };
43274d2ef5fSClaudiu Beznea
433d011c022SLad Prabhakar static const struct irq_chip rzg2l_irqc_chip = {
4343fed0955SLad Prabhakar .name = "rzg2l-irqc",
4353fed0955SLad Prabhakar .irq_eoi = rzg2l_irqc_eoi,
4363fed0955SLad Prabhakar .irq_mask = irq_chip_mask_parent,
4373fed0955SLad Prabhakar .irq_unmask = irq_chip_unmask_parent,
4383fed0955SLad Prabhakar .irq_disable = rzg2l_irqc_irq_disable,
4393fed0955SLad Prabhakar .irq_enable = rzg2l_irqc_irq_enable,
4403fed0955SLad Prabhakar .irq_get_irqchip_state = irq_chip_get_parent_state,
4413fed0955SLad Prabhakar .irq_set_irqchip_state = irq_chip_set_parent_state,
4423fed0955SLad Prabhakar .irq_retrigger = irq_chip_retrigger_hierarchy,
4433fed0955SLad Prabhakar .irq_set_type = rzg2l_irqc_set_type,
444f881feb1SLad Prabhakar .irq_set_affinity = irq_chip_set_affinity_parent,
4453fed0955SLad Prabhakar .flags = IRQCHIP_MASK_ON_SUSPEND |
4463fed0955SLad Prabhakar IRQCHIP_SET_TYPE_MASKED |
4473fed0955SLad Prabhakar IRQCHIP_SKIP_SET_WAKE,
4483fed0955SLad Prabhakar };
4493fed0955SLad Prabhakar
450d011c022SLad Prabhakar static const struct irq_chip rzfive_irqc_chip = {
451d011c022SLad Prabhakar .name = "rzfive-irqc",
452d011c022SLad Prabhakar .irq_eoi = rzg2l_irqc_eoi,
453d011c022SLad Prabhakar .irq_mask = rzfive_irqc_mask,
454d011c022SLad Prabhakar .irq_unmask = rzfive_irqc_unmask,
455d011c022SLad Prabhakar .irq_disable = rzfive_irqc_irq_disable,
456d011c022SLad Prabhakar .irq_enable = rzfive_irqc_irq_enable,
457d011c022SLad Prabhakar .irq_get_irqchip_state = irq_chip_get_parent_state,
458d011c022SLad Prabhakar .irq_set_irqchip_state = irq_chip_set_parent_state,
459d011c022SLad Prabhakar .irq_retrigger = irq_chip_retrigger_hierarchy,
460d011c022SLad Prabhakar .irq_set_type = rzg2l_irqc_set_type,
461d011c022SLad Prabhakar .irq_set_affinity = irq_chip_set_affinity_parent,
462d011c022SLad Prabhakar .flags = IRQCHIP_MASK_ON_SUSPEND |
463d011c022SLad Prabhakar IRQCHIP_SET_TYPE_MASKED |
464d011c022SLad Prabhakar IRQCHIP_SKIP_SET_WAKE,
465d011c022SLad Prabhakar };
466d011c022SLad Prabhakar
rzg2l_irqc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)4673fed0955SLad Prabhakar static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
4683fed0955SLad Prabhakar unsigned int nr_irqs, void *arg)
4693fed0955SLad Prabhakar {
4703fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = domain->host_data;
4713fed0955SLad Prabhakar unsigned long tint = 0;
4723fed0955SLad Prabhakar irq_hw_number_t hwirq;
4733fed0955SLad Prabhakar unsigned int type;
4743fed0955SLad Prabhakar int ret;
4753fed0955SLad Prabhakar
4763fed0955SLad Prabhakar ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
4773fed0955SLad Prabhakar if (ret)
4783fed0955SLad Prabhakar return ret;
4793fed0955SLad Prabhakar
4803fed0955SLad Prabhakar /*
4813fed0955SLad Prabhakar * For TINT interrupts ie where pinctrl driver is child of irqc domain
4823fed0955SLad Prabhakar * the hwirq and TINT are encoded in fwspec->param[0].
4833fed0955SLad Prabhakar * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
4843fed0955SLad Prabhakar * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
4853fed0955SLad Prabhakar * in IRQC registers to enable a given gpio pin as interrupt.
4863fed0955SLad Prabhakar */
4873fed0955SLad Prabhakar if (hwirq > IRQC_IRQ_COUNT) {
4883fed0955SLad Prabhakar tint = TINT_EXTRACT_GPIOINT(hwirq);
4893fed0955SLad Prabhakar hwirq = TINT_EXTRACT_HWIRQ(hwirq);
4903fed0955SLad Prabhakar
4913fed0955SLad Prabhakar if (hwirq < IRQC_TINT_START)
4923fed0955SLad Prabhakar return -EINVAL;
4933fed0955SLad Prabhakar }
4943fed0955SLad Prabhakar
4953fed0955SLad Prabhakar if (hwirq > (IRQC_NUM_IRQ - 1))
4963fed0955SLad Prabhakar return -EINVAL;
4973fed0955SLad Prabhakar
498d011c022SLad Prabhakar ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,
4993fed0955SLad Prabhakar (void *)(uintptr_t)tint);
5003fed0955SLad Prabhakar if (ret)
5013fed0955SLad Prabhakar return ret;
5023fed0955SLad Prabhakar
5033fed0955SLad Prabhakar return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
5043fed0955SLad Prabhakar }
5053fed0955SLad Prabhakar
5063fed0955SLad Prabhakar static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
5073fed0955SLad Prabhakar .alloc = rzg2l_irqc_alloc,
5083fed0955SLad Prabhakar .free = irq_domain_free_irqs_common,
5093fed0955SLad Prabhakar .translate = irq_domain_translate_twocell,
5103fed0955SLad Prabhakar };
5113fed0955SLad Prabhakar
rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv * priv,struct device_node * np)5123fed0955SLad Prabhakar static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
5133fed0955SLad Prabhakar struct device_node *np)
5143fed0955SLad Prabhakar {
5153fed0955SLad Prabhakar struct of_phandle_args map;
5163fed0955SLad Prabhakar unsigned int i;
5173fed0955SLad Prabhakar int ret;
5183fed0955SLad Prabhakar
5193fed0955SLad Prabhakar for (i = 0; i < IRQC_NUM_IRQ; i++) {
5203fed0955SLad Prabhakar ret = of_irq_parse_one(np, i, &map);
5213fed0955SLad Prabhakar if (ret)
5223fed0955SLad Prabhakar return ret;
5233fed0955SLad Prabhakar of_phandle_args_to_fwspec(np, map.args, map.args_count,
5243fed0955SLad Prabhakar &priv->fwspec[i]);
5253fed0955SLad Prabhakar }
5263fed0955SLad Prabhakar
5273fed0955SLad Prabhakar return 0;
5283fed0955SLad Prabhakar }
5293fed0955SLad Prabhakar
rzg2l_irqc_common_init(struct device_node * node,struct device_node * parent,const struct irq_chip * irq_chip)530d011c022SLad Prabhakar static int rzg2l_irqc_common_init(struct device_node *node, struct device_node *parent,
531d011c022SLad Prabhakar const struct irq_chip *irq_chip)
5323fed0955SLad Prabhakar {
5333fed0955SLad Prabhakar struct irq_domain *irq_domain, *parent_domain;
5343fed0955SLad Prabhakar struct platform_device *pdev;
5353fed0955SLad Prabhakar struct reset_control *resetn;
5363fed0955SLad Prabhakar int ret;
5373fed0955SLad Prabhakar
5383fed0955SLad Prabhakar pdev = of_find_device_by_node(node);
5393fed0955SLad Prabhakar if (!pdev)
5403fed0955SLad Prabhakar return -ENODEV;
5413fed0955SLad Prabhakar
5423fed0955SLad Prabhakar parent_domain = irq_find_host(parent);
5433fed0955SLad Prabhakar if (!parent_domain) {
5443fed0955SLad Prabhakar dev_err(&pdev->dev, "cannot find parent domain\n");
5453fed0955SLad Prabhakar return -ENODEV;
5463fed0955SLad Prabhakar }
5473fed0955SLad Prabhakar
54874d2ef5fSClaudiu Beznea rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
54974d2ef5fSClaudiu Beznea if (!rzg2l_irqc_data)
5503fed0955SLad Prabhakar return -ENOMEM;
5513fed0955SLad Prabhakar
552d011c022SLad Prabhakar rzg2l_irqc_data->irqchip = irq_chip;
553d011c022SLad Prabhakar
55474d2ef5fSClaudiu Beznea rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
55574d2ef5fSClaudiu Beznea if (IS_ERR(rzg2l_irqc_data->base))
55674d2ef5fSClaudiu Beznea return PTR_ERR(rzg2l_irqc_data->base);
5573fed0955SLad Prabhakar
55874d2ef5fSClaudiu Beznea ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
5593fed0955SLad Prabhakar if (ret) {
5603fed0955SLad Prabhakar dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
5613fed0955SLad Prabhakar return ret;
5623fed0955SLad Prabhakar }
5633fed0955SLad Prabhakar
5643fed0955SLad Prabhakar resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
5653fed0955SLad Prabhakar if (IS_ERR(resetn))
5663fed0955SLad Prabhakar return PTR_ERR(resetn);
5673fed0955SLad Prabhakar
5683fed0955SLad Prabhakar ret = reset_control_deassert(resetn);
5693fed0955SLad Prabhakar if (ret) {
5703fed0955SLad Prabhakar dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
5713fed0955SLad Prabhakar return ret;
5723fed0955SLad Prabhakar }
5733fed0955SLad Prabhakar
5743fed0955SLad Prabhakar pm_runtime_enable(&pdev->dev);
5753fed0955SLad Prabhakar ret = pm_runtime_resume_and_get(&pdev->dev);
5763fed0955SLad Prabhakar if (ret < 0) {
5773fed0955SLad Prabhakar dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
5783fed0955SLad Prabhakar goto pm_disable;
5793fed0955SLad Prabhakar }
5803fed0955SLad Prabhakar
58174d2ef5fSClaudiu Beznea raw_spin_lock_init(&rzg2l_irqc_data->lock);
5823fed0955SLad Prabhakar
5833fed0955SLad Prabhakar irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
5843fed0955SLad Prabhakar node, &rzg2l_irqc_domain_ops,
58574d2ef5fSClaudiu Beznea rzg2l_irqc_data);
5863fed0955SLad Prabhakar if (!irq_domain) {
5873fed0955SLad Prabhakar dev_err(&pdev->dev, "failed to add irq domain\n");
5883fed0955SLad Prabhakar ret = -ENOMEM;
5893fed0955SLad Prabhakar goto pm_put;
5903fed0955SLad Prabhakar }
5913fed0955SLad Prabhakar
59274d2ef5fSClaudiu Beznea register_syscore_ops(&rzg2l_irqc_syscore_ops);
59374d2ef5fSClaudiu Beznea
5943fed0955SLad Prabhakar return 0;
5953fed0955SLad Prabhakar
5963fed0955SLad Prabhakar pm_put:
5973fed0955SLad Prabhakar pm_runtime_put(&pdev->dev);
5983fed0955SLad Prabhakar pm_disable:
5993fed0955SLad Prabhakar pm_runtime_disable(&pdev->dev);
6003fed0955SLad Prabhakar reset_control_assert(resetn);
6013fed0955SLad Prabhakar return ret;
6023fed0955SLad Prabhakar }
6033fed0955SLad Prabhakar
rzg2l_irqc_init(struct device_node * node,struct device_node * parent)604d011c022SLad Prabhakar static int __init rzg2l_irqc_init(struct device_node *node,
605d011c022SLad Prabhakar struct device_node *parent)
606d011c022SLad Prabhakar {
607d011c022SLad Prabhakar return rzg2l_irqc_common_init(node, parent, &rzg2l_irqc_chip);
608d011c022SLad Prabhakar }
609d011c022SLad Prabhakar
rzfive_irqc_init(struct device_node * node,struct device_node * parent)610d011c022SLad Prabhakar static int __init rzfive_irqc_init(struct device_node *node,
611d011c022SLad Prabhakar struct device_node *parent)
612d011c022SLad Prabhakar {
613d011c022SLad Prabhakar return rzg2l_irqc_common_init(node, parent, &rzfive_irqc_chip);
614d011c022SLad Prabhakar }
615d011c022SLad Prabhakar
6163fed0955SLad Prabhakar IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
6173fed0955SLad Prabhakar IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
618d011c022SLad Prabhakar IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_init)
6193fed0955SLad Prabhakar IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
6203fed0955SLad Prabhakar MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
6213fed0955SLad Prabhakar MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
622