1c53bb605SFabio Estevam // SPDX-License-Identifier: GPL-2.0+
2c53bb605SFabio Estevam //
3c53bb605SFabio Estevam // Copyright (C) 2000-2001 Deep Blue Solutions
4c53bb605SFabio Estevam // Copyright (C) 2002 Shane Nay (shane@minirl.com)
5c53bb605SFabio Estevam // Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
6c53bb605SFabio Estevam // Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
7bea5af41SShawn Guo
8bea5af41SShawn Guo #include <linux/interrupt.h>
9bea5af41SShawn Guo #include <linux/irq.h>
10bea5af41SShawn Guo #include <linux/clockchips.h>
11bea5af41SShawn Guo #include <linux/clk.h>
12bea5af41SShawn Guo #include <linux/delay.h>
13bea5af41SShawn Guo #include <linux/err.h>
14bea5af41SShawn Guo #include <linux/sched_clock.h>
15bea5af41SShawn Guo #include <linux/slab.h>
16bea5af41SShawn Guo #include <linux/of.h>
17bea5af41SShawn Guo #include <linux/of_address.h>
18bea5af41SShawn Guo #include <linux/of_irq.h>
19bea5af41SShawn Guo
20bea5af41SShawn Guo /*
21bea5af41SShawn Guo * There are 4 versions of the timer hardware on Freescale MXC hardware.
22bea5af41SShawn Guo * - MX1/MXL
23bea5af41SShawn Guo * - MX21, MX27.
24bea5af41SShawn Guo * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
25bea5af41SShawn Guo * - MX6DL, MX6SX, MX6Q(rev1.1+)
26bea5af41SShawn Guo */
27281bf6b9SUwe Kleine-König enum imx_gpt_type {
28281bf6b9SUwe Kleine-König GPT_TYPE_IMX1, /* i.MX1 */
29281bf6b9SUwe Kleine-König GPT_TYPE_IMX21, /* i.MX21/27 */
30281bf6b9SUwe Kleine-König GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */
31281bf6b9SUwe Kleine-König GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */
32281bf6b9SUwe Kleine-König };
33bea5af41SShawn Guo
34bea5af41SShawn Guo /* defines common for all i.MX */
35bea5af41SShawn Guo #define MXC_TCTL 0x00
36bea5af41SShawn Guo #define MXC_TCTL_TEN (1 << 0) /* Enable module */
37bea5af41SShawn Guo #define MXC_TPRER 0x04
38bea5af41SShawn Guo
39bea5af41SShawn Guo /* MX1, MX21, MX27 */
40bea5af41SShawn Guo #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
41bea5af41SShawn Guo #define MX1_2_TCTL_IRQEN (1 << 4)
42bea5af41SShawn Guo #define MX1_2_TCTL_FRR (1 << 8)
43bea5af41SShawn Guo #define MX1_2_TCMP 0x08
44bea5af41SShawn Guo #define MX1_2_TCN 0x10
45bea5af41SShawn Guo #define MX1_2_TSTAT 0x14
46bea5af41SShawn Guo
47bea5af41SShawn Guo /* MX21, MX27 */
48bea5af41SShawn Guo #define MX2_TSTAT_CAPT (1 << 1)
49bea5af41SShawn Guo #define MX2_TSTAT_COMP (1 << 0)
50bea5af41SShawn Guo
51bea5af41SShawn Guo /* MX31, MX35, MX25, MX5, MX6 */
52bea5af41SShawn Guo #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
53bea5af41SShawn Guo #define V2_TCTL_CLK_IPG (1 << 6)
54bea5af41SShawn Guo #define V2_TCTL_CLK_PER (2 << 6)
55bea5af41SShawn Guo #define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
56bea5af41SShawn Guo #define V2_TCTL_FRR (1 << 9)
57bea5af41SShawn Guo #define V2_TCTL_24MEN (1 << 10)
58bea5af41SShawn Guo #define V2_TPRER_PRE24M 12
59bea5af41SShawn Guo #define V2_IR 0x0c
60bea5af41SShawn Guo #define V2_TSTAT 0x08
61bea5af41SShawn Guo #define V2_TSTAT_OF1 (1 << 0)
62bea5af41SShawn Guo #define V2_TCN 0x24
63bea5af41SShawn Guo #define V2_TCMP 0x10
64bea5af41SShawn Guo
65bea5af41SShawn Guo #define V2_TIMER_RATE_OSC_DIV8 3000000
66bea5af41SShawn Guo
67bea5af41SShawn Guo struct imx_timer {
68bea5af41SShawn Guo enum imx_gpt_type type;
69bea5af41SShawn Guo void __iomem *base;
70bea5af41SShawn Guo int irq;
71bea5af41SShawn Guo struct clk *clk_per;
72bea5af41SShawn Guo struct clk *clk_ipg;
73bea5af41SShawn Guo const struct imx_gpt_data *gpt;
74bea5af41SShawn Guo struct clock_event_device ced;
75bea5af41SShawn Guo };
76bea5af41SShawn Guo
77bea5af41SShawn Guo struct imx_gpt_data {
78bea5af41SShawn Guo int reg_tstat;
79bea5af41SShawn Guo int reg_tcn;
80bea5af41SShawn Guo int reg_tcmp;
81bea5af41SShawn Guo void (*gpt_setup_tctl)(struct imx_timer *imxtm);
82bea5af41SShawn Guo void (*gpt_irq_enable)(struct imx_timer *imxtm);
83bea5af41SShawn Guo void (*gpt_irq_disable)(struct imx_timer *imxtm);
84bea5af41SShawn Guo void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
85bea5af41SShawn Guo int (*set_next_event)(unsigned long evt,
86bea5af41SShawn Guo struct clock_event_device *ced);
87bea5af41SShawn Guo };
88bea5af41SShawn Guo
to_imx_timer(struct clock_event_device * ced)89bea5af41SShawn Guo static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
90bea5af41SShawn Guo {
91bea5af41SShawn Guo return container_of(ced, struct imx_timer, ced);
92bea5af41SShawn Guo }
93bea5af41SShawn Guo
imx1_gpt_irq_disable(struct imx_timer * imxtm)94bea5af41SShawn Guo static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
95bea5af41SShawn Guo {
96bea5af41SShawn Guo unsigned int tmp;
97bea5af41SShawn Guo
98bea5af41SShawn Guo tmp = readl_relaxed(imxtm->base + MXC_TCTL);
99bea5af41SShawn Guo writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
100bea5af41SShawn Guo }
101bea5af41SShawn Guo
imx31_gpt_irq_disable(struct imx_timer * imxtm)102bea5af41SShawn Guo static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
103bea5af41SShawn Guo {
104bea5af41SShawn Guo writel_relaxed(0, imxtm->base + V2_IR);
105bea5af41SShawn Guo }
106bea5af41SShawn Guo
imx1_gpt_irq_enable(struct imx_timer * imxtm)107bea5af41SShawn Guo static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
108bea5af41SShawn Guo {
109bea5af41SShawn Guo unsigned int tmp;
110bea5af41SShawn Guo
111bea5af41SShawn Guo tmp = readl_relaxed(imxtm->base + MXC_TCTL);
112bea5af41SShawn Guo writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
113bea5af41SShawn Guo }
114bea5af41SShawn Guo
imx31_gpt_irq_enable(struct imx_timer * imxtm)115bea5af41SShawn Guo static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
116bea5af41SShawn Guo {
117bea5af41SShawn Guo writel_relaxed(1<<0, imxtm->base + V2_IR);
118bea5af41SShawn Guo }
119bea5af41SShawn Guo
imx1_gpt_irq_acknowledge(struct imx_timer * imxtm)120bea5af41SShawn Guo static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
121bea5af41SShawn Guo {
122bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
123bea5af41SShawn Guo }
124bea5af41SShawn Guo
imx21_gpt_irq_acknowledge(struct imx_timer * imxtm)125bea5af41SShawn Guo static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
126bea5af41SShawn Guo {
127bea5af41SShawn Guo writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
128bea5af41SShawn Guo imxtm->base + MX1_2_TSTAT);
129bea5af41SShawn Guo }
130bea5af41SShawn Guo
imx31_gpt_irq_acknowledge(struct imx_timer * imxtm)131bea5af41SShawn Guo static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
132bea5af41SShawn Guo {
133bea5af41SShawn Guo writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
134bea5af41SShawn Guo }
135bea5af41SShawn Guo
136bea5af41SShawn Guo static void __iomem *sched_clock_reg;
137bea5af41SShawn Guo
mxc_read_sched_clock(void)138bea5af41SShawn Guo static u64 notrace mxc_read_sched_clock(void)
139bea5af41SShawn Guo {
140bea5af41SShawn Guo return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
141bea5af41SShawn Guo }
142bea5af41SShawn Guo
143df181e38SAnson Huang #if defined(CONFIG_ARM)
144bea5af41SShawn Guo static struct delay_timer imx_delay_timer;
145bea5af41SShawn Guo
imx_read_current_timer(void)146bea5af41SShawn Guo static unsigned long imx_read_current_timer(void)
147bea5af41SShawn Guo {
148bea5af41SShawn Guo return readl_relaxed(sched_clock_reg);
149bea5af41SShawn Guo }
150df181e38SAnson Huang #endif
151bea5af41SShawn Guo
mxc_clocksource_init(struct imx_timer * imxtm)152bea5af41SShawn Guo static int __init mxc_clocksource_init(struct imx_timer *imxtm)
153bea5af41SShawn Guo {
154bea5af41SShawn Guo unsigned int c = clk_get_rate(imxtm->clk_per);
155bea5af41SShawn Guo void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
156bea5af41SShawn Guo
157df181e38SAnson Huang #if defined(CONFIG_ARM)
158bea5af41SShawn Guo imx_delay_timer.read_current_timer = &imx_read_current_timer;
159bea5af41SShawn Guo imx_delay_timer.freq = c;
160bea5af41SShawn Guo register_current_timer_delay(&imx_delay_timer);
161df181e38SAnson Huang #endif
162bea5af41SShawn Guo
163bea5af41SShawn Guo sched_clock_reg = reg;
164bea5af41SShawn Guo
165bea5af41SShawn Guo sched_clock_register(mxc_read_sched_clock, 32, c);
166bea5af41SShawn Guo return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
167bea5af41SShawn Guo clocksource_mmio_readl_up);
168bea5af41SShawn Guo }
169bea5af41SShawn Guo
170bea5af41SShawn Guo /* clock event */
171bea5af41SShawn Guo
mx1_2_set_next_event(unsigned long evt,struct clock_event_device * ced)172bea5af41SShawn Guo static int mx1_2_set_next_event(unsigned long evt,
173bea5af41SShawn Guo struct clock_event_device *ced)
174bea5af41SShawn Guo {
175bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced);
176bea5af41SShawn Guo unsigned long tcmp;
177bea5af41SShawn Guo
178bea5af41SShawn Guo tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
179bea5af41SShawn Guo
180bea5af41SShawn Guo writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
181bea5af41SShawn Guo
182bea5af41SShawn Guo return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
183bea5af41SShawn Guo -ETIME : 0;
184bea5af41SShawn Guo }
185bea5af41SShawn Guo
v2_set_next_event(unsigned long evt,struct clock_event_device * ced)186bea5af41SShawn Guo static int v2_set_next_event(unsigned long evt,
187bea5af41SShawn Guo struct clock_event_device *ced)
188bea5af41SShawn Guo {
189bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced);
190bea5af41SShawn Guo unsigned long tcmp;
191bea5af41SShawn Guo
192bea5af41SShawn Guo tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
193bea5af41SShawn Guo
194bea5af41SShawn Guo writel_relaxed(tcmp, imxtm->base + V2_TCMP);
195bea5af41SShawn Guo
196bea5af41SShawn Guo return evt < 0x7fffffff &&
197bea5af41SShawn Guo (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
198bea5af41SShawn Guo -ETIME : 0;
199bea5af41SShawn Guo }
200bea5af41SShawn Guo
mxc_shutdown(struct clock_event_device * ced)20126b91f04SViresh Kumar static int mxc_shutdown(struct clock_event_device *ced)
20226b91f04SViresh Kumar {
20326b91f04SViresh Kumar struct imx_timer *imxtm = to_imx_timer(ced);
20426b91f04SViresh Kumar u32 tcn;
20526b91f04SViresh Kumar
20626b91f04SViresh Kumar /* Disable interrupt in GPT module */
20726b91f04SViresh Kumar imxtm->gpt->gpt_irq_disable(imxtm);
20826b91f04SViresh Kumar
20926b91f04SViresh Kumar tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
21026b91f04SViresh Kumar /* Set event time into far-far future */
21126b91f04SViresh Kumar writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
21226b91f04SViresh Kumar
21326b91f04SViresh Kumar /* Clear pending interrupt */
21426b91f04SViresh Kumar imxtm->gpt->gpt_irq_acknowledge(imxtm);
21526b91f04SViresh Kumar
216bea5af41SShawn Guo #ifdef DEBUG
21726b91f04SViresh Kumar printk(KERN_INFO "%s: changing mode\n", __func__);
218bea5af41SShawn Guo #endif /* DEBUG */
219bea5af41SShawn Guo
22026b91f04SViresh Kumar return 0;
22126b91f04SViresh Kumar }
22226b91f04SViresh Kumar
mxc_set_oneshot(struct clock_event_device * ced)22326b91f04SViresh Kumar static int mxc_set_oneshot(struct clock_event_device *ced)
224bea5af41SShawn Guo {
225bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced);
226bea5af41SShawn Guo
227bea5af41SShawn Guo /* Disable interrupt in GPT module */
228bea5af41SShawn Guo imxtm->gpt->gpt_irq_disable(imxtm);
229bea5af41SShawn Guo
23026b91f04SViresh Kumar if (!clockevent_state_oneshot(ced)) {
231bea5af41SShawn Guo u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
232bea5af41SShawn Guo /* Set event time into far-far future */
233bea5af41SShawn Guo writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
234bea5af41SShawn Guo
235bea5af41SShawn Guo /* Clear pending interrupt */
236bea5af41SShawn Guo imxtm->gpt->gpt_irq_acknowledge(imxtm);
237bea5af41SShawn Guo }
238bea5af41SShawn Guo
239bea5af41SShawn Guo #ifdef DEBUG
24026b91f04SViresh Kumar printk(KERN_INFO "%s: changing mode\n", __func__);
241bea5af41SShawn Guo #endif /* DEBUG */
242bea5af41SShawn Guo
243bea5af41SShawn Guo /*
244bea5af41SShawn Guo * Do not put overhead of interrupt enable/disable into
245bea5af41SShawn Guo * mxc_set_next_event(), the core has about 4 minutes
246bea5af41SShawn Guo * to call mxc_set_next_event() or shutdown clock after
247bea5af41SShawn Guo * mode switching
248bea5af41SShawn Guo */
249bea5af41SShawn Guo imxtm->gpt->gpt_irq_enable(imxtm);
25026b91f04SViresh Kumar
25126b91f04SViresh Kumar return 0;
252bea5af41SShawn Guo }
253bea5af41SShawn Guo
254bea5af41SShawn Guo /*
255bea5af41SShawn Guo * IRQ handler for the timer
256bea5af41SShawn Guo */
mxc_timer_interrupt(int irq,void * dev_id)257bea5af41SShawn Guo static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
258bea5af41SShawn Guo {
259bea5af41SShawn Guo struct clock_event_device *ced = dev_id;
260bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced);
261bea5af41SShawn Guo
262*bf3159c0SDaniel Lezcano readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
263bea5af41SShawn Guo
264bea5af41SShawn Guo imxtm->gpt->gpt_irq_acknowledge(imxtm);
265bea5af41SShawn Guo
266bea5af41SShawn Guo ced->event_handler(ced);
267bea5af41SShawn Guo
268bea5af41SShawn Guo return IRQ_HANDLED;
269bea5af41SShawn Guo }
270bea5af41SShawn Guo
mxc_clockevent_init(struct imx_timer * imxtm)271bea5af41SShawn Guo static int __init mxc_clockevent_init(struct imx_timer *imxtm)
272bea5af41SShawn Guo {
273bea5af41SShawn Guo struct clock_event_device *ced = &imxtm->ced;
274bea5af41SShawn Guo
275bea5af41SShawn Guo ced->name = "mxc_timer1";
276f1c08c9bSLucas Stach ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
27726b91f04SViresh Kumar ced->set_state_shutdown = mxc_shutdown;
27826b91f04SViresh Kumar ced->set_state_oneshot = mxc_set_oneshot;
27926b91f04SViresh Kumar ced->tick_resume = mxc_shutdown;
280bea5af41SShawn Guo ced->set_next_event = imxtm->gpt->set_next_event;
281bea5af41SShawn Guo ced->rating = 200;
282bea5af41SShawn Guo ced->cpumask = cpumask_of(0);
283f1c08c9bSLucas Stach ced->irq = imxtm->irq;
284bea5af41SShawn Guo clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
285bea5af41SShawn Guo 0xff, 0xfffffffe);
286bea5af41SShawn Guo
287cc2550b4Safzal mohammed return request_irq(imxtm->irq, mxc_timer_interrupt,
288cc2550b4Safzal mohammed IRQF_TIMER | IRQF_IRQPOLL, "i.MX Timer Tick", ced);
289bea5af41SShawn Guo }
290bea5af41SShawn Guo
imx1_gpt_setup_tctl(struct imx_timer * imxtm)291bea5af41SShawn Guo static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
292bea5af41SShawn Guo {
293bea5af41SShawn Guo u32 tctl_val;
294bea5af41SShawn Guo
295bea5af41SShawn Guo tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
296bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
297bea5af41SShawn Guo }
298bea5af41SShawn Guo
imx31_gpt_setup_tctl(struct imx_timer * imxtm)299bea5af41SShawn Guo static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
300bea5af41SShawn Guo {
301bea5af41SShawn Guo u32 tctl_val;
302bea5af41SShawn Guo
303bea5af41SShawn Guo tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
304bea5af41SShawn Guo if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
305bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_OSC_DIV8;
306bea5af41SShawn Guo else
307bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_PER;
308bea5af41SShawn Guo
309bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
310bea5af41SShawn Guo }
311bea5af41SShawn Guo
imx6dl_gpt_setup_tctl(struct imx_timer * imxtm)312bea5af41SShawn Guo static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
313bea5af41SShawn Guo {
314bea5af41SShawn Guo u32 tctl_val;
315bea5af41SShawn Guo
316bea5af41SShawn Guo tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
317bea5af41SShawn Guo if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
318bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_OSC_DIV8;
319bea5af41SShawn Guo /* 24 / 8 = 3 MHz */
320bea5af41SShawn Guo writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
321bea5af41SShawn Guo tctl_val |= V2_TCTL_24MEN;
322bea5af41SShawn Guo } else {
323bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_PER;
324bea5af41SShawn Guo }
325bea5af41SShawn Guo
326bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
327bea5af41SShawn Guo }
328bea5af41SShawn Guo
329bea5af41SShawn Guo static const struct imx_gpt_data imx1_gpt_data = {
330bea5af41SShawn Guo .reg_tstat = MX1_2_TSTAT,
331bea5af41SShawn Guo .reg_tcn = MX1_2_TCN,
332bea5af41SShawn Guo .reg_tcmp = MX1_2_TCMP,
333bea5af41SShawn Guo .gpt_irq_enable = imx1_gpt_irq_enable,
334bea5af41SShawn Guo .gpt_irq_disable = imx1_gpt_irq_disable,
335bea5af41SShawn Guo .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
336bea5af41SShawn Guo .gpt_setup_tctl = imx1_gpt_setup_tctl,
337bea5af41SShawn Guo .set_next_event = mx1_2_set_next_event,
338bea5af41SShawn Guo };
339bea5af41SShawn Guo
340bea5af41SShawn Guo static const struct imx_gpt_data imx21_gpt_data = {
341bea5af41SShawn Guo .reg_tstat = MX1_2_TSTAT,
342bea5af41SShawn Guo .reg_tcn = MX1_2_TCN,
343bea5af41SShawn Guo .reg_tcmp = MX1_2_TCMP,
34495aded1bSUwe Kleine-König .gpt_irq_enable = imx1_gpt_irq_enable,
34595aded1bSUwe Kleine-König .gpt_irq_disable = imx1_gpt_irq_disable,
346bea5af41SShawn Guo .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
34795aded1bSUwe Kleine-König .gpt_setup_tctl = imx1_gpt_setup_tctl,
348bea5af41SShawn Guo .set_next_event = mx1_2_set_next_event,
349bea5af41SShawn Guo };
350bea5af41SShawn Guo
351bea5af41SShawn Guo static const struct imx_gpt_data imx31_gpt_data = {
352bea5af41SShawn Guo .reg_tstat = V2_TSTAT,
353bea5af41SShawn Guo .reg_tcn = V2_TCN,
354bea5af41SShawn Guo .reg_tcmp = V2_TCMP,
355bea5af41SShawn Guo .gpt_irq_enable = imx31_gpt_irq_enable,
356bea5af41SShawn Guo .gpt_irq_disable = imx31_gpt_irq_disable,
357bea5af41SShawn Guo .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
358bea5af41SShawn Guo .gpt_setup_tctl = imx31_gpt_setup_tctl,
359bea5af41SShawn Guo .set_next_event = v2_set_next_event,
360bea5af41SShawn Guo };
361bea5af41SShawn Guo
362bea5af41SShawn Guo static const struct imx_gpt_data imx6dl_gpt_data = {
363bea5af41SShawn Guo .reg_tstat = V2_TSTAT,
364bea5af41SShawn Guo .reg_tcn = V2_TCN,
365bea5af41SShawn Guo .reg_tcmp = V2_TCMP,
36695aded1bSUwe Kleine-König .gpt_irq_enable = imx31_gpt_irq_enable,
36795aded1bSUwe Kleine-König .gpt_irq_disable = imx31_gpt_irq_disable,
36895aded1bSUwe Kleine-König .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
369bea5af41SShawn Guo .gpt_setup_tctl = imx6dl_gpt_setup_tctl,
370bea5af41SShawn Guo .set_next_event = v2_set_next_event,
371bea5af41SShawn Guo };
372bea5af41SShawn Guo
_mxc_timer_init(struct imx_timer * imxtm)373c11cd416SDaniel Lezcano static int __init _mxc_timer_init(struct imx_timer *imxtm)
374bea5af41SShawn Guo {
375c11cd416SDaniel Lezcano int ret;
376c11cd416SDaniel Lezcano
377bea5af41SShawn Guo switch (imxtm->type) {
378bea5af41SShawn Guo case GPT_TYPE_IMX1:
379bea5af41SShawn Guo imxtm->gpt = &imx1_gpt_data;
380bea5af41SShawn Guo break;
381bea5af41SShawn Guo case GPT_TYPE_IMX21:
382bea5af41SShawn Guo imxtm->gpt = &imx21_gpt_data;
383bea5af41SShawn Guo break;
384bea5af41SShawn Guo case GPT_TYPE_IMX31:
385bea5af41SShawn Guo imxtm->gpt = &imx31_gpt_data;
386bea5af41SShawn Guo break;
387bea5af41SShawn Guo case GPT_TYPE_IMX6DL:
388bea5af41SShawn Guo imxtm->gpt = &imx6dl_gpt_data;
389bea5af41SShawn Guo break;
390bea5af41SShawn Guo default:
391c11cd416SDaniel Lezcano return -EINVAL;
392bea5af41SShawn Guo }
393bea5af41SShawn Guo
394bea5af41SShawn Guo if (IS_ERR(imxtm->clk_per)) {
395bea5af41SShawn Guo pr_err("i.MX timer: unable to get clk\n");
396c11cd416SDaniel Lezcano return PTR_ERR(imxtm->clk_per);
397bea5af41SShawn Guo }
398bea5af41SShawn Guo
399bea5af41SShawn Guo if (!IS_ERR(imxtm->clk_ipg))
400bea5af41SShawn Guo clk_prepare_enable(imxtm->clk_ipg);
401bea5af41SShawn Guo
402bea5af41SShawn Guo clk_prepare_enable(imxtm->clk_per);
403bea5af41SShawn Guo
404bea5af41SShawn Guo /*
405bea5af41SShawn Guo * Initialise to a known state (all timers off, and timing reset)
406bea5af41SShawn Guo */
407bea5af41SShawn Guo
408bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MXC_TCTL);
409bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
410bea5af41SShawn Guo
411bea5af41SShawn Guo imxtm->gpt->gpt_setup_tctl(imxtm);
412bea5af41SShawn Guo
413bea5af41SShawn Guo /* init and register the timer to the framework */
414c11cd416SDaniel Lezcano ret = mxc_clocksource_init(imxtm);
415c11cd416SDaniel Lezcano if (ret)
416c11cd416SDaniel Lezcano return ret;
417c11cd416SDaniel Lezcano
418c11cd416SDaniel Lezcano return mxc_clockevent_init(imxtm);
419bea5af41SShawn Guo }
420bea5af41SShawn Guo
mxc_timer_init_dt(struct device_node * np,enum imx_gpt_type type)421c11cd416SDaniel Lezcano static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
422bea5af41SShawn Guo {
423bea5af41SShawn Guo struct imx_timer *imxtm;
424bea5af41SShawn Guo static int initialized;
425c11cd416SDaniel Lezcano int ret;
426bea5af41SShawn Guo
427bea5af41SShawn Guo /* Support one instance only */
428bea5af41SShawn Guo if (initialized)
429c11cd416SDaniel Lezcano return 0;
430bea5af41SShawn Guo
431bea5af41SShawn Guo imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
432c11cd416SDaniel Lezcano if (!imxtm)
433c11cd416SDaniel Lezcano return -ENOMEM;
434bea5af41SShawn Guo
435bea5af41SShawn Guo imxtm->base = of_iomap(np, 0);
4368051a993SJacky Bai if (!imxtm->base) {
4378051a993SJacky Bai ret = -ENXIO;
4388051a993SJacky Bai goto err_kfree;
4398051a993SJacky Bai }
440c11cd416SDaniel Lezcano
441bea5af41SShawn Guo imxtm->irq = irq_of_parse_and_map(np, 0);
4428051a993SJacky Bai if (imxtm->irq <= 0) {
4438051a993SJacky Bai ret = -EINVAL;
4448051a993SJacky Bai goto err_kfree;
4458051a993SJacky Bai }
446bea5af41SShawn Guo
447bea5af41SShawn Guo imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
448bea5af41SShawn Guo
449bea5af41SShawn Guo /* Try osc_per first, and fall back to per otherwise */
450bea5af41SShawn Guo imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
451bea5af41SShawn Guo if (IS_ERR(imxtm->clk_per))
452bea5af41SShawn Guo imxtm->clk_per = of_clk_get_by_name(np, "per");
453bea5af41SShawn Guo
454bea5af41SShawn Guo imxtm->type = type;
455bea5af41SShawn Guo
456c11cd416SDaniel Lezcano ret = _mxc_timer_init(imxtm);
457c11cd416SDaniel Lezcano if (ret)
4588051a993SJacky Bai goto err_kfree;
459bea5af41SShawn Guo
460bea5af41SShawn Guo initialized = 1;
461c11cd416SDaniel Lezcano
462c11cd416SDaniel Lezcano return 0;
4638051a993SJacky Bai
4648051a993SJacky Bai err_kfree:
4658051a993SJacky Bai kfree(imxtm);
4668051a993SJacky Bai return ret;
467bea5af41SShawn Guo }
468bea5af41SShawn Guo
imx1_timer_init_dt(struct device_node * np)469c11cd416SDaniel Lezcano static int __init imx1_timer_init_dt(struct device_node *np)
470bea5af41SShawn Guo {
471c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX1);
472bea5af41SShawn Guo }
473bea5af41SShawn Guo
imx21_timer_init_dt(struct device_node * np)474c11cd416SDaniel Lezcano static int __init imx21_timer_init_dt(struct device_node *np)
475bea5af41SShawn Guo {
476c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX21);
477bea5af41SShawn Guo }
478bea5af41SShawn Guo
imx31_timer_init_dt(struct device_node * np)479c11cd416SDaniel Lezcano static int __init imx31_timer_init_dt(struct device_node *np)
480bea5af41SShawn Guo {
481bea5af41SShawn Guo enum imx_gpt_type type = GPT_TYPE_IMX31;
482bea5af41SShawn Guo
483bea5af41SShawn Guo /*
484bea5af41SShawn Guo * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
485bea5af41SShawn Guo * GPT device, while they actually have different programming model.
486bea5af41SShawn Guo * This is a workaround to keep the existing i.MX6DL/S DTBs continue
487bea5af41SShawn Guo * working with the new kernel.
488bea5af41SShawn Guo */
489bea5af41SShawn Guo if (of_machine_is_compatible("fsl,imx6dl"))
490bea5af41SShawn Guo type = GPT_TYPE_IMX6DL;
491bea5af41SShawn Guo
492c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, type);
493bea5af41SShawn Guo }
494bea5af41SShawn Guo
imx6dl_timer_init_dt(struct device_node * np)495c11cd416SDaniel Lezcano static int __init imx6dl_timer_init_dt(struct device_node *np)
496bea5af41SShawn Guo {
497c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
498bea5af41SShawn Guo }
499bea5af41SShawn Guo
50017273395SDaniel Lezcano TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
50117273395SDaniel Lezcano TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
50217273395SDaniel Lezcano TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
50317273395SDaniel Lezcano TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
50417273395SDaniel Lezcano TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
50517273395SDaniel Lezcano TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
50617273395SDaniel Lezcano TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
50717273395SDaniel Lezcano TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
50817273395SDaniel Lezcano TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
50917273395SDaniel Lezcano TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
51017273395SDaniel Lezcano TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
51117273395SDaniel Lezcano TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
512