| /linux/drivers/clk/renesas/ |
| H A D | rcar-gen4-cpg.c | 106 unsigned long prate; in cpg_pll_8_25_clk_determine_rate() local
108 prate = req->best_parent_rate * 2; in cpg_pll_8_25_clk_determine_rate()
109 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_8_25_clk_determine_rate()
110 max_mult = min(div64_ul(req->max_rate, prate), 256ULL); in cpg_pll_8_25_clk_determine_rate()
115 ni = div64_ul(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
121 nf = div64_ul((u64)(req->rate - prate * ni) << 24, in cpg_pll_8_25_clk_determine_rate()
125 ni = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
129 req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24); in cpg_pll_8_25_clk_determine_rate()
138 unsigned long prate = parent_rate * 2; in cpg_pll_8_25_clk_set_rate() local
144 ni = div64_ul(rate, prate); in cpg_pll_8_25_clk_set_rate()
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| H A D | rcar-gen3-cpg.c | 68 unsigned long prate; in cpg_pll_clk_determine_rate() local
70 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
71 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_clk_determine_rate()
72 max_mult = min(div64_ul(req->max_rate, prate), 128ULL); in cpg_pll_clk_determine_rate()
76 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
79 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
188 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
193 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
196 prate = rate; in cpg_z_clk_determine_rate()
199 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
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| H A D | clk-div6.c | 107 unsigned long prate, calc_rate, diff, best_rate, best_prate; in cpg_div6_clock_determine_rate() local
118 prate = clk_hw_get_rate(parent); in cpg_div6_clock_determine_rate()
119 if (!prate) in cpg_div6_clock_determine_rate()
122 min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL); in cpg_div6_clock_determine_rate()
123 max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64; in cpg_div6_clock_determine_rate()
127 div = cpg_div6_clock_calc_div(req->rate, prate); in cpg_div6_clock_determine_rate()
129 calc_rate = prate / div; in cpg_div6_clock_determine_rate()
135 best_prate = prate; in cpg_div6_clock_determine_rate()
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| H A D | rcar-gen2-cpg.c | 69 unsigned long prate = req->best_parent_rate; in cpg_z_clk_determine_rate() local
72 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); in cpg_z_clk_determine_rate()
73 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); in cpg_z_clk_determine_rate()
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
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| /linux/drivers/clk/spear/ |
| H A D | clk-frac-synth.c | 41 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, in frac_calc_rate() argument
47 prate /= 10000; in frac_calc_rate()
48 prate <<= 14; in frac_calc_rate()
49 prate /= (2 * rtbl[index].div); in frac_calc_rate()
50 prate *= 10000; in frac_calc_rate()
52 return prate; in frac_calc_rate()
95 unsigned long prate) in clk_frac_set_rate() argument
102 clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, in clk_frac_set_rate()
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| H A D | clk-gpt-synth.c | 31 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, in gpt_calc_rate() argument
37 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); in gpt_calc_rate()
39 return prate; in gpt_calc_rate()
80 unsigned long prate) in clk_gpt_set_rate() argument
87 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, in clk_gpt_set_rate()
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| H A D | clk-aux-synth.c | 41 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, in aux_calc_rate() argument
48 return (((prate / 10000) * rtbl[index].xscale) / in aux_calc_rate()
99 unsigned long prate) in clk_aux_set_rate() argument
106 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, in clk_aux_set_rate()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 169 unsigned long prate) in rockchip_rk3036_pll_recalc_rate() argument
173 u64 rate64 = prate; in rockchip_rk3036_pll_recalc_rate()
182 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
256 unsigned long prate) in rockchip_rk3036_pll_set_rate() argument
262 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
408 unsigned long prate) in rockchip_rk3066_pll_recalc_rate() argument
412 u64 rate64 = prate; in rockchip_rk3066_pll_recalc_rate()
419 return prate; in rockchip_rk3066_pll_recalc_rate()
491 unsigned long prate) in rockchip_rk3066_pll_set_rate() argument
497 __func__, clk_hw_get_name(hw), drate, prate); in rockchip_rk3066_pll_set_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-regmap-mux-div.c | 125 unsigned long prate, u32 src) in __mux_div_set_rate_and_parent() argument
187 unsigned long rate, unsigned long prate) in mux_div_set_rate() argument
191 return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); in mux_div_set_rate()
195 unsigned long prate, u8 index) in mux_div_set_rate_and_parent() argument
199 return __mux_div_set_rate_and_parent(hw, rate, prate, in mux_div_set_rate_and_parent()
203 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) in mux_div_recalc_rate() argument
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
30 rate64 = prate; in lgm_pll_calc_rate()
40 static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in lgm_pll_recalc_rate() argument
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 207 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
208 if (cfg_data->prate == 0) in exynos_cpuclk_pre_rate_change()
287 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_post_rate_change()
288 if (cfg_data->prate == 0) in exynos_cpuclk_post_rate_change()
334 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos5433_cpuclk_pre_rate_change()
335 if (cfg_data->prate == 0) in exynos5433_cpuclk_pre_rate_change()
495 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos850_cpuclk_pre_rate_change()
496 if (cfg_data->prate == 0) in exynos850_cpuclk_pre_rate_change()
691 for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; ) in exynos_register_cpu_clock()
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| H A D | clk-cpu.h | 43 unsigned long prate; member
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| /linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | dss.c | 518 unsigned long prate; in dss_div_calc() local
538 prate = clk_get_rate(dss.parent_clk); in dss_div_calc()
542 fckd_start = min(prate * m / fck_min, fckd_hw_max); in dss_div_calc()
543 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); in dss_div_calc()
546 fck = DIV_ROUND_UP(prate, fckd) * m; in dss_div_calc()
581 unsigned long max_dss_fck, prate; in dss_setup_default_clock() local
591 prate = clk_get_rate(dss.parent_clk); in dss_setup_default_clock()
593 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, in dss_setup_default_clock()
595 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; in dss_setup_default_clock()
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| /linux/drivers/peci/controller/ |
| H A D | peci-aspeed.c | 332 static int clk_aspeed_peci_get_div(unsigned long rate, const unsigned long *prate) in clk_aspeed_peci_get_div() argument
334 unsigned long this_rate = *prate / (4 * rate); in clk_aspeed_peci_get_div()
343 unsigned long prate) in clk_aspeed_peci_set_rate() argument
347 unsigned long this_rate = prate / (4 * rate); in clk_aspeed_peci_set_rate()
375 static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned long prate) in clk_aspeed_peci_recalc_rate() argument
394 return DIV_ROUND_UP_ULL(prate, div); in clk_aspeed_peci_recalc_rate()
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| /linux/drivers/clk/microchip/ |
| H A D | clk-mpfs.c | 147 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) in mpfs_clk_msspll_recalc_rate() argument
159 return prate * mult / (ref_div * MSSPLL_FIXED_DIV); in mpfs_clk_msspll_recalc_rate()
252 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) in mpfs_cfg_clk_recalc_rate() argument
262 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); in mpfs_cfg_clk_recalc_rate()
273 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) in mpfs_cfg_clk_set_rate() argument
281 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); in mpfs_cfg_clk_set_rate()
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| H A D | clk-mpfs-ccc.c | 74 static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in mpfs_ccc_pll_recalc_rate() argument
86 return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV); in mpfs_ccc_pll_recalc_rate()
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| /linux/drivers/clk/ |
| H A D | clk-sp7021.c | 433 unsigned long prate) in sp_pll_recalc_rate() argument
440 ret = prate; /* bypass */ in sp_pll_recalc_rate()
458 ret = prate >> r; in sp_pll_recalc_rate()
466 ret = (prate / m * n) >> r; in sp_pll_recalc_rate()
478 unsigned long prate) in sp_pll_set_rate() argument
486 if (rate == prate) { in sp_pll_set_rate()
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| /linux/include/trace/events/ |
| H A D | clk.h | 278 __field(unsigned long, prate )
286 __entry->prate = req->best_parent_rate;
293 (unsigned long)__entry->prate)
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-pll.c | 48 unsigned long prate, unsigned long *rate, in ipll_find_rate() argument
61 tmp = ipll_calc_rate(prate, pre, div, post); in ipll_find_rate()
284 unsigned long prate, in fpll_find_rate() argument
300 tmp = fpll_find_synthesizer(prate, trate, in fpll_find_rate()
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| /linux/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 86 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate) in i2s_pll_get_cfg() argument
88 switch (prate) { in i2s_pll_get_cfg()
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dss.c | 606 unsigned long prate; in dss_div_calc() local
626 prate = clk_get_rate(dss->parent_clk); in dss_div_calc()
630 fckd_start = min(prate * m / fck_min, fckd_hw_max); in dss_div_calc()
631 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); in dss_div_calc()
634 fck = DIV_ROUND_UP(prate, fckd) * m; in dss_div_calc()
673 unsigned long max_dss_fck, prate; in dss_setup_default_clock() local
683 prate = clk_get_rate(dss->parent_clk); in dss_setup_default_clock()
685 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier, in dss_setup_default_clock()
687 fck = DIV_ROUND_UP(prate, fck_div) in dss_setup_default_clock()
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| /linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 265 uint64_t prate, in clk_sscg_pll_find_setup() argument
279 if (prate == rate) { in clk_sscg_pll_find_setup()
286 ret = clk_sscg_pll2_find_setup(setup, &temp_setup, prate); in clk_sscg_pll_find_setup()
289 ret = clk_sscg_pll1_find_setup(setup, &temp_setup, prate); in clk_sscg_pll_find_setup()
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| /linux/drivers/clk/mmp/ |
| H A D | clk-frac.c | 79 unsigned long prate) in clk_factor_set_rate() argument
92 rate = (u64)prate * d->denominator; in clk_factor_set_rate()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-bcm2835.c | 1148 unsigned long *prate, in bcm2835_clock_choose_div_and_prate() argument
1161 *prate = clk_hw_get_rate(parent); in bcm2835_clock_choose_div_and_prate()
1162 *div = bcm2835_clock_choose_div(hw, rate, *prate); in bcm2835_clock_choose_div_and_prate()
1164 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); in bcm2835_clock_choose_div_and_prate()
1170 high = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1173 low = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1208 *prate = curdiv * best_rate; in bcm2835_clock_choose_div_and_prate()
1220 unsigned long prate, best_prate = 0; in bcm2835_clock_determine_rate() local
1246 &div, &prate, in bcm2835_clock_determine_rate()
1250 best_prate = prate; in bcm2835_clock_determine_rate()
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 1123 unsigned long prate, unsigned long rate, in samsung_mipi_dcphy_pll_round_rate() argument
1136 if (!prate) { in samsung_mipi_dcphy_pll_round_rate()
1146 fin = div64_ul(prate, MSEC_PER_SEC); in samsung_mipi_dcphy_pll_round_rate()
1447 unsigned long prate = clk_get_rate(samsung->ref_clk); in samsung_mipi_dcphy_pll_calc_rate() local
1455 fout = samsung_mipi_dcphy_pll_round_rate(samsung, prate, rate, in samsung_mipi_dcphy_pll_calc_rate()
1460 __func__, prate, rate); in samsung_mipi_dcphy_pll_calc_rate()
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