Home
last modified time | relevance | path

Searched refs:prate (Results 1 – 25 of 68) sorted by relevance

123

/linux/drivers/clk/spacemit/
H A Dccu_ddn.c25 static unsigned long ccu_ddn_calc_rate(unsigned long prate, unsigned long num, in ccu_ddn_calc_rate() argument
28 return prate * den / pre_div / num; in ccu_ddn_calc_rate()
32 unsigned long rate, unsigned long prate, in ccu_ddn_calc_best_rate() argument
35 rational_best_approximation(rate, prate / ddn->pre_div, in ccu_ddn_calc_best_rate()
39 return ccu_ddn_calc_rate(prate, *num, *den, ddn->pre_div); in ccu_ddn_calc_best_rate()
54 static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate) in ccu_ddn_recalc_rate() argument
64 return ccu_ddn_calc_rate(prate, num, den, ddn->pre_div); in ccu_ddn_recalc_rate()
68 unsigned long prate) in ccu_ddn_set_rate() argument
73 ccu_ddn_calc_best_rate(ddn, rate, prate, &num, &den); in ccu_ddn_set_rate()
/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c106 unsigned long prate; in cpg_pll_8_25_clk_determine_rate() local
108 prate = req->best_parent_rate * 2; in cpg_pll_8_25_clk_determine_rate()
109 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_8_25_clk_determine_rate()
110 max_mult = min(div64_ul(req->max_rate, prate), 256ULL); in cpg_pll_8_25_clk_determine_rate()
115 ni = div64_ul(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
121 nf = div64_ul((u64)(req->rate - prate * ni) << 24, in cpg_pll_8_25_clk_determine_rate()
125 ni = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
129 req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24); in cpg_pll_8_25_clk_determine_rate()
138 unsigned long prate = parent_rate * 2; in cpg_pll_8_25_clk_set_rate() local
144 ni = div64_ul(rate, prate); in cpg_pll_8_25_clk_set_rate()
[all …]
H A Drcar-gen3-cpg.c68 unsigned long prate; in cpg_pll_clk_determine_rate() local
70 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
71 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_clk_determine_rate()
72 max_mult = min(div64_ul(req->max_rate, prate), 128ULL); in cpg_pll_clk_determine_rate()
76 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
79 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
188 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
193 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
196 prate = rate; in cpg_z_clk_determine_rate()
199 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
[all …]
H A Dclk-div6.c107 unsigned long prate, calc_rate, diff, best_rate, best_prate; in cpg_div6_clock_determine_rate() local
118 prate = clk_hw_get_rate(parent); in cpg_div6_clock_determine_rate()
119 if (!prate) in cpg_div6_clock_determine_rate()
122 min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL); in cpg_div6_clock_determine_rate()
123 max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64; in cpg_div6_clock_determine_rate()
127 div = cpg_div6_clock_calc_div(req->rate, prate); in cpg_div6_clock_determine_rate()
129 calc_rate = prate / div; in cpg_div6_clock_determine_rate()
135 best_prate = prate; in cpg_div6_clock_determine_rate()
/linux/drivers/clk/spear/
H A Dclk-frac-synth.c41 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, in frac_calc_rate() argument
47 prate /= 10000; in frac_calc_rate()
48 prate <<= 14; in frac_calc_rate()
49 prate /= (2 * rtbl[index].div); in frac_calc_rate()
50 prate *= 10000; in frac_calc_rate()
52 return prate; in frac_calc_rate()
95 unsigned long prate) in clk_frac_set_rate() argument
102 clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, in clk_frac_set_rate()
H A Dclk-vco-pll.c67 unsigned long prate, int index, unsigned long *pll_rate) in pll_calc_rate() argument
69 unsigned long rate = prate; in pll_calc_rate()
82 unsigned long *prate, int *index) in clk_pll_round_rate_index() argument
89 if (!prate) { in clk_pll_round_rate_index()
96 vco_prev_rate = *prate; in clk_pll_round_rate_index()
97 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
103 *prate = vco_prev_rate; in clk_pll_round_rate_index()
145 unsigned long prate) in clk_pll_set_rate() argument
175 unsigned long prate, int index) in vco_calc_rate() argument
179 return pll_calc_rate(vco->rtbl, prate, index, NULL); in vco_calc_rate()
[all …]
H A Dclk-gpt-synth.c31 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, in gpt_calc_rate() argument
37 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); in gpt_calc_rate()
39 return prate; in gpt_calc_rate()
80 unsigned long prate) in clk_gpt_set_rate() argument
87 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, in clk_gpt_set_rate()
H A Dclk-aux-synth.c41 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, in aux_calc_rate() argument
48 return (((prate / 10000) * rtbl[index].xscale) / in aux_calc_rate()
99 unsigned long prate) in clk_aux_set_rate() argument
106 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, in clk_aux_set_rate()
/linux/drivers/rtc/
H A Drtc-ac100.c120 unsigned long prate) in ac100_clkout_recalc_rate() argument
128 if (prate != AC100_RTC_32K_RATE) { in ac100_clkout_recalc_rate()
131 prate = divider_recalc_rate(hw, prate, div, in ac100_clkout_recalc_rate()
138 return divider_recalc_rate(hw, prate, div, NULL, in ac100_clkout_recalc_rate()
144 unsigned long prate) in ac100_clkout_round_rate() argument
149 if (prate == AC100_RTC_32K_RATE) in ac100_clkout_round_rate()
150 return divider_round_rate(hw, rate, &prate, NULL, in ac100_clkout_round_rate()
155 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); in ac100_clkout_round_rate()
178 unsigned long tmp, prate; in ac100_clkout_determine_rate() local
200 prate = clk_hw_get_rate(parent); in ac100_clkout_determine_rate()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c169 unsigned long prate) in rockchip_rk3036_pll_recalc_rate() argument
173 u64 rate64 = prate; in rockchip_rk3036_pll_recalc_rate()
182 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
256 unsigned long prate) in rockchip_rk3036_pll_set_rate() argument
262 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
408 unsigned long prate) in rockchip_rk3066_pll_recalc_rate() argument
412 u64 rate64 = prate; in rockchip_rk3066_pll_recalc_rate()
419 return prate; in rockchip_rk3066_pll_recalc_rate()
491 unsigned long prate) in rockchip_rk3066_pll_set_rate() argument
497 __func__, clk_hw_get_name(hw), drate, prate); in rockchip_rk3066_pll_set_rate()
[all …]
/linux/drivers/clk/qcom/
H A Dclk-regmap-mux-div.c125 unsigned long prate, u32 src) in __mux_div_set_rate_and_parent() argument
187 unsigned long rate, unsigned long prate) in mux_div_set_rate() argument
191 return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); in mux_div_set_rate()
195 unsigned long prate, u8 index) in mux_div_set_rate_and_parent() argument
199 return __mux_div_set_rate_and_parent(hw, rate, prate, in mux_div_set_rate_and_parent()
203 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) in mux_div_recalc_rate() argument
H A Dclk-alpha-pll.c660 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) in alpha_pll_calc_rate() argument
662 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); in alpha_pll_calc_rate()
666 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, in alpha_pll_round_rate() argument
673 remainder = do_div(quotient, prate); in alpha_pll_round_rate()
684 remainder = do_div(quotient, prate); in alpha_pll_round_rate()
690 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); in alpha_pll_round_rate()
710 u64 a = 0, prate = parent_rate; in clk_alpha_pll_recalc_rate() local
736 return alpha_pll_calc_rate(prate, l, a, alpha_width); in clk_alpha_pll_recalc_rate()
817 unsigned long prate, in __clk_alpha_pll_set_rate() argument
825 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); in __clk_alpha_pll_set_rate()
[all …]
/linux/drivers/clk/x86/
H A Dclk-cgu.c148 unsigned long prate) in lgm_clk_divider_set_rate() argument
153 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
397 u64 prate; in lgm_clk_ddiv_recalc_rate() local
405 prate = (u64)parent_rate; in lgm_clk_ddiv_recalc_rate()
406 do_div(prate, div0); in lgm_clk_ddiv_recalc_rate()
407 do_div(prate, div1); in lgm_clk_ddiv_recalc_rate()
410 do_div(prate, ddiv->div); in lgm_clk_ddiv_recalc_rate()
411 prate *= ddiv->mult; in lgm_clk_ddiv_recalc_rate()
414 return prate; in lgm_clk_ddiv_recalc_rate()
464 unsigned long prate) in lgm_clk_ddiv_set_rate() argument
[all …]
H A Dclk-cgu-pll.c25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
30 rate64 = prate; in lgm_pll_calc_rate()
40 static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in lgm_pll_recalc_rate() argument
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
/linux/drivers/clk/samsung/
H A Dclk-cpu.c207 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
208 if (cfg_data->prate == 0) in exynos_cpuclk_pre_rate_change()
287 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_post_rate_change()
288 if (cfg_data->prate == 0) in exynos_cpuclk_post_rate_change()
334 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos5433_cpuclk_pre_rate_change()
335 if (cfg_data->prate == 0) in exynos5433_cpuclk_pre_rate_change()
495 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos850_cpuclk_pre_rate_change()
496 if (cfg_data->prate == 0) in exynos850_cpuclk_pre_rate_change()
691 for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; ) in exynos_register_cpu_clock()
H A Dclk-cpu.h43 unsigned long prate; member
/linux/drivers/clk/
H A Dclk-lmk04832.c375 unsigned long prate) in lmk04832_vco_recalc_rate() argument
406 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN, in lmk04832_vco_recalc_rate()
460 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate, in lmk04832_calc_pll2_params() argument
470 div = gcd(rate, prate); in lmk04832_calc_pll2_params()
473 pll2_r = DIV_ROUND_CLOSEST(prate, div); in lmk04832_calc_pll2_params()
491 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r); in lmk04832_calc_pll2_params()
524 unsigned long prate) in lmk04832_vco_set_rate() argument
542 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r); in lmk04832_vco_set_rate()
879 unsigned long prate) in lmk04832_sclk_recalc_rate() argument
893 return DIV_ROUND_CLOSEST(prate, sysref_div); in lmk04832_sclk_recalc_rate()
[all …]
H A Dclk-divider.c391 unsigned long rate, unsigned long *prate, in divider_round_rate_parent() argument
399 req.best_parent_rate = *prate; in divider_round_rate_parent()
406 *prate = req.best_parent_rate; in divider_round_rate_parent()
413 unsigned long rate, unsigned long *prate, in divider_ro_round_rate_parent() argument
421 req.best_parent_rate = *prate; in divider_ro_round_rate_parent()
428 *prate = req.best_parent_rate; in divider_ro_round_rate_parent()
H A Dclk-sp7021.c433 unsigned long prate) in sp_pll_recalc_rate() argument
440 ret = prate; /* bypass */ in sp_pll_recalc_rate()
458 ret = prate >> r; in sp_pll_recalc_rate()
466 ret = (prate / m * n) >> r; in sp_pll_recalc_rate()
478 unsigned long prate) in sp_pll_set_rate() argument
486 if (rate == prate) { in sp_pll_set_rate()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddss.c518 unsigned long prate; in dss_div_calc() local
538 prate = clk_get_rate(dss.parent_clk); in dss_div_calc()
542 fckd_start = min(prate * m / fck_min, fckd_hw_max); in dss_div_calc()
543 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); in dss_div_calc()
546 fck = DIV_ROUND_UP(prate, fckd) * m; in dss_div_calc()
581 unsigned long max_dss_fck, prate; in dss_setup_default_clock() local
591 prate = clk_get_rate(dss.parent_clk); in dss_setup_default_clock()
593 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, in dss_setup_default_clock()
595 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; in dss_setup_default_clock()
/linux/drivers/peci/controller/
H A Dpeci-aspeed.c332 static int clk_aspeed_peci_get_div(unsigned long rate, const unsigned long *prate) in clk_aspeed_peci_get_div() argument
334 unsigned long this_rate = *prate / (4 * rate); in clk_aspeed_peci_get_div()
343 unsigned long prate) in clk_aspeed_peci_set_rate() argument
347 unsigned long this_rate = prate / (4 * rate); in clk_aspeed_peci_set_rate()
375 static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned long prate) in clk_aspeed_peci_recalc_rate() argument
394 return DIV_ROUND_UP_ULL(prate, div); in clk_aspeed_peci_recalc_rate()
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c147 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) in mpfs_clk_msspll_recalc_rate() argument
159 return prate * mult / (ref_div * MSSPLL_FIXED_DIV); in mpfs_clk_msspll_recalc_rate()
252 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) in mpfs_cfg_clk_recalc_rate() argument
262 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); in mpfs_cfg_clk_recalc_rate()
273 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) in mpfs_cfg_clk_set_rate() argument
281 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); in mpfs_cfg_clk_set_rate()
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.c48 unsigned long prate, unsigned long *rate, in ipll_find_rate() argument
61 tmp = ipll_calc_rate(prate, pre, div, post); in ipll_find_rate()
284 unsigned long prate, in fpll_find_rate() argument
300 tmp = fpll_find_synthesizer(prate, trate, in fpll_find_rate()
/linux/include/trace/events/
H A Dclk.h278 __field(unsigned long, prate )
286 __entry->prate = req->best_parent_rate;
293 (unsigned long)__entry->prate)
/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c86 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate) in i2s_pll_get_cfg() argument
88 switch (prate) { in i2s_pll_get_cfg()

123