| /linux/arch/mips/ath79/ |
| H A D | clock.c | 238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
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| /linux/drivers/clk/mmp/ |
| H A D | clk-audio.c | 121 unsigned int postdiv; in audio_pll_recalc_rate() local
140 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
154 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
159 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
171 unsigned int postdiv; in audio_pll_determine_rate() local
177 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_determine_rate()
180 freq /= postdivs[postdiv].divisor; in audio_pll_determine_rate()
201 unsigned int postdiv; in audio_pll_set_rate() local
208 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
[all …]
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| H A D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 48 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
71 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
101 int postdiv) in mtk_pll_set_rate_regs() argument
111 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
145 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
165 *postdiv = 1 << val; in mtk_pll_calc_values()
168 *postdiv = 1 << val; in mtk_pll_calc_values()
169 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
187 u32 postdiv; in mtk_pll_set_rate() local
189 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
[all …]
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| H A D | clk-fhctl.c | 171 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) in __set_postdiv() argument
177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; in __set_postdiv()
182 unsigned int postdiv) in fhctl_hopping() argument
193 if (postdiv) { in fhctl_hopping()
196 if (postdiv > pll_postdiv) in fhctl_hopping()
197 __set_postdiv(pll, postdiv); in fhctl_hopping()
206 if (postdiv && postdiv < pll_postdiv) in fhctl_hopping()
207 __set_postdiv(pll, postdiv); in fhctl_hopping()
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| H A D | clk-pllfh.c | 33 u32 postdiv; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
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| H A D | clk-pllfh.h | 67 unsigned int postdiv);
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| H A D | clk-pll.h | 103 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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| /linux/drivers/clk/keystone/ |
| H A D | pll.c | 60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | keystone-pll.txt | 18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
19 for postdiv
28 fixed-postdiv = <2>;
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| /linux/drivers/clk/ |
| H A D | clk-tps68470.c | 35 unsigned int postdiv; member
173 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
174 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
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| H A D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | lontium-lt9611.c | 174 … lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
176 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
224 …lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
245 *postdiv = 1; in lt9611_pll_setup()
248 *postdiv = 2; in lt9611_pll_setup()
251 *postdiv = 4; in lt9611_pll_setup()
652 unsigned int postdiv; in lt9611_bridge_atomic_enable() local
669 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_atomic_enable()
671 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_atomic_enable()
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| /linux/drivers/clk/visconti/ |
| H A D | pll.c | 59 u32 postdiv, val; in visconti_pll_get_params() local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
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| /linux/drivers/video/fbdev/ |
| H A D | gxt4500.c | 239 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
249 postdiv = pdiv1 * pdiv2; in calc_pll()
250 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
258 n = intf * postdiv / period_ps; in calc_pll()
261 t = par->refclk_ps * m * postdiv / n; in calc_pll()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 683 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 907 u64 rate64 = prate, postdiv; in rockchip_rk3588_pll_recalc_rate() local
918 postdiv = cur.p * 65535; in rockchip_rk3588_pll_recalc_rate()
919 do_div(frac_rate64, postdiv); in rockchip_rk3588_pll_recalc_rate()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu74_discrete.h | 45 uint8_t postdiv; member
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| H A D | smu75_discrete.h | 44 uint8_t postdiv; /* divide by 2^n */ member
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv770_dpm.c | 344 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) in rv770_encode_yclk_post_div() argument
348 switch (postdiv) { in rv770_encode_yclk_post_div()
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