1d7964de8SJohnson Wang /* SPDX-License-Identifier: GPL-2.0-only */ 2d7964de8SJohnson Wang /* 3d7964de8SJohnson Wang * Copyright (c) 2022 MediaTek Inc. 4d7964de8SJohnson Wang * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> 5d7964de8SJohnson Wang */ 6d7964de8SJohnson Wang 7d7964de8SJohnson Wang #ifndef __CLK_PLLFH_H 8d7964de8SJohnson Wang #define __CLK_PLLFH_H 9d7964de8SJohnson Wang 10d7964de8SJohnson Wang #include "clk-pll.h" 11d7964de8SJohnson Wang 12d7964de8SJohnson Wang struct fh_pll_state { 13d7964de8SJohnson Wang void __iomem *base; 14d7964de8SJohnson Wang u32 fh_enable; 15d7964de8SJohnson Wang u32 ssc_rate; 16d7964de8SJohnson Wang }; 17d7964de8SJohnson Wang 18d7964de8SJohnson Wang struct fh_pll_data { 19d7964de8SJohnson Wang int pll_id; 20d7964de8SJohnson Wang int fh_id; 21*8da312d6SAngeloGioacchino Del Regno int fh_ver; 22d7964de8SJohnson Wang u32 fhx_offset; 23d7964de8SJohnson Wang u32 dds_mask; 24d7964de8SJohnson Wang u32 slope0_value; 25d7964de8SJohnson Wang u32 slope1_value; 26d7964de8SJohnson Wang u32 sfstrx_en; 27d7964de8SJohnson Wang u32 frddsx_en; 28d7964de8SJohnson Wang u32 fhctlx_en; 29d7964de8SJohnson Wang u32 tgl_org; 30d7964de8SJohnson Wang u32 dvfs_tri; 31d7964de8SJohnson Wang u32 pcwchg; 32d7964de8SJohnson Wang u32 dt_val; 33d7964de8SJohnson Wang u32 df_val; 34d7964de8SJohnson Wang u32 updnlmt_shft; 35d7964de8SJohnson Wang u32 msk_frddsx_dys; 36d7964de8SJohnson Wang u32 msk_frddsx_dts; 37d7964de8SJohnson Wang }; 38d7964de8SJohnson Wang 39d7964de8SJohnson Wang struct mtk_pllfh_data { 40d7964de8SJohnson Wang struct fh_pll_state state; 41d7964de8SJohnson Wang const struct fh_pll_data data; 42d7964de8SJohnson Wang }; 43d7964de8SJohnson Wang 44d7964de8SJohnson Wang struct fh_pll_regs { 45d7964de8SJohnson Wang void __iomem *reg_hp_en; 46d7964de8SJohnson Wang void __iomem *reg_clk_con; 47d7964de8SJohnson Wang void __iomem *reg_rst_con; 48d7964de8SJohnson Wang void __iomem *reg_slope0; 49d7964de8SJohnson Wang void __iomem *reg_slope1; 50d7964de8SJohnson Wang void __iomem *reg_cfg; 51d7964de8SJohnson Wang void __iomem *reg_updnlmt; 52d7964de8SJohnson Wang void __iomem *reg_dds; 53d7964de8SJohnson Wang void __iomem *reg_dvfs; 54d7964de8SJohnson Wang void __iomem *reg_mon; 55d7964de8SJohnson Wang }; 56d7964de8SJohnson Wang 57d7964de8SJohnson Wang struct mtk_fh { 58d7964de8SJohnson Wang struct mtk_clk_pll clk_pll; 59d7964de8SJohnson Wang struct fh_pll_regs regs; 60d7964de8SJohnson Wang struct mtk_pllfh_data *pllfh_data; 61d7964de8SJohnson Wang const struct fh_operation *ops; 62d7964de8SJohnson Wang spinlock_t *lock; 63d7964de8SJohnson Wang }; 64d7964de8SJohnson Wang 65d7964de8SJohnson Wang struct fh_operation { 66d7964de8SJohnson Wang int (*hopping)(struct mtk_fh *fh, unsigned int new_dds, 67d7964de8SJohnson Wang unsigned int postdiv); 68d7964de8SJohnson Wang int (*ssc_enable)(struct mtk_fh *fh, u32 rate); 69d7964de8SJohnson Wang }; 70d7964de8SJohnson Wang 71d7964de8SJohnson Wang int mtk_clk_register_pllfhs(struct device_node *node, 72d7964de8SJohnson Wang const struct mtk_pll_data *plls, int num_plls, 73d7964de8SJohnson Wang struct mtk_pllfh_data *pllfhs, int num_pllfhs, 74d7964de8SJohnson Wang struct clk_hw_onecell_data *clk_data); 75d7964de8SJohnson Wang 76d7964de8SJohnson Wang void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, 77d7964de8SJohnson Wang struct mtk_pllfh_data *pllfhs, int num_fhs, 78d7964de8SJohnson Wang struct clk_hw_onecell_data *clk_data); 79d7964de8SJohnson Wang 80d7964de8SJohnson Wang void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, 81d7964de8SJohnson Wang int num_pllfhs); 82d7964de8SJohnson Wang 83d7964de8SJohnson Wang #endif /* __CLK_PLLFH_H */ 84