Searched refs:pll_regs (Results 1 – 8 of 8) sorted by relevance
140 const struct cpu_dfs_regs *pll_regs; member150 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()151 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_recalc_rate()153 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; in ap_cpu_clk_recalc_rate()154 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; in ap_cpu_clk_recalc_rate()166 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()167 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()168 cpu_force_reg = clk->pll_regs->force_reg + in ap_cpu_clk_set_rate()169 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()170 cpu_ratio_reg = clk->pll_regs->ratio_reg + in ap_cpu_clk_set_rate()[all …]
46 uint8_t pll_regs[6]; member
15 (named "pll_regs") and the second one ("soc_ctrl") - for register
1113 static const u32 pll_regs[] = { variable1178 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h616_ccu_probe()1179 val = readl(reg + pll_regs[i]); in sun50i_h616_ccu_probe()1181 writel(val, reg + pll_regs[i]); in sun50i_h616_ccu_probe()
1160 static const u32 pll_regs[] = { variable1216 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h6_ccu_probe()1217 val = readl(reg + pll_regs[i]); in sun50i_h6_ccu_probe()1219 writel(val, reg + pll_regs[i]); in sun50i_h6_ccu_probe()
1322 static const u32 pll_regs[] = { variable1356 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun20i_d1_ccu_probe()1357 val = readl(reg + pll_regs[i]); in sun20i_d1_ccu_probe()1359 writel(val, reg + pll_regs[i]); in sun20i_d1_ccu_probe()
1636 static const u32 pll_regs[] = { variable1666 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun55i_a523_ccu_probe()1667 val = readl(reg + pll_regs[i]); in sun55i_a523_ccu_probe()1669 writel(val, reg + pll_regs[i]); in sun55i_a523_ccu_probe()
639 reg-names = "i2s_regs", "pll_regs", "soc_ctrl";