140 	const struct cpu_dfs_regs *pll_regs;  member
150 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_recalc_rate()
151 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_recalc_rate()
153 	cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;  in ap_cpu_clk_recalc_rate()
154 	cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;  in ap_cpu_clk_recalc_rate()
166 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_set_rate()
167 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
168 	cpu_force_reg = clk->pll_regs->force_reg +  in ap_cpu_clk_set_rate()
169 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
170 	cpu_ratio_reg = clk->pll_regs->ratio_reg +  in ap_cpu_clk_set_rate()
171 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
174 	reg &= ~(clk->pll_regs->divider_mask);  in ap_cpu_clk_set_rate()
175 	reg |= (divider << clk->pll_regs->divider_offset);  in ap_cpu_clk_set_rate()
181 	if (clk->pll_regs->divider_ratio) {  in ap_cpu_clk_set_rate()
183 		reg |= ((divider * clk->pll_regs->divider_ratio) <<  in ap_cpu_clk_set_rate()
190 			   clk->pll_regs->force_mask,  in ap_cpu_clk_set_rate()
191 			   clk->pll_regs->force_mask);  in ap_cpu_clk_set_rate()
194 			   BIT(clk->pll_regs->ratio_offset),  in ap_cpu_clk_set_rate()
195 			   BIT(clk->pll_regs->ratio_offset));  in ap_cpu_clk_set_rate()
197 	stable_bit = BIT(clk->pll_regs->ratio_state_offset +  in ap_cpu_clk_set_rate()
199 			 clk->pll_regs->ratio_state_cluster_offset);  in ap_cpu_clk_set_rate()
201 				       clk->pll_regs->ratio_state_reg, reg,  in ap_cpu_clk_set_rate()
208 			   BIT(clk->pll_regs->ratio_offset), 0);  in ap_cpu_clk_set_rate()
319 		ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);  in ap_cpu_clock_probe()