Home
last modified time | relevance | path

Searched refs:pll_clk (Results 1 – 25 of 43) sorted by relevance

12

/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c194 struct socfpga_pll *pll_clk; in s10_register_pll() local
199 pll_clk = kzalloc_obj(*pll_clk); in s10_register_pll()
200 if (WARN_ON(!pll_clk)) in s10_register_pll()
203 pll_clk->hw.reg = reg + clks->offset; in s10_register_pll()
216 pll_clk->hw.hw.init = &init; in s10_register_pll()
218 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; in s10_register_pll()
220 hw_clk = &pll_clk->hw.hw; in s10_register_pll()
224 kfree(pll_clk); in s10_register_pll()
234 struct socfpga_pll *pll_clk; in agilex_register_pll() local
239 pll_clk = kzalloc_obj(*pll_clk); in agilex_register_pll()
[all …]
H A Dclk-pll-a10.c71 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local
81 pll_clk = kzalloc_obj(*pll_clk); in __socfpga_pll_init()
82 if (WARN_ON(!pll_clk)) in __socfpga_pll_init()
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; in __socfpga_pll_init()
102 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
104 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init()
105 hw_clk = &pll_clk->hw.hw; in __socfpga_pll_init()
125 kfree(pll_clk); in __socfpga_pll_init()
H A Dclk-pll.c78 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local
87 pll_clk = kzalloc_obj(*pll_clk); in __socfpga_pll_init()
88 if (WARN_ON(!pll_clk)) in __socfpga_pll_init()
95 pll_clk->hw.reg = clk_mgr_base_addr + reg; in __socfpga_pll_init()
105 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
107 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init()
109 hw_clk = &pll_clk->hw.hw; in __socfpga_pll_init()
129 kfree(pll_clk); in __socfpga_pll_init()
/linux/drivers/clk/axs10x/
H A Dpll_clock.c221 struct axs10x_pll_clk *pll_clk; in axs10x_pll_clk_probe() local
225 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in axs10x_pll_clk_probe()
226 if (!pll_clk) in axs10x_pll_clk_probe()
229 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in axs10x_pll_clk_probe()
230 if (IS_ERR(pll_clk->base)) in axs10x_pll_clk_probe()
231 return PTR_ERR(pll_clk->base); in axs10x_pll_clk_probe()
233 pll_clk->lock = devm_platform_ioremap_resource(pdev, 1); in axs10x_pll_clk_probe()
234 if (IS_ERR(pll_clk->lock)) in axs10x_pll_clk_probe()
235 return PTR_ERR(pll_clk->lock); in axs10x_pll_clk_probe()
242 pll_clk->hw.init = &init; in axs10x_pll_clk_probe()
[all …]
H A Di2s_pll_clock.c170 struct i2s_pll_clk *pll_clk; in i2s_pll_clk_probe() local
173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in i2s_pll_clk_probe()
174 if (!pll_clk) in i2s_pll_clk_probe()
177 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in i2s_pll_clk_probe()
178 if (IS_ERR(pll_clk->base)) in i2s_pll_clk_probe()
179 return PTR_ERR(pll_clk->base); in i2s_pll_clk_probe()
188 pll_clk->hw.init = &init; in i2s_pll_clk_probe()
189 pll_clk->dev = dev; in i2s_pll_clk_probe()
191 clk = devm_clk_register(dev, &pll_clk->hw); in i2s_pll_clk_probe()
/linux/drivers/clk/
H A Dclk-hsdk-pll.c310 struct hsdk_pll_clk *pll_clk; in hsdk_pll_clk_probe() local
314 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in hsdk_pll_clk_probe()
315 if (!pll_clk) in hsdk_pll_clk_probe()
318 pll_clk->regs = devm_platform_ioremap_resource(pdev, 0); in hsdk_pll_clk_probe()
319 if (IS_ERR(pll_clk->regs)) in hsdk_pll_clk_probe()
320 return PTR_ERR(pll_clk->regs); in hsdk_pll_clk_probe()
333 pll_clk->hw.init = &init; in hsdk_pll_clk_probe()
334 pll_clk->dev = dev; in hsdk_pll_clk_probe()
335 pll_clk->pll_devdata = of_device_get_match_data(dev); in hsdk_pll_clk_probe()
337 if (!pll_clk->pll_devdata) { in hsdk_pll_clk_probe()
[all …]
H A Dclk-vt8500.c688 struct clk_pll *pll_clk; in vtwm_pll_clk_init() local
701 pll_clk = kzalloc_obj(*pll_clk); in vtwm_pll_clk_init()
702 if (WARN_ON(!pll_clk)) in vtwm_pll_clk_init()
705 pll_clk->reg = pmc_base + reg; in vtwm_pll_clk_init()
706 pll_clk->lock = &_lock; in vtwm_pll_clk_init()
707 pll_clk->type = pll_type; in vtwm_pll_clk_init()
718 pll_clk->hw.init = &init; in vtwm_pll_clk_init()
720 hw = &pll_clk->hw; in vtwm_pll_clk_init()
721 rc = clk_hw_register(NULL, &pll_clk->hw); in vtwm_pll_clk_init()
723 kfree(pll_clk); in vtwm_pll_clk_init()
H A Dclk-npcm8xx.c309 struct npcm8xx_clk_pll_data *pll_clk = &npcm8xx_pll_clks[i]; in npcm8xx_clk_probe() local
311 hw = npcm8xx_clk_register_pll(dev, clk_base + pll_clk->reg, in npcm8xx_clk_probe()
312 pll_clk->name, &pll_clk->parent, in npcm8xx_clk_probe()
313 pll_clk->flags); in npcm8xx_clk_probe()
316 pll_clk->hw = *hw; in npcm8xx_clk_probe()
/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c85 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_recalc_rate() local
86 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_recalc_rate()
93 nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg)); in cpg_pll_8_25_clk_recalc_rate()
103 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_determine_rate() local
105 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_determine_rate()
137 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_8_25_clk_set_rate() local
139 u32 cr0 = readl(pll_clk->pllcr0_reg); in cpg_pll_8_25_clk_set_rate()
158 if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) in cpg_pll_8_25_clk_set_rate()
161 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI8, in cpg_pll_8_25_clk_set_rate()
164 cpg_reg_modify(pll_clk->pllcr1_reg, CPG_PLLxCR1_NF25, in cpg_pll_8_25_clk_set_rate()
[all …]
H A Drcar-gen3-cpg.c55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_recalc_rate() local
58 mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; in cpg_pll_clk_recalc_rate()
60 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
66 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_determine_rate() local
70 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
86 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); in cpg_pll_clk_set_rate() local
90 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
93 val = readl(pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
96 writel(val, pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
99 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask) in cpg_pll_clk_set_rate()
[all …]
H A Dr9a09g077-cpg.c115 struct pll_clk { struct
124 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
585 struct pll_clk *pll_clk = to_pll(hw); in r9a09g077_cpg_pll3_clk_recalc_rate() local
592 ctr0 = readl(CPG_PLL3_VCO_CTR0(pll_clk->reg)); in r9a09g077_cpg_pll3_clk_recalc_rate()
593 ctr1 = readl(CPG_PLL3_VCO_CTR1(pll_clk->reg)); in r9a09g077_cpg_pll3_clk_recalc_rate()
608 struct pll_clk *pll_clk = to_pll(hw); in r9a09g077_cpg_pll3_determine_rate() local
611 if (req->rate == pll_clk->cur_rate) in r9a09g077_cpg_pll3_determine_rate()
615 if (!rzv2h_cpg_get_pll_pars(pll_clk->limits, &pll_clk->pll_parameters, in r9a09g077_cpg_pll3_determine_rate()
617 dev_dbg(pll_clk->dev, in r9a09g077_cpg_pll3_determine_rate()
622 req->rate = DIV_ROUND_CLOSEST_ULL(pll_clk->pll_parameters.freq_millihz, MILLI); in r9a09g077_cpg_pll3_determine_rate()
[all …]
H A Drzv2h-cpg.c136 struct pll_clk { struct
142 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
256 struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw)); in rzv2h_cpg_plldsi_div_determine_rate() local
265 dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance]; in rzv2h_cpg_plldsi_div_determine_rate()
298 struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw)); in rzv2h_cpg_plldsi_div_set_rate() local
307 dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance]; in rzv2h_cpg_plldsi_div_set_rate()
379 struct pll_clk *pll_clk = to_pll(hw); in rzv2h_cpg_plldsi_determine_rate() local
380 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_plldsi_determine_rate()
384 dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance]; in rzv2h_cpg_plldsi_determine_rate()
405 static int rzv2h_cpg_pll_set_rate(struct pll_clk *pll_clk, in rzv2h_cpg_pll_set_rate() argument
[all …]
H A Drzg2l-cpg.c1067 struct pll_clk { struct
1076 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
1081 struct pll_clk *pll_clk = to_pll(hw); in rzg2l_cpg_pll_clk_recalc_rate() local
1082 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg2l_cpg_pll_clk_recalc_rate()
1086 if (pll_clk->type != CLK_TYPE_SAM_PLL) in rzg2l_cpg_pll_clk_recalc_rate()
1089 val1 = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate()
1090 val2 = readl(priv->base + CPG_PLL_CLK2_OFFSET(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate()
1105 struct pll_clk *pll_clk = to_pll(hw); in rzg3s_cpg_pll_clk_recalc_rate() local
1106 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg3s_cpg_pll_clk_recalc_rate()
1110 setting = CPG_PLL1_SETTING_OFFSET(pll_clk->conf); in rzg3s_cpg_pll_clk_recalc_rate()
[all …]
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c47 static struct clk pll_clk = { variable
64 .parent = &pll_clk,
79 .parent = &pll_clk,
86 &pll_clk,
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
142 CLKDEV_CON_ID("pll_clk", &pll_clk),
H A Dclock-sh7264.c51 static struct clk pll_clk = { variable
60 &pll_clk,
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c82 static struct clk pll_clk = { variable
91 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
174 CLKDEV_CON_ID("pll_clk", &pll_clk),
226 pll_clk.parent = &dll_clk; in arch_clk_init()
228 pll_clk.parent = &extal_clk; in arch_clk_init()
H A Dclock-sh7366.c79 static struct clk pll_clk = { variable
88 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
188 CLKDEV_CON_ID("pll_clk", &pll_clk),
251 pll_clk.parent = &dll_clk; in arch_clk_init()
253 pll_clk.parent = &extal_clk; in arch_clk_init()
H A Dclock-sh7757.c37 static struct clk pll_clk = { variable
45 &pll_clk,
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
105 CLKDEV_CON_ID("pll_clk", &pll_clk),
H A Dclock-shx3.c36 static struct clk pll_clk = { variable
44 &pll_clk,
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
103 CLKDEV_CON_ID("pll_clk", &pll_clk),
H A Dclock-sh7343.c76 static struct clk pll_clk = { variable
85 &pll_clk,
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
122 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
190 CLKDEV_CON_ID("pll_clk", &pll_clk),
258 pll_clk.parent = &dll_clk; in arch_clk_init()
260 pll_clk.parent = &extal_clk; in arch_clk_init()
H A Dclock-sh7723.c83 static struct clk pll_clk = { variable
92 &pll_clk,
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
199 CLKDEV_CON_ID("pll_clk", &pll_clk),
274 pll_clk.parent = &dll_clk; in arch_clk_init()
276 pll_clk.parent = &extal_clk; in arch_clk_init()
H A Dclock-sh7785.c40 static struct clk pll_clk = { variable
48 &pll_clk,
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
119 CLKDEV_CON_ID("pll_clk", &pll_clk),
H A Dclock-sh7724.c85 static struct clk pll_clk = { variable
102 .parent = &pll_clk,
119 &pll_clk,
151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
264 CLKDEV_CON_ID("pll_clk", &pll_clk),
348 pll_clk.parent = &fll_clk; in arch_clk_init()
350 pll_clk.parent = &extal_clk; in arch_clk_init()
H A Dclock-sh7786.c42 static struct clk pll_clk = { variable
50 &pll_clk,
68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
128 CLKDEV_CON_ID("pll_clk", &pll_clk),
/linux/drivers/clk/ti/
H A Dfapll.c496 struct clk *pll_clk) in ti_fapll_synth_setup() argument
521 synth->clk_pll = pll_clk; in ti_fapll_synth_setup()
543 struct clk *pll_clk; in ti_fapll_setup() local
599 pll_clk = clk_register(NULL, &fd->hw); in ti_fapll_setup()
600 if (IS_ERR(pll_clk)) in ti_fapll_setup()
603 fd->outputs.clks[0] = pll_clk; in ti_fapll_setup()
642 output_name, name, pll_clk); in ti_fapll_setup()

12