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Searched refs:pipe_count (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c829 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
933 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1011 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1073 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1131 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1209 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1271 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1329 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1406 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
1468 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
/linux/sound/pci/mixart/
H A Dmixart_core.h233 u32 pipe_count; /* set to 1 for instance */ member
402 u32 pipe_count; /* set to 1 (array size !) */ member
H A Dmixart.c100 group_state.pipe_count = 1; in mixart_set_pipe_state()
123 group_state.pipe_count = 0; /* in case of start same command once again with pipe_count=0 */ in mixart_set_pipe_state()
566 stream_param.pipe_count = 1; /* set to 1 */ in mixart_set_format()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c786 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
877 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1125 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1138 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1201 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_dc_resource_mgmt.c248 const int pipe_count, in find_preferred_pipe_candidates() argument
270 for (i = 0; i < pipe_count; i++) { in find_preferred_pipe_candidates()
295 const int pipe_count, in find_last_resort_pipe_candidates() argument
312 for (i = 0; i < pipe_count; i++) { in find_last_resort_pipe_candidates()
H A Ddml2_wrapper_fpu.c484 …_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_count); in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c198 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn35_disable_otg_wa()
264 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dtb_dto()
302 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dpp_dto()
330 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Ddce_calcs.h485 int pipe_count,
/linux/kernel/rcu/
H A Drcutorture.c2557 int pipe_count; in rcu_torture_one_read_end() local
2562 pipe_count = READ_ONCE(rtorsp->p->rtort_pipe_count); in rcu_torture_one_read_end()
2563 if (pipe_count > RCU_TORTURE_PIPE_LEN) { in rcu_torture_one_read_end()
2566 pipe_count = RCU_TORTURE_PIPE_LEN; in rcu_torture_one_read_end()
2569 if (pipe_count > 1) { in rcu_torture_one_read_end()
2574 this_cpu_inc(rcu_torture_count[pipe_count]); in rcu_torture_one_read_end()
2607 if ((pipe_count > 1 || completed > 1) && !xchg(&err_segs_recorded, 1)) { in rcu_torture_one_read_end()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c122 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn31_disable_otg_wa()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c157 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn314_disable_otg_wa()