| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1142 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1421 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1643 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1686 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1758 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1781 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1803 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1832 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1880 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_apply_pipe_split_flags()
1900 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1133 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1214 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1254 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1256 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1278 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1280 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1365 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1420 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1544 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1630 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 836 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
940 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1023 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1085 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1143 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1223 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1285 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1343 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1421 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1483 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 829 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
933 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1011 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1073 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1131 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1209 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1271 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1329 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1406 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
1468 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 703 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
705 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
738 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
740 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
943 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
944 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1003 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1078 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1197 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1351 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 821 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
987 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1277 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1278 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1279 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1280 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1281 pool->pipe_count++; in underlay_create()
1376 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1377 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1453 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 742 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
744 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
777 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
779 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
998 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
999 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1059 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1134 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1256 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1419 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 342 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
487 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
564 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
575 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
609 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
683 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
686 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
707 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
736 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
818 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 320 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_init_hw()
1169 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_calculate_cab_allocation()
1384 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn401_optimize_bandwidth()
1765 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1777 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1796 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1983 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn401_reset_hw_ctx_wrap()
2350 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2364 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2379 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box_fpu()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box_fpu()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1104 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1214 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1216 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1238 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1240 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1337 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1467 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1631 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1674 pool->base.pipe_count = j; in dcn301_resource_construct()
1748 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1432 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1550 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1552 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1574 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1576 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1687 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1801 dc->res_pool->pipe_count); in dcn31_validate_bandwidth()
1938 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2118 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
2253 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1433 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_destruct()
1551 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1553 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1575 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1577 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1678 for (i = 0; i < dc->res_pool->pipe_count; i++) { in allow_pixel_rate_crb()
1713 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1779 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1910 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2068 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 954 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1388 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1391 pool->base.pipe_count = 3; in dcn10_resource_construct()
1606 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1675 pool->base.pipe_count = j; in dcn10_resource_construct()
1682 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1683 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1712 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 706 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
854 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
878 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
966 dc->res_pool->pipe_count); in dcn21_validate_bandwidth()
1448 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1613 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
1681 pool->base.pipe_count = j; in dcn21_resource_construct()
1732 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1479 for (i = 0; i < pool->base.pipe_count; i++) { in dcn351_resource_destruct()
1618 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1620 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1656 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1658 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
1870 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
2064 for (i = 0; i < pool->base.pipe_count; i++) { in dcn351_resource_construct()
2194 dc->caps.max_planes = pool->base.pipe_count; in dcn351_resource_construct()
2204 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn351_resource_construct()
2206 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn351_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1499 for (i = 0; i < pool->base.pipe_count; i++) { in dcn35_resource_destruct()
1638 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1640 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1676 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1678 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
1897 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
2092 for (i = 0; i < pool->base.pipe_count; i++) { in dcn35_resource_construct()
2222 dc->caps.max_planes = pool->base.pipe_count; in dcn35_resource_construct()
2231 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn35_resource_construct()
2233 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn35_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1486 for (i = 0; i < pool->base.pipe_count; i++) { in dcn36_resource_destruct()
1625 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1627 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1663 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1665 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
1867 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
2062 for (i = 0; i < pool->base.pipe_count; i++) { in dcn36_resource_construct()
2192 dc->caps.max_planes = pool->base.pipe_count; in dcn36_resource_construct()
2201 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn36_resource_construct()
2203 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn36_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 786 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
877 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1120 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1133 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1196 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /linux/sound/pci/mixart/ |
| H A D | mixart_core.h | 233 u32 pipe_count; /* set to 1 for instance */ member
402 u32 pipe_count; /* set to 1 (array size !) */ member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1491 for (i = 0; i < pool->base.pipe_count; i++) { in dcn314_resource_destruct()
1608 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1610 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1632 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1634 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1742 dc->res_pool->pipe_count); in dcn314_validate_bandwidth()
1864 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
2036 for (i = 0; i < pool->base.pipe_count; i++) { in dcn314_resource_construct()
2164 dc->caps.max_planes = pool->base.pipe_count; in dcn314_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1428 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_destruct()
1543 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1545 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1567 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1569 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1656 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn316_populate_dml_pipes_from_context()
1785 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1942 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_construct()
2059 dc->caps.max_planes = pool->base.pipe_count; in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 604 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
1083 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1173 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_construct()
1249 pool->base.pipe_count = j; in dce120_resource_construct()
1264 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
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