| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
151 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
331 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| H A D | dc.c | 1215 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
1405 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1509 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1581 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1673 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1676 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1699 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1702 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1711 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1725 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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| H A D | dc_resource.c | 1880 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1892 for (i = pool->pipe_count - 1; i >= 0; i--) { in resource_find_free_secondary_pipe_legacy()
1960 for (i = 0; i < pool->pipe_count; i++) { in recource_find_free_pipe_not_used_in_cur_res_ctx()
1983 for (i = 0; i < pool->pipe_count; i++) { in recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx()
2006 for (i = 0; i < pool->pipe_count; i++) { in resource_find_free_pipe_used_as_cur_sec_dpp()
2030 for (i = 0; i < pool->pipe_count; i++) { in resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine()
2053 for (i = 0; i < pool->pipe_count; i++) { in resource_find_any_free_pipe()
2650 for (i = 0; i < pool->pipe_count && result; i++) { in update_pipe_params_after_odm_slice_count_change()
2673 for (i = 0; i < pool->pipe_count && result; i++) { in update_pipe_params_after_mpc_slice_count_change()
2688 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 835 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
939 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1019 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1081 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1139 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1219 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1281 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1339 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1417 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
1479 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1258 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1339 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1379 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1381 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1403 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1405 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1491 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1547 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1671 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1757 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 793 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
795 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
828 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
830 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
1034 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1035 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1111 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1186 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1306 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1463 for (i = 0; i < (int)pool->pipe_count; i++) { in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 832 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
834 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
867 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
869 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
1089 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1090 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1167 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1242 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1365 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1531 for (i = 0; i < (int)pool->pipe_count; i++) { in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/ |
| H A D | dcn42_pg_cntl.c | 522 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_plane_otg_pg_control()
554 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_plane_otg_pg_control()
581 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_init_pg_status()
591 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_init_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1560 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1678 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1680 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1702 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1704 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1815 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1929 dc->res_pool->pipe_count); in dcn31_validate_bandwidth()
2067 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2249 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn31_resource_construct()
2384 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1562 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_destruct()
1680 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1682 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1704 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1706 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1807 for (i = 0; i < dc->res_pool->pipe_count; i++) { in allow_pixel_rate_crb()
1843 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1909 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
2041 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2202 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 786 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
877 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1125 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1138 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1201 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /linux/sound/pci/mixart/ |
| H A D | mixart_core.h | 233 u32 pipe_count; /* set to 1 for instance */ member
402 u32 pipe_count; /* set to 1 (array size !) */ member
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| H A D | mixart.c | 100 group_state.pipe_count = 1; in mixart_set_pipe_state()
123 group_state.pipe_count = 0; /* in case of start same command once again with pipe_count=0 */ in mixart_set_pipe_state()
566 stream_param.pipe_count = 1; /* set to 1 */ in mixart_set_format()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1555 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_destruct()
1670 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1672 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1694 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1696 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1784 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn316_populate_dml_pipes_from_context()
1914 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
2073 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn316_resource_construct()
2190 dc->caps.max_planes = pool->base.pipe_count; in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1607 for (i = 0; i < pool->base.pipe_count; i++) { in dcn36_resource_destruct()
1746 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1748 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1784 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1786 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
1989 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
2187 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn36_resource_construct()
2317 dc->caps.max_planes = pool->base.pipe_count; in dcn36_resource_construct()
2326 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn36_resource_construct()
2328 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn36_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1620 for (i = 0; i < pool->base.pipe_count; i++) { in dcn35_resource_destruct()
1759 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1761 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1797 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1799 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
2019 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
2217 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn35_resource_construct()
2347 dc->caps.max_planes = pool->base.pipe_count; in dcn35_resource_construct()
2356 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn35_resource_construct()
2358 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn35_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1600 for (i = 0; i < pool->base.pipe_count; i++) { in dcn351_resource_destruct()
1739 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create() local
1741 for (i = 0; i < pipe_count; i++) { in dcn35_dwbc_create()
1777 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create() local
1779 for (i = 0; i < pipe_count; i++) { in dcn35_mmhubbub_create()
1992 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
2189 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn351_resource_construct()
2319 dc->caps.max_planes = pool->base.pipe_count; in dcn351_resource_construct()
2329 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn351_resource_construct()
2331 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn351_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1620 for (i = 0; i < pool->base.pipe_count; i++) { in dcn314_resource_destruct()
1737 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1739 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1761 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1763 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1871 dc->res_pool->pipe_count); in dcn314_validate_bandwidth()
1994 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
2169 for (i = 0; i < (int)pool->base.pipe_count; i++) { in dcn314_resource_construct()
2297 dc->caps.max_planes = pool->base.pipe_count; in dcn314_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 345 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_setup_audio_dto()
395 if (i == dc->res_pool->pipe_count) { in dcn60_setup_audio_dto()
396 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_setup_audio_dto()
477 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_apply_ctx_to_hw()
503 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_apply_ctx_to_hw()
722 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1570 for (i = 0; i < pool->base.pipe_count; i++) { in dcn32_resource_destruct()
1899 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_add_phantom_pipes()
1925 dc->res_pool->pipe_count); in dml1_validate()
2075 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_populate_dml_pipes_from_context()
2089 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_populate_dml_pipes_from_context()
2369 pool->base.pipe_count = num_pipes; in dcn32_resource_construct()
2688 dc->caps.max_planes = pool->base.pipe_count; in dcn32_resource_construct()
2708 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn32_resource_construct()
2887 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2900 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe_check_mpo()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 248 const int pipe_count, in find_preferred_pipe_candidates() argument
270 for (i = 0; i < pipe_count; i++) { in find_preferred_pipe_candidates()
295 const int pipe_count, in find_last_resort_pipe_candidates() argument
312 for (i = 0; i < pipe_count; i++) { in find_last_resort_pipe_candidates()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 1555 for (i = 0; i < pool->base.pipe_count; i++) { in dcn42_resource_destruct()
1761 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn42_mmhubbub_create() local
1763 for (i = 0; i < pipe_count; i++) { in dcn42_mmhubbub_create()
2020 pool->base.pipe_count = num_pipes; in dcn42_resource_construct()
2389 dc->caps.max_planes = pool->base.pipe_count; in dcn42_resource_construct()
2397 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn42_resource_construct()
2403 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn42_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 1543 for (i = 0; i < pool->base.pipe_count; i++) { in dcn42b_resource_destruct()
1750 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn42b_mmhubbub_create() local
1752 for (i = 0; i < pipe_count; i++) { in dcn42b_mmhubbub_create()
1984 pool->base.pipe_count = num_pipes; in dcn42b_resource_construct()
2368 dc->caps.max_planes = pool->base.pipe_count; in dcn42b_resource_construct()
2377 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn42b_resource_construct()
2383 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn42b_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 91 for (i = 0; i < pool->pipe_count; i++) { in dcn30_log_color_state()
614 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { in dcn30_program_all_writeback_pipes_in_tree()
802 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_init_hw()
1217 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_hardware_release()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/ |
| H A D | dcn42_dccg.c | 306 for (i = 0; i < res_pool->pipe_count; i++) { in dccg42_init()
|