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Searched refs:pipe_count (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
358 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
369 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
H A Ddcn351_hwseq.c45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_surface.c73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
H A Ddc.c1224 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
1335 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1439 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1511 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1604 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1607 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1630 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1633 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1642 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1656 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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H A Ddc_resource.c1793 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1805 for (i = pool->pipe_count - 1; i >= 0; i--) { in resource_find_free_secondary_pipe_legacy()
1871 for (i = 0; i < pool->pipe_count; i++) { in recource_find_free_pipe_not_used_in_cur_res_ctx()
1894 for (i = 0; i < pool->pipe_count; i++) { in recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx()
1917 for (i = 0; i < pool->pipe_count; i++) { in resource_find_free_pipe_used_as_cur_sec_dpp()
1941 for (i = 0; i < pool->pipe_count; i++) { in resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine()
1964 for (i = 0; i < pool->pipe_count; i++) { in resource_find_any_free_pipe()
2562 for (i = 0; i < pool->pipe_count && result; i++) { in update_pipe_params_after_odm_slice_count_change()
2585 for (i = 0; i < pool->pipe_count && result; i++) { in update_pipe_params_after_mpc_slice_count_change()
2600 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
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H A Ddc_stream.c486 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
H A Ddc_hw_sequencer.c668 for (int i = 0; i < dc->res_pool->pipe_count; i++) { in set_p_state_switch_method()
2165 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { in hwss_wait_for_outstanding_hw_updates()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c316 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_init_hw()
1246 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_calculate_cab_allocation()
1461 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn401_optimize_bandwidth()
1837 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1849 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1868 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
2039 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn401_reset_hw_ctx_wrap()
2397 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2411 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2426 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c88 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
2063 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2075 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2090 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2097 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2115 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2123 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2151 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2164 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2257 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn351_update_bw_bounding_box_fpu()
486 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
589 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
616 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_decide_zstate_support()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn35_update_bw_bounding_box_fpu()
453 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
556 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
586 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_decide_zstate_support()
/linux/sound/pci/mixart/
H A Dmixart_core.h233 u32 pipe_count; /* set to 1 for instance */ member
402 u32 pipe_count; /* set to 1 (array size !) */ member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c287 for (i = 0; i < res_pool->pipe_count; i++) { in dcn201_init_hw()
340 for (i = 0; i < res_pool->pipe_count; i++) { in dcn201_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c163 for (i = 0; i < dc->res_pool->pipe_count; i++) { in ramp_up_dispclk_with_dpp()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Ddce_calcs.h485 int pipe_count,
/linux/kernel/rcu/
H A Drcutorture.c2367 int pipe_count; in rcu_torture_one_read_end() local
2372 pipe_count = READ_ONCE(rtorsp->p->rtort_pipe_count); in rcu_torture_one_read_end()
2373 if (pipe_count > RCU_TORTURE_PIPE_LEN) { in rcu_torture_one_read_end()
2376 pipe_count = RCU_TORTURE_PIPE_LEN; in rcu_torture_one_read_end()
2379 if (pipe_count > 1) { in rcu_torture_one_read_end()
2384 __this_cpu_inc(rcu_torture_count[pipe_count]); in rcu_torture_one_read_end()
2417 if ((pipe_count > 1 || completed > 1) && !xchg(&err_segs_recorded, 1)) { in rcu_torture_one_read_end()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c113 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in rn_update_clocks_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h6076 uint8_t pipe_count; member