| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
358 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
369 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
139 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
154 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 244 for (i = 0; i < res_pool->pipe_count; i++) in dcn35_init_hw()
263 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_hw()
709 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
736 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
764 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
827 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
1005 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_gate()
1057 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn35_calc_blocks_to_gate()
1080 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_ungate()
1169 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn35_calc_blocks_to_ungate()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1270 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1271 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1272 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1273 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1274 pool->pipe_count++; in underlay_create()
1368 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1369 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1444 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 342 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
487 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
564 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
575 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
609 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
681 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
684 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
705 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
734 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
816 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
180 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
212 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
238 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
270 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
300 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_color_state()
848 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
892 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
919 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
1122 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_reset_back_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn35_update_bw_bounding_box_fpu()
449 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
554 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
582 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 196 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
412 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 677 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
821 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
845 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
932 pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL); in dcn21_validate_bandwidth()
1406 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1570 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
1638 pool->base.pipe_count = j; in dcn21_resource_construct()
1681 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
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| /linux/sound/pci/mixart/ |
| H A D | mixart_core.h | 233 u32 pipe_count; /* set to 1 for instance */ member
402 u32 pipe_count; /* set to 1 (array size !) */ member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_soc_parameter_types.h | 164 unsigned int pipe_count; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 932 for (i = 0; i < pool->base.pipe_count; i++) { in dcn201_resource_destruct()
1103 pool->base.pipe_count = 4; in dcn201_resource_construct()
1194 dcn201_ip.max_num_dpp = pool->base.pipe_count; in dcn201_resource_construct()
1205 for (i = 0; i < pool->base.pipe_count; i++) { in dcn201_resource_construct()
1282 dc->caps.max_planes = pool->base.pipe_count; in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 781 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
902 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1240 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1328 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_construct()
1397 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1049 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
1064 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
1180 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1225 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1326 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1350 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1742 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_wm()
2115 memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st)); in dcn20_validate_bandwidth_fp()
2253 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 414 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_dmub_srv_populate_fams_pipe_info()
421 fams_pipe_data->pipe_count = pipe_idx; in dc_dmub_srv_populate_fams_pipe_info()
446 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
465 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
652 for (i = 0; i < dc->res_pool->pipe_count; i++) { in populate_subvp_cmd_vblank_pipe_info()
828 for (j = 0; j < dc->res_pool->pipe_count; j++) { in populate_subvp_cmd_pipe_info()
875 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
888 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| H A D | dcn4_soc_bb.h | 336 .pipe_count = 4,
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| H A D | dcn3_soc_bb.h | 374 .pipe_count = 4,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 337 dcn3_01_ip.max_num_dpp = pool->base.pipe_count; in dcn301_fpu_update_bw_bounding_box()
453 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_fpu_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1780 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
2180 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
2193 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2346 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2383 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2384 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2439 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2468 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2781 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2809 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_utils.c | 287 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_sub_vp_enabled()
521 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dml21_build_fams2_programming()
550 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dml21_build_fams2_programming()
|