| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
358 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
369 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| H A D | dc.c | 1226 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
1337 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1441 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1513 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1606 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1609 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1632 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1635 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1644 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1658 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1107 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1385 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1606 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1649 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1720 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1743 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1765 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1794 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1837 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_apply_pipe_split_flags()
1857 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 238 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
360 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
391 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
412 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
615 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
634 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
680 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_mall_sel()
740 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_program_mall_pipe_config()
955 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_init_hw()
1258 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_resync_fifo_dccg_dio()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 270 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_hw()
637 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
664 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
692 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
756 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_init_pipes()
942 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_gate()
969 for (j = 0; j < dc->res_pool->pipe_count; ++j) { in dcn35_calc_blocks_to_gate()
1008 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn35_calc_blocks_to_gate()
1031 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_ungate()
1120 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_calc_blocks_to_ungate()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1098 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1179 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1219 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1221 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1245 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1330 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1385 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1509 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1595 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 830 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
934 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1012 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1074 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1132 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1210 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1272 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1330 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1407 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
1469 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 836 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
940 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1023 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1085 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1143 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1223 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1285 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1343 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1421 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1483 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 675 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
677 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
712 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
914 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
915 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
969 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1044 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1162 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1308 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 819 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
984 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1271 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1272 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1273 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1274 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1275 pool->pipe_count++; in underlay_create()
1369 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1370 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1446 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 714 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
716 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
749 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
751 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
969 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
970 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1025 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1100 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1221 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1376 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1069 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1179 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1181 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1205 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1302 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1431 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1587 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1630 pool->base.pipe_count = j; in dcn301_resource_construct()
1704 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_init_hw()
1253 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_calculate_cab_allocation()
1468 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn401_optimize_bandwidth()
1848 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1860 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
1879 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_interdependent_update_lock()
2050 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn401_reset_hw_ctx_wrap()
2408 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2422 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn401_program_front_end_for_ctx()
2437 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn401_program_front_end_for_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 229 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
303 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
338 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
375 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
401 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
433 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
463 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_color_state()
1066 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
1110 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
1137 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 89 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
2048 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2060 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2075 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2082 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2100 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2108 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
2136 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2149 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
2242 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1399 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1519 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1543 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1654 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1771 dc->res_pool->pipe_count); in dcn31_validate_bandwidth()
1900 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2067 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
2202 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 920 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1345 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1348 pool->base.pipe_count = 3; in dcn10_resource_construct()
1563 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1632 pool->base.pipe_count = j; in dcn10_resource_construct()
1639 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1640 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1661 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn351_update_bw_bounding_box_fpu()
486 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
589 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
616 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn35_update_bw_bounding_box_fpu()
453 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
556 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
586 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1400 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_destruct()
1518 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1520 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1544 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1645 for (i = 0; i < dc->res_pool->pipe_count; i++) { in allow_pixel_rate_crb()
1680 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1746 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1871 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2016 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 680 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
822 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
846 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
934 dc->res_pool->pipe_count); in dcn21_validate_bandwidth()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1572 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
1640 pool->base.pipe_count = j; in dcn21_resource_construct()
1683 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
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