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Searched refs:pcie (Results 1 – 25 of 647) sorted by relevance

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/linux/drivers/pci/controller/
H A Dpcie-iproc.c400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
401 return pcie; in iproc_data()
409 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
412 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
415 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
418 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg()
423 return readl(pcie->base + offset); in iproc_pcie_read_reg()
426 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
429 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg()
434 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
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H A Dpcie-xilinx.c113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
133 static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie) in xilinx_pcie_clear_err_interrupts() argument
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
136 unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR); in xilinx_pcie_clear_err_interrupts()
141 pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK, in xilinx_pcie_clear_err_interrupts()
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H A Dpcie-rcar.c14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
39 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY) in rcar_pcie_wait_for_phyrdy()
48 int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) in rcar_pcie_wait_for_dl() argument
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H A Dpcie-iproc-bcma.c28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
56 pcie->base_addr = bdev->addr; in iproc_bcma_pcie_probe()
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H A DMakefile11 obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
12 obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
17 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
18 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
19 obj-$(CONFIG_PCIE_XILINX_CPM) += pcie-xilinx-cpm.o
20 obj-$(CONFIG_PCIE_XILINX_DMA_PL) += pcie-xilinx-dma-pl.o
25 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
26 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
27 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
28 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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H A Dpcie-iproc-msi.c94 struct iproc_pcie *pcie; member
132 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_read_reg() local
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
141 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_write_reg() local
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
488 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_irq_setup() local
500 dev_err(pcie->dev, in iproc_msi_irq_setup()
505 dev_err(pcie->dev, "failed to alloc CPU mask\n"); in iproc_msi_irq_setup()
519 int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node) in iproc_msi_init() argument
531 if (pcie->msi) in iproc_msi_init()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
103 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
108 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
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H A Dpcie-mobiveil.c28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
99 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) in mobiveil_csr_read() argument
105 addr = mobiveil_pcie_comp_addr(pcie, off); in mobiveil_csr_read()
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H A Dpcie-layerscape-gen4.c45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
70 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
72 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
77 static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_enable_interrupt() argument
79 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_enable_interrupt()
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H A Dpcie-mobiveil.h148 int (*interrupt_init)(struct mobiveil_pcie *pcie);
163 int (*link_up)(struct mobiveil_pcie *pcie);
179 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
180 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
181 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
182 int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
183 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
185 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
187 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
188 void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
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/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_mpu_writel() argument
116 writel_relaxed(val, pcie->mpu_base + reg); in visconti_mpu_writel()
119 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) in visconti_mpu_readl() argument
121 return readl_relaxed(pcie->mpu_base + reg); in visconti_mpu_readl()
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H A Dpcie-uniphier.c75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
104 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
109 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
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H A Dpcie-keembay.c72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
109 val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); in keembay_pcie_link_up()
116 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_start_link() local
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H A DMakefile2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
11 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
15 obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o
16 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
17 obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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H A Dpcie-armada8k.c73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
96 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
100 ret = phy_power_on(pcie->phy[i]); in armada8k_pcie_enable_phys()
102 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
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H A Dpci-layerscape-ep.c52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
62 static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) in ls_pcie_pf_lut_writel() argument
64 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_writel()
66 if (pcie->big_endian) in ls_pcie_pf_lut_writel()
74 struct ls_pcie_ep *pcie = dev_id; in ls_pcie_ep_event_handler() local
75 struct dw_pcie *pci = pcie->pci; in ls_pcie_ep_event_handler()
79 val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); in ls_pcie_ep_event_handler()
80 ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); in ls_pcie_ep_event_handler()
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H A Dpcie-al.c26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
153 static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id) in al_pcie_rev_id_get() argument
158 dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET + in al_pcie_rev_id_get()
174 dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n", in al_pcie_rev_id_get()
179 dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val); in al_pcie_rev_id_get()
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H A Dpcie-hisi.c65 struct hisi_pcie *pcie = cfg->priv; in hisi_pcie_map_bus() local
68 return pcie->reg_base + where; in hisi_pcie_map_bus()
78 struct hisi_pcie *pcie; in hisi_pcie_init() local
84 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in hisi_pcie_init()
85 if (!pcie) in hisi_pcie_init()
102 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res)); in hisi_pcie_init()
103 if (!pcie->reg_base) in hisi_pcie_init()
106 cfg->priv = pcie; in hisi_pcie_init()
126 struct hisi_pcie *pcie; in hisi_pcie_platform_init() local
130 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in hisi_pcie_platform_init()
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
58 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus()
71 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); in cdns_pci_map_bus()
82 static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) in cdns_pcie_host_training_complete() argument
91 lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); in cdns_pcie_host_training_complete()
103 static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) in cdns_pcie_host_wait_for_link() argument
105 struct device *dev = pcie->dev; in cdns_pcie_host_wait_for_link()
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H A Dpcie-cadence.h285 int (*start_link)(struct cdns_pcie *pcie);
286 void (*stop_link)(struct cdns_pcie *pcie);
287 bool (*link_up)(struct cdns_pcie *pcie);
288 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
329 struct cdns_pcie pcie; member
373 struct cdns_pcie pcie; member
391 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) in cdns_pcie_writel() argument
393 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
396 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_readl() argument
398 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
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H A Dpcie-cadence-plat.c22 struct cdns_pcie *pcie; member
31 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
73 rc->pcie.dev = dev; in cdns_plat_pcie_probe()
74 rc->pcie.ops = &cdns_plat_ops; in cdns_plat_pcie_probe()
75 cdns_plat_pcie->pcie = &rc->pcie; in cdns_plat_pcie_probe()
77 ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); in cdns_plat_pcie_probe()
100 ep->pcie.dev = dev; in cdns_plat_pcie_probe()
101 ep->pcie.ops = &cdns_plat_ops; in cdns_plat_pcie_probe()
102 cdns_plat_pcie->pcie = &ep->pcie; in cdns_plat_pcie_probe()
104 ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); in cdns_plat_pcie_probe()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dpcie.c53 if (!pci->func->pcie.version) in nvkm_pcie_get_version()
56 return pci->func->pcie.version(pci); in nvkm_pcie_get_version()
62 if (!pci->func->pcie.version_supported) in nvkm_pcie_get_max_version()
65 return pci->func->pcie.version_supported(pci); in nvkm_pcie_get_max_version()
71 if (!pci->func->pcie.set_version) in nvkm_pcie_set_version()
75 pci->func->pcie.set_version(pci, version); in nvkm_pcie_set_version()
82 if (pci->func->pcie.max_speed) in nvkm_pcie_oneinit()
84 nvkm_pcie_speeds[pci->func->pcie.max_speed(pci)]); in nvkm_pcie_oneinit()
105 if (pci->func->pcie.init) in nvkm_pcie_init()
106 pci->func->pcie.init(pci); in nvkm_pcie_init()
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/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_hw_stats.c121 struct fbnic_pcie_stats *pcie) in fbnic_reset_pcie_stats_asic() argument
126 &pcie->ob_rd_tlp); in fbnic_reset_pcie_stats_asic()
130 &pcie->ob_rd_dword); in fbnic_reset_pcie_stats_asic()
134 &pcie->ob_cpl_tlp); in fbnic_reset_pcie_stats_asic()
138 &pcie->ob_cpl_dword); in fbnic_reset_pcie_stats_asic()
142 &pcie->ob_wr_tlp); in fbnic_reset_pcie_stats_asic()
146 &pcie->ob_wr_dword); in fbnic_reset_pcie_stats_asic()
151 &pcie->ob_rd_no_tag); in fbnic_reset_pcie_stats_asic()
155 &pcie->ob_rd_no_cpl_cred); in fbnic_reset_pcie_stats_asic()
159 &pcie->ob_rd_no_np_cred); in fbnic_reset_pcie_stats_asic()
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/linux/Documentation/devicetree/bindings/pci/
H A Daxis,artpec6-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
21 - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
26 pcie@f8050000 {
27 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
49 axis,syscon-pcie = <&syscon>;
H A Dmediatek-pcie.txt5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
85 pcie: pcie@1a140000 {
86 compatible = "mediatek,mt7623-pcie";
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