| /linux/drivers/pci/controller/ |
| H A D | pcie-altera.c | 45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument
82 #define AGLX_RP_SECONDARY(pcie) \ argument
83 readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
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| H A D | pcie-mediatek-gen3.c | 167 int (*power_up)(struct mtk_gen3_pcie *pcie);
277 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
286 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
292 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
294 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
322 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, in mtk_pcie_set_trans_table() argument
346 dev_err(pcie->dev, "illegal table size %#llx\n", in mtk_pcie_set_trans_table()
351 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; in mtk_pcie_set_trans_table()
367 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", in mtk_pcie_set_trans_table()
379 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", in mtk_pcie_set_trans_table()
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| H A D | pcie-iproc.c | 401 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
402 return pcie; in iproc_data()
410 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
413 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
416 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
419 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg()
424 return readl(pcie->base + offset); in iproc_pcie_read_reg()
427 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
430 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg()
435 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
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| H A D | pcie-brcmstb.c | 237 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) argument
238 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) argument
239 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) argument
240 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) argument
241 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) argument
295 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
296 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
297 int (*post_setup)(struct brcm_pcie *pcie);
349 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
351 return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; in is_bmips()
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| H A D | pcie-rcar-host.c | 49 struct rcar_pcie pcie; member
92 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
95 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
117 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
124 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
126 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
131 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
138 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
143 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
153 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
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| H A D | pcie-rcar.c | 14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
39 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY) in rcar_pcie_wait_for_phyrdy()
48 int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) in rcar_pcie_wait_for_dl() argument
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| H A D | pcie-iproc-platform.c | 42 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
48 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_pltfm_pcie_probe()
52 pcie = pci_host_bridge_priv(bridge); in iproc_pltfm_pcie_probe()
54 pcie->dev = dev; in iproc_pltfm_pcie_probe()
55 pcie->type = (uintptr_t)of_device_get_match_data(dev); in iproc_pltfm_pcie_probe()
63 pcie->base = devm_pci_remap_cfgspace(dev, reg.start, in iproc_pltfm_pcie_probe()
65 if (!pcie->base) { in iproc_pltfm_pcie_probe()
69 pcie->base_addr = reg.start; in iproc_pltfm_pcie_probe()
81 pcie->ob.axi_offset = val; in iproc_pltfm_pcie_probe()
82 pcie->need_ob_cfg = true; in iproc_pltfm_pcie_probe()
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| H A D | pcie-iproc-bcma.c | 28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
56 pcie->base_addr = bdev->addr; in iproc_bcma_pcie_probe()
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| H A D | pcie-iproc-msi.c | 94 struct iproc_pcie *pcie; member
131 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_read_reg() local
133 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
140 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_write_reg() local
142 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
484 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_irq_setup() local
496 dev_err(pcie->dev, in iproc_msi_irq_setup()
501 dev_err(pcie->dev, "failed to alloc CPU mask\n"); in iproc_msi_irq_setup()
515 int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node) in iproc_msi_init() argument
527 if (pcie->msi) in iproc_msi_init()
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| H A D | pci-mvebu.c | 116 struct mvebu_pcie *pcie; member
343 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
350 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_child_rd_conf() local
354 port = mvebu_pcie_find_port(pcie, bus, devfn); in mvebu_pcie_child_rd_conf()
386 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_child_wr_conf() local
390 port = mvebu_pcie_find_port(pcie, bus, devfn); in mvebu_pcie_child_wr_conf()
462 dev_err(&port->pcie->pdev->dev, in mvebu_pcie_add_windows()
538 desired.base = port->pcie->io.start + desired.remap; in mvebu_pcie_handle_iobase_change()
960 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, in mvebu_pcie_find_port() argument
966 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_find_port()
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-intel-gw.c | 81 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
83 writel(val, pcie->app_base + ofs); in pcie_app_wr()
86 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
89 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
92 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
94 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
97 static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
99 dw_pcie_writel_dbi(&pcie->pci, ofs, val); in pcie_rc_cfg_wr()
102 static void pcie_rc_cfg_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_rc_cfg_wr_mask() argument
105 pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
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| H A D | pcie-amd-mdb.c | 77 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_mask() local
78 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_mask()
91 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
97 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_unmask() local
98 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_unmask()
111 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
147 struct amd_mdb_pcie *pcie = args; in dw_pcie_rp_intx() local
151 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in dw_pcie_rp_intx()
156 generic_handle_domain_irq(pcie->intx_domain, i); in dw_pcie_rp_intx()
178 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(d); in amd_mdb_event_irq_mask() local
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| H A D | pcie-visconti.c | 96 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
98 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
101 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
103 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
109 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
113 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_mpu_writel() argument
115 writel_relaxed(val, pcie->mpu_base + reg); in visconti_mpu_writel()
118 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) in visconti_mpu_readl() argument
120 return readl_relaxed(pcie->mpu_base + reg); in visconti_mpu_readl()
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| H A D | pcie-uniphier.c | 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
104 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
109 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
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| H A D | pcie-keembay.c | 70 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
72 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
76 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
86 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
90 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
94 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
99 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
104 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
107 val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); in keembay_pcie_link_up()
114 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_start_link() local
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| H A D | Makefile | 2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
4 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
5 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
6 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
7 obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
8 obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
9 obj-$(CONFIG_PCIE_ESWIN) += pcie-eswin.o
12 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
14 obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o
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| H A D | pcie-eswin.c | 94 struct eswin_pcie *pcie) in eswin_pcie_perst_reset() argument
100 dev_err(pcie->pci.dev, "Failed to assert PERST#\n"); in eswin_pcie_perst_reset()
109 dev_err(pcie->pci.dev, "Failed to deassert PERST#\n"); in eswin_pcie_perst_reset()
116 static void eswin_pcie_assert(struct eswin_pcie *pcie) in eswin_pcie_assert() argument
120 list_for_each_entry(port, &pcie->ports, list) in eswin_pcie_assert()
122 reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets); in eswin_pcie_assert()
125 static int eswin_pcie_parse_port(struct eswin_pcie *pcie, in eswin_pcie_parse_port() argument
128 struct device *dev = pcie->pci.dev; in eswin_pcie_parse_port()
150 pcie->pci.num_lanes = port->num_lanes; in eswin_pcie_parse_port()
153 list_add_tail(&port->list, &pcie->ports); in eswin_pcie_parse_port()
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| H A D | pcie-armada8k.c | 73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
96 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
100 ret = phy_power_on(pcie->phy[i]); in armada8k_pcie_enable_phys()
102 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
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| H A D | pcie-al.c | 26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
153 static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id) in al_pcie_rev_id_get() argument
158 dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET + in al_pcie_rev_id_get()
174 dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n", in al_pcie_rev_id_get()
179 dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val); in al_pcie_rev_id_get()
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| H A D | pcie-hisi.c | 66 struct hisi_pcie *pcie = cfg->priv; in hisi_pcie_map_bus() local
69 return pcie->reg_base + where; in hisi_pcie_map_bus()
79 struct hisi_pcie *pcie; in hisi_pcie_init() local
85 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in hisi_pcie_init()
86 if (!pcie) in hisi_pcie_init()
103 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res)); in hisi_pcie_init()
104 if (!pcie->reg_base) in hisi_pcie_init()
107 cfg->priv = pcie; in hisi_pcie_init()
127 struct hisi_pcie *pcie; in hisi_pcie_platform_init() local
131 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in hisi_pcie_platform_init()
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| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
86 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
87 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
104 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
109 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
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| H A D | pcie-layerscape-gen4.c | 45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
72 static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_enable_interrupt() argument
74 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_enable_interrupt()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/ |
| H A D | pcie.c | 53 if (!pci->func->pcie.version) in nvkm_pcie_get_version()
56 return pci->func->pcie.version(pci); in nvkm_pcie_get_version()
62 if (!pci->func->pcie.version_supported) in nvkm_pcie_get_max_version()
65 return pci->func->pcie.version_supported(pci); in nvkm_pcie_get_max_version()
71 if (!pci->func->pcie.set_version) in nvkm_pcie_set_version()
75 pci->func->pcie.set_version(pci, version); in nvkm_pcie_set_version()
82 if (pci->func->pcie.max_speed) in nvkm_pcie_oneinit()
84 nvkm_pcie_speeds[pci->func->pcie.max_speed(pci)]); in nvkm_pcie_oneinit()
105 if (pci->func->pcie.init) in nvkm_pcie_init()
106 pci->func->pcie.init(pci); in nvkm_pcie_init()
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-sg2042.c | 38 struct cdns_pcie *pcie; in sg2042_pcie_probe() local
52 pcie = &rc->pcie; in sg2042_pcie_probe()
53 pcie->dev = dev; in sg2042_pcie_probe()
55 platform_set_drvdata(pdev, pcie); in sg2042_pcie_probe()
61 ret = cdns_pcie_init_phy(dev, pcie); in sg2042_pcie_probe()
68 cdns_pcie_disable_phy(pcie); in sg2042_pcie_probe()
77 struct cdns_pcie *pcie = platform_get_drvdata(pdev); in sg2042_pcie_remove() local
80 rc = container_of(pcie, struct cdns_pcie_rc, pcie); in sg2042_pcie_remove()
83 cdns_pcie_disable_phy(pcie); in sg2042_pcie_remove()
88 struct cdns_pcie *pcie = dev_get_drvdata(dev); in sg2042_pcie_suspend_noirq() local
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-mv78460.dtsi | 70 pciec: pcie@82000000 {
71 compatible = "marvell,armada-xp-pcie";
116 pcie1: pcie@1,0 {
133 marvell,pcie-port = <0>;
134 marvell,pcie-lane = <0>;
144 pcie2: pcie@2,0 {
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <1>;
172 pcie3: pcie@3,0 {
189 marvell,pcie-port = <0>;
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