| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
289 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
290 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
294 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
302 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
[all …]
|
| /linux/arch/powerpc/kernel/ |
| H A D | rtas-proc.c | 508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_policy.c | 85 if (table->num_states == 0) { in insert_entry_into_table_sorted()
91 if (index >= (int) table->num_states) in insert_entry_into_table_sorted()
95 for (i = table->num_states; i > index; i--) { in insert_entry_into_table_sorted()
105 table->num_states++; in insert_entry_into_table_sorted()
113 if (table->num_states == 0) in remove_entry_from_table_at_index()
116 for (i = index; i < (int) table->num_states - 1; i++) { in remove_entry_from_table_at_index()
119 memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st)); in remove_entry_from_table_at_index()
163 p->out_states->num_states = 0; in dml2_policy_build_synthetic_soc_states()
221 for (i = p->out_states->num_states - 1; i >= 0; i--) { in dml2_policy_build_synthetic_soc_states()
233 for (i = p->out_states->num_states - 1; i >= 0; i--) { in dml2_policy_build_synthetic_soc_states()
[all …]
|
| H A D | dml2_translation_helper.c | 355 p->in_states->num_states = 2; in dml2_init_soc_states()
391 p->in_states->num_states = 2; in dml2_init_soc_states()
426 p->in_states->num_states = 2; in dml2_init_soc_states()
463 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
517 if (dml2->config.bbox_overrides.clks_table.num_states) { in dml2_init_soc_states()
518 p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; in dml2_init_soc_states()
561 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
580 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
600 p->out_states->num_states = p->in_states->num_states; in dml2_init_soc_states()
709 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states) in dml2_translate_soc_states() argument
[all …]
|
| H A D | dml2_translation_helper.h | 36 void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states);
|
| H A D | dml2_wrapper.c | 59 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
260 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
265 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { in calculate_lowest_supported_state_for_temp_read()
289 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
643 (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { in dml2_validate_and_build_resource()
644 lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in dml2_validate_and_build_resource()
|
| H A D | dml2_wrapper.h | 177 unsigned int num_states; member
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 122 .num_states = 1,
710 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
783 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
784 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
787 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
788 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
795 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
796 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
797 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_fpu_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_fpu_update_bw_bounding_box()
370 s[dcn3_01_soc.num_states] = in dcn301_fpu_update_bw_bounding_box()
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_fpu_update_bw_bounding_box()
372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_fpu_update_bw_bounding_box()
|
| /linux/drivers/regulator/ |
| H A D | irq_helpers.c | 62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
435 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1668 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1672 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1696 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1863 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2086 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2102 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2195 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2197 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2198 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
[all …]
|
| /linux/net/netfilter/ipvs/ |
| H A D | ip_vs_proto_ah_esp.c | 119 .num_states = 1,
141 .num_states = 1,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 143 .num_states = 1,
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
1411 if (new_vlevel < context->bw_ctx.dml.soc.num_states) { in try_odm_power_optimization_and_revalidate()
1467 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1487 …(*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpe… in dcn32_full_validate_bw_helper()
1503 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1527 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { in dcn32_full_validate_bw_helper()
1534 if (*vlevel < context->bw_ctx.dml.soc.num_states in dcn32_full_validate_bw_helper()
1565 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
2146 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw()
[all …]
|
| H A D | display_mode_vba_32.c | 112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 150 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
225 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
259 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 169 .num_states = 5,
413 .num_states = 5,
619 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
652 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
712 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
758 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
792 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
|
| H A D | display_mode_vba_31.c | 2119 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4058 for (i = 0; i < v->soc.num_states; i++) {
4068 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4069 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4076 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4077 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4084 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4085 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4219 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4220 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 166 .num_states = 5,
256 for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
266 closest_clk_lvl = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
317 dcn3_5_soc.num_states = clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
356 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn35_update_bw_bounding_box_fpu()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 292 .num_states = 5,
403 .num_states = 5,
514 .num_states = 5,
765 .num_states = 8
1852 unsigned int num_states) in dcn20_update_bounding_box() argument
1860 if (num_states == 0) in dcn20_update_bounding_box()
1876 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1907 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1911 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1922 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
[all …]
|
| H A D | dcn20_fpu.h | 61 unsigned int num_states);
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 78 uint32_t num_states; member
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1880 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1885 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2035 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2109 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2349 unsigned int num_states = 0; in init_soc_bounding_box() local
2356 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2371 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2373 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2572 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2580 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 230 unsigned int *clock_values_in_khz, unsigned int *num_states);
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_pp_smu.c | 709 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
717 num_states); in pp_nv_get_uclk_dpm_states()
|