| /linux/arch/powerpc/kernel/ |
| H A D | rtas-proc.c | 508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1667 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1671 …alidate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1685 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1695 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1862 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2084 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2100 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2193 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2195 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2196 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
[all …]
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| /linux/net/netfilter/ipvs/ |
| H A D | ip_vs_proto_ah_esp.c | 118 .num_states = 1,
140 .num_states = 1,
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| H A D | ip_vs_proto_udp.c | 478 .num_states = IP_VS_UDP_S_LAST,
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| H A D | ip_vs_proto_sctp.c | 573 .num_states = IP_VS_SCTP_S_LAST,
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| H A D | ip_vs_proto_tcp.c | 720 .num_states = IP_VS_TCP_S_LAST,
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| H A D | ip_vs_sync.c | 1000 if (state >= pp->num_states) { in ip_vs_process_message_v0()
1159 if (state >= pp->num_states) { in ip_vs_proc_sync_conn()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 169 .num_states = 5,
413 .num_states = 5,
619 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
652 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
712 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
758 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
792 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 204 .num_states = 8,
290 for (closest_clk_lvl = 0, j = dcn3_51_soc.num_states - 1; in dcn351_update_bw_bounding_box_fpu()
300 closest_clk_lvl = dcn3_51_soc.num_states - 1; in dcn351_update_bw_bounding_box_fpu()
351 dcn3_51_soc.num_states = clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
390 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn351_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 166 .num_states = 5,
256 for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
266 closest_clk_lvl = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
317 dcn3_5_soc.num_states = clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
356 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 78 uint32_t num_states; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1883 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1888 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2036 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2110 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2349 unsigned int num_states = 0; in init_soc_bounding_box() local
2356 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2371 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2373 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2573 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2581 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 1885 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3383 start_state = v->soc.num_states - 1; in dml30_ModeSupportAndSystemConfigurationFull()
3685 for (i = start_state; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3694 …utODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3695 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3700 …MCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3701 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3706 …MCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3707 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3815 …(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->so… in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_32.c | 112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 230 unsigned int *clock_values_in_khz, unsigned int *num_states);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.c | 291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
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| H A D | display_mode_structs.h | 187 unsigned int num_states; member
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| H A D | display_mode_vba.c | 376 for (i = 0; i < mode_lib->vba.soc.num_states; i++) in fetch_socbb_params()
394 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1330 if (loaded_bb->num_states == 1) { in set_wm_ranges()
1338 } else if (loaded_bb->num_states > 1) { in set_wm_ranges()
1339 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { in set_wm_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
905 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 2049 … navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) in navi10_get_uclk_dpm_states() argument
2057 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) in navi10_get_uclk_dpm_states()
2067 *num_states = num_discrete_levels; in navi10_get_uclk_dpm_states()
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| H A D | sienna_cichlid_ppt.c | 2009 …cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) in sienna_cichlid_get_uclk_dpm_states() argument
2018 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) in sienna_cichlid_get_uclk_dpm_states()
2029 *num_states = num_discrete_levels; in sienna_cichlid_get_uclk_dpm_states()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 197 .num_states = 4,
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 524 unsigned int *num_states);
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 1032 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
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