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Searched refs:num_states (Results 1 – 21 of 21) sorted by relevance

/linux/arch/powerpc/kernel/
H A Drtas-proc.c508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
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/linux/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c118 .num_states = 1,
140 .num_states = 1,
H A Dip_vs_proto_udp.c484 .num_states = IP_VS_UDP_S_LAST,
H A Dip_vs_proto_sctp.c579 .num_states = IP_VS_SCTP_S_LAST,
H A Dip_vs_proto_tcp.c727 .num_states = IP_VS_TCP_S_LAST,
H A Dip_vs_sync.c1000 if (state >= pp->num_states) { in ip_vs_process_message_v0()
1159 if (state >= pp->num_states) { in ip_vs_proc_sync_conn()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c169 .num_states = 5,
413 .num_states = 5,
619 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
652 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
712 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
758 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
792 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c204 .num_states = 8,
290 for (closest_clk_lvl = 0, j = dcn3_51_soc.num_states - 1; in dcn351_update_bw_bounding_box_fpu()
300 closest_clk_lvl = dcn3_51_soc.num_states - 1; in dcn351_update_bw_bounding_box_fpu()
351 dcn3_51_soc.num_states = clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
390 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn351_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c166 .num_states = 5,
256 for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
266 closest_clk_lvl = dcn3_5_soc.num_states - 1; in dcn35_update_bw_bounding_box_fpu()
317 dcn3_5_soc.num_states = clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
356 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn35_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h230 unsigned int *clock_values_in_khz, unsigned int *num_states);
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.c291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
H A Ddisplay_mode_structs.h187 unsigned int num_states; member
H A Ddisplay_mode_vba.c376 for (i = 0; i < mode_lib->vba.soc.num_states; i++) in fetch_socbb_params()
394 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c2006 unsigned int *num_states) in amdgpu_dpm_get_uclk_dpm_states() argument
2017 num_states); in amdgpu_dpm_get_uclk_dpm_states()
/linux/sound/soc/
H A Dsoc-pcm.c62 int num_states) in snd_soc_dpcm_check_state() argument
75 for (i = 0; i < num_states; i++) { in snd_soc_dpcm_check_state()
/linux/include/net/
H A Dip_vs.h480 u16 num_states; member
/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c3643 unsigned int *num_states) in smu_get_uclk_dpm_states() argument
3652 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); in smu_get_uclk_dpm_states()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core_structs.h1267 dml_uint_t num_states; /// <brief num of soc pwr states member
H A Ddisplay_mode_core.c10048 dml_print("DML::%s: state_idx=%u (num_states=%u)\n", __func__, state_idx, states->num_states); in dml_get_soc_state_bounding_box()
10050 if (state_idx >= (dml_uint_t)states->num_states) { in dml_get_soc_state_bounding_box()
10051 …("DML::%s: ERROR: Invalid state_idx=%u! num_states=%u\n", __func__, state_idx, states->num_states); in dml_get_soc_state_bounding_box()
10064 mode_lib->ms.max_state_idx = mode_lib->states.num_states - 1; in cache_ip_soc_cfg()
10069 …>ms.max_state = dml_get_soc_state_bounding_box(&mode_lib->states, mode_lib->states.num_states - 1); in cache_ip_soc_cfg()
10178 if (end_state_idx >= mode_lib->states.num_states) // idx is 0-based in mode_support_pwr_states()
10201 in_out_params->mode_lib->states.num_states - 1); in dml_mode_support_ex()