| /linux/drivers/input/joystick/ |
| H A D | adc-joystick.c | 25 unsigned int num_chans; member
26 struct adc_joystick_axis axes[] __counted_by(num_chans);
43 for (i = 0; i < joy->num_chans; i++) { in adc_joystick_poll()
64 for (i = 0; i < joy->num_chans; ++i) { in adc_joystick_handle()
145 if (num_axes != joy->num_chans) { in adc_joystick_set_axes()
147 num_axes, joy->num_chans); in adc_joystick_set_axes()
200 unsigned int *num_chans) in adc_joystick_count_channels() argument
223 *num_chans = i; in adc_joystick_count_channels()
234 unsigned int num_chans; in adc_joystick_probe() local
256 &num_chans); in adc_joystick_probe()
[all …]
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| /linux/drivers/mailbox/ |
| H A D | rockchip-mailbox.c | 31 int num_chans; member
84 writel_relaxed((1 << mb->mbox.num_chans) - 1, in rockchip_mbox_startup()
113 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_irq()
131 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_isr()
155 .num_chans = 4,
180 mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
185 mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
193 mb->mbox.num_chans = drv_data->num_chans; in rockchip_mbox_probe()
202 mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2); in rockchip_mbox_probe()
218 for (i = 0; i < mb->mbox.num_chans; i++) { in rockchip_mbox_probe()
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| H A D | qcom-ipcc.c | 57 int num_chans; member
177 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) { in qcom_ipcc_mbox_xlate()
188 if (chan_id >= mbox->num_chans) in qcom_ipcc_mbox_xlate()
220 ipcc->num_chans = 0; in qcom_ipcc_setup_mbox()
231 ipcc->num_chans++; in qcom_ipcc_setup_mbox()
236 if (!ipcc->num_chans) in qcom_ipcc_setup_mbox()
239 ipcc->chans = devm_kcalloc(dev, ipcc->num_chans, in qcom_ipcc_setup_mbox()
246 mbox->num_chans = ipcc->num_chans; in qcom_ipcc_setup_mbox()
321 if (ipcc->num_chans) in qcom_ipcc_probe()
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| H A D | arm_mhu_db.c | 65 for (i = 0; i < mbox->num_chans; i++) { in mhu_db_mbox_to_channel()
171 for (i = 0; i < mbox->num_chans; i++) in mhu_db_shutdown()
175 if (mbox->num_chans == i) { in mhu_db_shutdown()
213 for (i = 0; i < mbox->num_chans; i++) in mhu_db_mbox_xlate()
217 if (mbox->num_chans == i) { in mhu_db_mbox_xlate()
290 mhu->mbox.num_chans = max_chans; in mhu_db_probe()
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| H A D | mailbox-sti.c | 104 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_to_channel()
306 for (i = 0; i < mbox->num_chans; i++) in sti_mbox_shutdown_chan()
310 if (mbox->num_chans == i) { in sti_mbox_shutdown_chan()
340 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_xlate()
455 mbox->num_chans = STI_MBOX_CHAN_MAX; in sti_mbox_probe()
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| H A D | mailbox.c | 126 for (i = 0; i < mbox->num_chans; i++) { in txdone_hrtimer()
503 if (ind >= mbox->num_chans) in of_mbox_index_xlate()
520 if (!mbox || !mbox->dev || !mbox->ops || !mbox->num_chans) in mbox_controller_register()
543 for (i = 0; i < mbox->num_chans; i++) { in mbox_controller_register()
578 for (i = 0; i < mbox->num_chans; i++) in mbox_controller_unregister()
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| H A D | stm32-ipcc.c | 296 ipcc->controller.num_chans = ipcc->n_chans; in stm32_ipcc_probe()
297 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, in stm32_ipcc_probe()
305 for (i = 0; i < ipcc->controller.num_chans; i++) in stm32_ipcc_probe()
319 ipcc->controller.num_chans, ipcc->proc_id); in stm32_ipcc_probe()
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| H A D | tegra-hsp.c | 198 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { in tegra_hsp_doorbell_irq()
315 if (db->master >= chan->mbox->num_chans) { in tegra_hsp_doorbell_startup()
603 for (i = 0; i < mbox->num_chans; i++) { in tegra_hsp_db_xlate()
791 hsp->mbox_db.num_chans = 32; in tegra_hsp_probe()
795 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, in tegra_hsp_probe()
819 hsp->mbox_sm.num_chans = hsp->num_sm; in tegra_hsp_probe()
823 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, in tegra_hsp_probe()
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| H A D | imx-mailbox.c | 690 if (chan >= mbox->num_chans) { in imx_mu_specific_xlate()
719 if (chan >= mbox->num_chans) { in imx_mu_xlate()
788 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
812 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; in imx_mu_init_specific() local
814 for (i = 0; i < num_chans; i++) { in imx_mu_init_specific()
825 priv->mbox.num_chans = num_chans; in imx_mu_init_specific()
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| H A D | arm_mhuv2.c | 652 while (i < mhu->mbox.num_chans) { in get_irq_chan_stat_rx()
868 mhu->mbox.num_chans = channels; in mhuv2_verify_protocol()
880 chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL); in mhuv2_allocate_channels()
926 BUG_ON(chans - mbox->chans != mbox->num_chans); in mhuv2_allocate_channels()
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| /linux/sound/soc/codecs/ |
| H A D | audio-iio-aux.c | 30 unsigned int num_chans; member
31 struct audio_iio_aux_chan chans[] __counted_by(num_chans);
174 for (i = 0; i < iio_aux->num_chans; i++) { in audio_iio_aux_component_probe()
247 iio_aux->num_chans = count; in audio_iio_aux_probe()
249 const char **names __free(kfree) = kcalloc(iio_aux->num_chans, in audio_iio_aux_probe()
255 u32 *invert_ranges __free(kfree) = kcalloc(iio_aux->num_chans, in audio_iio_aux_probe()
262 names, iio_aux->num_chans); in audio_iio_aux_probe()
272 count = min_t(unsigned int, count, iio_aux->num_chans); in audio_iio_aux_probe()
279 for (i = 0; i < iio_aux->num_chans; i++) { in audio_iio_aux_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 173 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
175 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
207 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn303_fpu_update_bw_bounding_box()
208 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn303_fpu_update_bw_bounding_box()
349 if (dcn3_03_soc.num_chans <= 4) { in dcn303_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 175 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
178 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
211 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn302_fpu_update_bw_bounding_box()
212 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn302_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 149 .num_chans = 8,
168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
177 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * in get_optimal_ntuple()
192 memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * in calculate_net_bw_in_kbytes_sec()
583 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * in dcn321_get_optimal_dcfclk_fclk_for_uclk()
585 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * in dcn321_get_optimal_dcfclk_fclk_for_uclk()
684 if (dc->ctx->dc_bios->vram_info.num_chans) { in dcn321_update_bw_bounding_box_fpu()
686 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn321_update_bw_bounding_box_fpu()
688 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); in dcn321_update_bw_bounding_box_fpu()
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| /linux/drivers/edac/ |
| H A D | cell_edac.c | 175 int rc, chanmask, num_chans; in cell_edac_probe() local
200 num_chans = chanmask == 3 ? 2 : 1; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
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| H A D | versal_edac.c | 1081 u8 num_chans, num_csrows; in mc_probe() local
1101 num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); in mc_probe()
1102 num_chans++; in mc_probe()
1113 layers[1].size = num_chans; in mc_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_policy.c | 37 entry->dram_speed_mts = bw_on_sdp / (socbb->num_chans * in get_optimal_ntuple()
43 entry->dram_speed_mts = bw_on_fabric / (socbb->num_chans * in get_optimal_ntuple()
46 float bw_on_dram = (float)(entry->dram_speed_mts * socbb->num_chans * in get_optimal_ntuple()
57 float memory_bw_mbytes_sec = (float)(entry->dram_speed_mts * socbb->num_chans * in calculate_net_bw_in_mbytes_sec()
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| /linux/drivers/firmware/arm_scmi/ |
| H A D | raw_mode.c | 1091 u8 *channels, int num_chans) in scmi_raw_mode_setup() argument
1110 if (num_chans > 1) { in scmi_raw_mode_setup()
1113 for (i = 0; i < num_chans; i++) { in scmi_raw_mode_setup()
1167 u8 *channels, int num_chans, in scmi_raw_mode_init() argument
1187 ret = scmi_raw_mode_setup(raw, channels, num_chans); in scmi_raw_mode_init()
1215 if (num_chans > 1) { in scmi_raw_mode_init()
1221 for (i = 0; i < num_chans; i++) { in scmi_raw_mode_init()
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| H A D | raw_mode.h | 22 u8 *channels, int num_chans,
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| /linux/include/linux/ |
| H A D | mailbox_controller.h | 78 int num_chans; member
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 69 uint32_t num_chans; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/ |
| H A D | dcn10_fpu.c | 120 .num_chans = 2,
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | p2p.c | 643 static s32 brcmf_p2p_escan(struct brcmf_p2p_info *p2p, u32 num_chans, in brcmf_p2p_escan() argument
659 memsize += num_chans * sizeof(__le16); in brcmf_p2p_escan()
717 if (num_chans == SOCIAL_CHAN_CNT || num_chans == (SOCIAL_CHAN_CNT + 1)) in brcmf_p2p_escan()
719 else if (num_chans == AF_PEER_SEARCH_CNT) in brcmf_p2p_escan()
727 if (num_chans == 1) { in brcmf_p2p_escan()
744 sparams->channel_num = cpu_to_le32(num_chans & in brcmf_p2p_escan()
746 for (i = 0; i < num_chans; i++) in brcmf_p2p_escan()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 295 .num_chans = 4,
605 dcn3_1_soc.num_chans = bw_params->num_channels; in dcn31_update_bw_bounding_box()
679 dcn3_15_soc.num_chans = bw_params->num_channels; in dcn315_update_bw_bounding_box()
744 dcn3_16_soc.num_chans = bw_params->num_channels; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 202 dcn3_14_soc.num_chans = bw_params->num_channels; in dcn314_update_bw_bounding_box_fpu()
204 ASSERT(dcn3_14_soc.num_chans); in dcn314_update_bw_bounding_box_fpu()
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