| /linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7110-aon.c | 99 unsigned long mis; in jh7110_aon_irq_handler() local
104 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
105 for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) in jh7110_aon_irq_handler()
|
| H A D | pinctrl-starfive-jh7100.c | 1179 unsigned long mis; in starfive_gpio_irq_handler() local
1184 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1185 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1188 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1189 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
|
| /linux/drivers/clocksource/ |
| H A D | timer-sp.h | 42 int mis; member
58 void __iomem *mis; member
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 844 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
845 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
846 pool->base.mis[i] = NULL; in dce80_resource_destruct()
1030 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1031 if (pool->base.mis[i] == NULL) { in dce80_construct()
1230 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1231 if (pool->base.mis[i] == NULL) { in dce81_construct()
1428 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1429 if (pool->base.mis[i] == NULL) { in dce83_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 838 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
839 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
840 pool->base.mis[i] = NULL; in dce60_resource_destruct()
1019 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce60_construct()
1020 if (pool->base.mis[i] == NULL) { in dce60_construct()
1217 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce61_construct()
1218 if (pool->base.mis[i] == NULL) { in dce61_construct()
1414 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce64_construct()
1415 if (pool->base.mis[i] == NULL) { in dce64_construct()
|
| /linux/fs/ceph/ |
| H A D | metric.h | 68 __le64 mis; member
103 __le64 mis; member
|
| H A D | metric.c | 69 cap->mis = cpu_to_le64(percpu_counter_sum(&m->i_caps_mis)); in ceph_mdsc_send_metrics()
119 dlease->mis = cpu_to_le64(percpu_counter_sum(&m->d_lease_mis)); in ceph_mdsc_send_metrics()
|
| /linux/drivers/pinctrl/spear/ |
| H A D | pinctrl-plgpio.c | 49 u32 mis; /* mask interrupt status register */ member
386 regmap_read(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
392 regmap_write(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
512 plgpio->regs.mis = val; in plgpio_probe_dt()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 830 if (pool->base.mis[i] != NULL) { in dce110_resource_destruct()
831 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce110_resource_destruct()
832 pool->base.mis[i] = NULL; in dce110_resource_destruct()
1144 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1274 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1456 pool->base.mis[i] = dce110_mem_input_create(ctx, i); in dce110_resource_construct()
1457 if (pool->base.mis[i] == NULL) { in dce110_resource_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 795 if (pool->base.mis[i] != NULL) { in dce100_resource_destruct()
796 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce100_resource_destruct()
797 pool->base.mis[i] = NULL; in dce100_resource_destruct()
1140 pool->base.mis[i] = dce100_mem_input_create(ctx, i); in dce100_resource_construct()
1141 if (pool->base.mis[i] == NULL) { in dce100_resource_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 614 if (pool->base.mis[i] != NULL) { in dce120_resource_destruct()
615 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce120_resource_destruct()
616 pool->base.mis[i] = NULL; in dce120_resource_destruct()
1191 pool->base.mis[j] = dce120_mem_input_create(ctx, i); in dce120_resource_construct()
1193 if (pool->base.mis[j] == NULL) { in dce120_resource_construct()
|
| /linux/drivers/net/ethernet/realtek/rtase/ |
| H A D | rtase_main.c | 214 u32 len = ring->mis.len[entry]; in rtase_tx_clear_range()
221 ring->mis.len[entry] = 0; in rtase_tx_clear_range()
285 rtase_unmap_tx_skb(tp->pdev, ring->mis.len[entry], desc); in tx_handler()
286 ring->mis.len[entry] = 0; in tx_handler()
333 ring->mis.len[i] = 0; in rtase_tx_desc_init()
412 &ring->mis.data_phy_addr[i]); in rtase_rx_ring_fill()
547 ring->mis.data_phy_addr[entry], in rx_handler()
601 ring->mis.data_phy_addr[i] = 0; in rtase_rx_desc_init()
1292 ring->mis.len[entry] = len; in rtase_xmit_frags()
1391 ring->mis.len[entry] = len; in rtase_start_xmit()
|
| H A D | rtase.h | 298 } mis; member
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 795 if (pool->base.mis[i] != NULL) { in dce112_resource_destruct()
796 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce112_resource_destruct()
797 pool->base.mis[i] = NULL; in dce112_resource_destruct()
1345 pool->base.mis[i] = dce112_mem_input_create(ctx, i); in dce112_resource_construct()
1346 if (pool->base.mis[i] == NULL) { in dce112_resource_construct()
|
| /linux/arch/arm/boot/dts/st/ |
| H A D | spear310.dtsi | 109 st-plgpio,mis-reg = <0x60>;
|
| H A D | spear320.dtsi | 137 st-plgpio,mis-reg = <0x84>;
|
| H A D | spear1340.dtsi | 162 st-plgpio,mis-reg = <0xa0>;
|
| H A D | spear1310.dtsi | 302 st-plgpio,mis-reg = <0x10>;
|
| /linux/Documentation/staging/ |
| H A D | speculation.rst | 42 It is possible that a CPU mis-predicts the conditional branch, and
|
| /linux/drivers/media/dvb-frontends/ |
| H A D | stv0900_core.c | 1542 enum fe_stv0900_demod_num demod, int mis) in stv0900_set_mis() argument
1546 if (mis < 0 || mis > 255) { in stv0900_set_mis()
1550 dprintk("Enable MIS filtering - %d\n", mis); in stv0900_set_mis()
1552 stv0900_write_reg(intp, ISIENTRY, mis); in stv0900_set_mis()
|
| H A D | stv090x.c | 3441 static int stv090x_set_mis(struct stv090x_state *state, int mis) in stv090x_set_mis() argument
3445 if (mis < 0 || mis > 255) { in stv090x_set_mis()
3452 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); in stv090x_set_mis()
3457 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) in stv090x_set_mis()
|
| /linux/drivers/crypto/stm32/ |
| H A D | stm32-cryp.c | 169 u32 mis; member
2218 cryp->irq_status = stm32_cryp_read(cryp, cryp->caps->mis); in stm32_cryp_irq()
2505 .mis = UX500_CRYP_MIS,
2528 .mis = CRYP_MISR,
2551 .mis = CRYP_MISR,
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 245 struct mem_input *mis[MAX_PIPES]; member
|
| /linux/tools/perf/Documentation/ |
| H A D | tips.txt | 19 Profiling branch (mis)predictions with: perf record -b / perf report
|
| /linux/fs/befs/ |
| H A D | ChangeLog | 125 * Added workaround for mis-understanding of the nature of the b+trees used
|