Home
last modified time | relevance | path

Searched refs:mis (Results 1 – 25 of 37) sorted by relevance

12

/linux/drivers/clocksource/
H A Dtimer-sp.h42 int mis; member
58 void __iomem *mis; member
/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110-aon.c99 unsigned long mis; in jh7110_aon_irq_handler() local
104 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
105 for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) in jh7110_aon_irq_handler()
H A Dpinctrl-starfive-jh7100.c1179 unsigned long mis; in starfive_gpio_irq_handler() local
1184 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1185 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1188 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1189 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c846 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
847 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
848 pool->base.mis[i] = NULL; in dce80_resource_destruct()
1032 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1033 if (pool->base.mis[i] == NULL) { in dce80_construct()
1232 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1233 if (pool->base.mis[i] == NULL) { in dce81_construct()
1430 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1431 if (pool->base.mis[i] == NULL) { in dce83_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c839 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
840 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
841 pool->base.mis[i] = NULL; in dce60_resource_destruct()
1020 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce60_construct()
1021 if (pool->base.mis[i] == NULL) { in dce60_construct()
1218 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce61_construct()
1219 if (pool->base.mis[i] == NULL) { in dce61_construct()
1415 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce64_construct()
1416 if (pool->base.mis[i] == NULL) { in dce64_construct()
/linux/fs/ceph/
H A Dmetric.h70 __le64 mis; member
105 __le64 mis; member
H A Dmetric.c174 cap->mis = cpu_to_le64(percpu_counter_sum(&m->i_caps_mis)); in ceph_mdsc_send_metrics()
224 dlease->mis = cpu_to_le64(percpu_counter_sum(&m->d_lease_mis)); in ceph_mdsc_send_metrics()
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c49 u32 mis; /* mask interrupt status register */ member
386 regmap_read(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
392 regmap_write(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
512 plgpio->regs.mis = val; in plgpio_probe_dt()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c831 if (pool->base.mis[i] != NULL) { in dce110_resource_destruct()
832 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce110_resource_destruct()
833 pool->base.mis[i] = NULL; in dce110_resource_destruct()
1149 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1279 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1462 pool->base.mis[i] = dce110_mem_input_create(ctx, i); in dce110_resource_construct()
1463 if (pool->base.mis[i] == NULL) { in dce110_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c796 if (pool->base.mis[i] != NULL) { in dce100_resource_destruct()
797 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce100_resource_destruct()
798 pool->base.mis[i] = NULL; in dce100_resource_destruct()
1145 pool->base.mis[i] = dce100_mem_input_create(ctx, i); in dce100_resource_construct()
1146 if (pool->base.mis[i] == NULL) { in dce100_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c614 if (pool->base.mis[i] != NULL) { in dce120_resource_destruct()
615 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce120_resource_destruct()
616 pool->base.mis[i] = NULL; in dce120_resource_destruct()
1192 pool->base.mis[j] = dce120_mem_input_create(ctx, i); in dce120_resource_construct()
1194 if (pool->base.mis[j] == NULL) { in dce120_resource_construct()
/linux/drivers/net/ethernet/realtek/rtase/
H A Drtase_main.c214 u32 len = ring->mis.len[entry]; in rtase_tx_clear_range()
221 ring->mis.len[entry] = 0; in rtase_tx_clear_range()
285 rtase_unmap_tx_skb(tp->pdev, ring->mis.len[entry], desc); in tx_handler()
286 ring->mis.len[entry] = 0; in tx_handler()
333 ring->mis.len[i] = 0; in rtase_tx_desc_init()
412 &ring->mis.data_phy_addr[i]); in rtase_rx_ring_fill()
547 ring->mis.data_phy_addr[entry], in rx_handler()
601 ring->mis.data_phy_addr[i] = 0; in rtase_rx_desc_init()
1292 ring->mis.len[entry] = len; in rtase_xmit_frags()
1391 ring->mis.len[entry] = len; in rtase_start_xmit()
H A Drtase.h298 } mis; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c796 if (pool->base.mis[i] != NULL) { in dce112_resource_destruct()
797 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce112_resource_destruct()
798 pool->base.mis[i] = NULL; in dce112_resource_destruct()
1350 pool->base.mis[i] = dce112_mem_input_create(ctx, i); in dce112_resource_construct()
1351 if (pool->base.mis[i] == NULL) { in dce112_resource_construct()
/linux/arch/arm/boot/dts/st/
H A Dspear310.dtsi109 st-plgpio,mis-reg = <0x60>;
H A Dspear320.dtsi137 st-plgpio,mis-reg = <0x84>;
H A Dspear1340.dtsi162 st-plgpio,mis-reg = <0xa0>;
H A Dspear1310.dtsi302 st-plgpio,mis-reg = <0x10>;
/linux/Documentation/staging/
H A Dspeculation.rst42 It is possible that a CPU mis-predicts the conditional branch, and
/linux/drivers/media/dvb-frontends/
H A Dstv0900_core.c1542 enum fe_stv0900_demod_num demod, int mis) in stv0900_set_mis() argument
1546 if (mis < 0 || mis > 255) { in stv0900_set_mis()
1550 dprintk("Enable MIS filtering - %d\n", mis); in stv0900_set_mis()
1552 stv0900_write_reg(intp, ISIENTRY, mis); in stv0900_set_mis()
H A Dstv090x.c3441 static int stv090x_set_mis(struct stv090x_state *state, int mis) in stv090x_set_mis() argument
3445 if (mis < 0 || mis > 255) { in stv090x_set_mis()
3452 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); in stv090x_set_mis()
3457 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) in stv090x_set_mis()
/linux/tools/perf/Documentation/
H A Dtips.txt19 Profiling branch (mis)predictions with: perf record -b / perf report
/linux/fs/befs/
H A DChangeLog125 * Added workaround for mis-understanding of the nature of the b+trees used
/linux/tools/perf/
H A Ddesign.txt7 as instructions executed, cachemisses suffered, or branches mis-predicted -
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1527 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1584 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()

12