| /linux/drivers/clocksource/ |
| H A D | timer-sp.h | 42 int mis; member
58 void __iomem *mis; member
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| /linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7110-aon.c | 99 unsigned long mis; in jh7110_aon_irq_handler() local
104 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
105 for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) in jh7110_aon_irq_handler()
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| H A D | pinctrl-starfive-jh7110-sys.c | 366 unsigned long mis; in jh7110_sys_irq_handler() local
371 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); in jh7110_sys_irq_handler()
372 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
375 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); in jh7110_sys_irq_handler()
376 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
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| H A D | pinctrl-starfive-jh7100.c | 1179 unsigned long mis; in starfive_gpio_irq_handler() local
1184 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1185 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1188 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1189 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
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| /linux/fs/ceph/ |
| H A D | metric.h | 68 __le64 mis; member
103 __le64 mis; member
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| H A D | metric.c | 69 cap->mis = cpu_to_le64(percpu_counter_sum(&m->i_caps_mis)); in ceph_mdsc_send_metrics()
119 dlease->mis = cpu_to_le64(percpu_counter_sum(&m->d_lease_mis)); in ceph_mdsc_send_metrics()
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| /linux/drivers/pinctrl/spear/ |
| H A D | pinctrl-plgpio.c | 49 u32 mis; /* mask interrupt status register */ member
386 regmap_read(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
392 regmap_write(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
512 plgpio->regs.mis = val; in plgpio_probe_dt()
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| /linux/drivers/net/ethernet/realtek/rtase/ |
| H A D | rtase_main.c | 214 u32 len = ring->mis.len[entry]; in rtase_tx_clear_range()
221 ring->mis.len[entry] = 0; in rtase_tx_clear_range()
285 rtase_unmap_tx_skb(tp->pdev, ring->mis.len[entry], desc); in tx_handler()
286 ring->mis.len[entry] = 0; in tx_handler()
333 ring->mis.len[i] = 0; in rtase_tx_desc_init()
412 &ring->mis.data_phy_addr[i]); in rtase_rx_ring_fill()
547 ring->mis.data_phy_addr[entry], in rx_handler()
601 ring->mis.data_phy_addr[i] = 0; in rtase_rx_desc_init()
1292 ring->mis.len[entry] = len; in rtase_xmit_frags()
1391 ring->mis.len[entry] = len; in rtase_start_xmit()
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| H A D | rtase.h | 298 } mis; member
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| /linux/arch/arm/boot/dts/st/ |
| H A D | spear310.dtsi | 109 st-plgpio,mis-reg = <0x60>;
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| H A D | spear320.dtsi | 137 st-plgpio,mis-reg = <0x84>;
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| H A D | spear1340.dtsi | 162 st-plgpio,mis-reg = <0xa0>;
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| H A D | spear1310.dtsi | 302 st-plgpio,mis-reg = <0x10>;
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| /linux/Documentation/staging/ |
| H A D | speculation.rst | 42 It is possible that a CPU mis-predicts the conditional branch, and
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| /linux/drivers/media/dvb-frontends/ |
| H A D | stv0900_core.c | 1544 enum fe_stv0900_demod_num demod, int mis) in stv0900_set_mis() argument
1548 if (mis < 0 || mis > 255) { in stv0900_set_mis()
1552 dprintk("Enable MIS filtering - %d\n", mis); in stv0900_set_mis()
1554 stv0900_write_reg(intp, ISIENTRY, mis); in stv0900_set_mis()
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| H A D | stv090x.c | 3441 static int stv090x_set_mis(struct stv090x_state *state, int mis) in stv090x_set_mis() argument
3445 if (mis < 0 || mis > 255) { in stv090x_set_mis()
3452 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); in stv090x_set_mis()
3457 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) in stv090x_set_mis()
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| /linux/tools/perf/Documentation/ |
| H A D | tips.txt | 19 Profiling branch (mis)predictions with: perf record -b / perf report
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| /linux/fs/befs/ |
| H A D | ChangeLog | 125 * Added workaround for mis-understanding of the nature of the b+trees used
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| /linux/tools/perf/ |
| H A D | design.txt | 7 as instructions executed, cachemisses suffered, or branches mis-predicted -
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| /linux/drivers/clk/ |
| H A D | Kconfig | 400 Adapter driver so that any PWM output can be (mis)used as clock signal
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 3786 pipe_ctx->plane_res.mi = pool->mis[id_src[i]]; in acquire_resource_from_hw_enabled_state()
3931 pipe_ctx->plane_res.mi = pool->mis[pipe_idx]; in acquire_otg_master_pipe_for_stream()
5555 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
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| /linux/Documentation/filesystems/xfs/ |
| H A D | xfs-self-describing-metadata.rst | 100 mis-directed writes - a write might be misdirected to the wrong LUN and so be
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | spectre.rst | 469 check from being mis-speculated. The barrier is done by the
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| /linux/crypto/ |
| H A D | Kconfig | 574 Xtendend Encryption Tiny Algorithm is a mis-implementation
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| /linux/Documentation/translations/sp_SP/process/ |
| H A D | handling-regressions.rst | 683 importan como desarrollador del kernel, y yo quiero que mis usuarios
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