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Searched refs:memory_clock (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drv740_dpm.c93 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
104 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
186 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
204 memory_clock, false, &dividers); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
269 memory_clock); in rv740_populate_mclk_value()
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
408 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
412 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio()
415 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
H A Drv770_dpm.h184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
H A Dcypress_dpm.c473 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
500 memory_clock, strobe_mode, &dividers); in cypress_populate_mclk_value()
554 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value()
577 memory_clock); in cypress_populate_mclk_value()
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
614 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument
620 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
622 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
625 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
627 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio()
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H A Dcypress_dpm.h125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
H A Dsi_dpm.h230 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
231 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
H A Drv730_dpm.c117 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
133 memory_clock, false, &dividers); in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
H A Dci_dpm.c2453 const u32 memory_clock, in ci_register_patching_mc_arb() argument
2465 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2469 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2745 u32 memory_clock, in ci_calculate_mclk_params() argument
2763 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2790 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2792 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2817 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2832 u32 memory_clock, in ci_populate_single_memory_level() argument
2842 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
[all …]
H A Drv770_dpm.c319 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument
330 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
332 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
388 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
412 memory_clock, false, &dividers); in rv770_populate_mclk_value()
419 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value()
446 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value()
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
H A Dsi_dpm.c3760 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
3764 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
3766 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
3769 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
3773 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
3778 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
3780 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
3783 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
3785 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
3787 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
[all …]
H A Dni_dpm.c2162 u32 memory_clock, in ni_populate_mclk_value() argument
2184 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2238 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value()
2261 memory_clock); in ni_populate_mclk_value()
2285 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1046 uint32_t memory_clock, in iceland_calculate_mclk_params() argument
1068 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params()
1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio()
[all …]
H A Dci_smumgr.c1025 uint32_t memory_clock, in ci_calculate_mclk_params() argument
1046 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params()
1078 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1080 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1105 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1119 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument
1125 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1127 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1130 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio()
1132 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio()
[all …]
H A Dtonga_smumgr.c789 uint32_t memory_clock, in tonga_calculate_mclk_params() argument
811 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params()
871 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
873 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
906 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
920 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
931 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c3349 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3350 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3403 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3409 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
3420 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3429 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules()
3430 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
3443 smu7_ps->performance_levels[0].memory_clock) && in smu7_apply_state_adjust_rules()
3445 smu7_ps->performance_levels[1].memory_clock)) { in smu7_apply_state_adjust_rules()
3459 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
[all …]
H A Dppatomctrl.c212 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument
225 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770()
895 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument
899 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum()
941 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument
949 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
H A Dhardwaremanager.c401 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
411 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
H A Dsmu7_hwmgr.h55 uint32_t memory_clock; member
H A Dsmu10_hwmgr.c1122 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level()
1125 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
H A Dsmu8_hwmgr.c1635 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level()
1637 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
H A Dvega10_hwmgr.c5699 level->memory_clock = vega10_ps->performance_levels[i].mem_clock; in vega10_get_performance_level()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h272 uint32_t memory_clock; member
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c4284 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
4288 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
4290 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
4293 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
4297 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
4302 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
4304 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
4307 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4309 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
4311 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h269 uint32_t memory_clock; member
423 uint32_t memory_clock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsienna_cichlid_ppt.c1839 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1863 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
H A Dnavi10_ppt.c2137 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
2161 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()