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Searched refs:mclk_latency_table (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.h212 struct smu10_mclk_latency_table mclk_latency_table; member
H A Dsmu7_hwmgr.h217 struct smu7_mclk_latency_table mclk_latency_table; member
H A Dvega12_hwmgr.h317 struct vega12_mclk_latency_table mclk_latency_table; member
H A Dvega10_hwmgr.h315 struct vega10_mclk_latency_table mclk_latency_table; member
H A Dsmu7_hwmgr.c3438 for (i = 0; i < data->mclk_latency_table.count; i++) { in smu7_apply_state_adjust_rules()
3439 if (data->mclk_latency_table.entries[i].latency <= latency) { in smu7_apply_state_adjust_rules()
3442 if ((data->mclk_latency_table.entries[i].frequency >= in smu7_apply_state_adjust_rules()
3444 (data->mclk_latency_table.entries[i].frequency <= in smu7_apply_state_adjust_rules()
3446 mclk = data->mclk_latency_table.entries[i].frequency; in smu7_apply_state_adjust_rules()
3451 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) { in smu7_apply_state_adjust_rules()
5287 data->mclk_latency_table.count = 0; in smu7_get_mclks_with_latency()
5292 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = in smu7_get_mclks_with_latency()
5295 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = in smu7_get_mclks_with_latency()
5298 data->mclk_latency_table.count++; in smu7_get_mclks_with_latency()
H A Dvega20_hwmgr.h439 struct vega20_mclk_latency_table mclk_latency_table; member
H A Dvega12_hwmgr.c1904 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; in vega12_get_memclocks()
1906 data->mclk_latency_table.entries[i].latency = in vega12_get_memclocks()
1910 clocks->num_levels = data->mclk_latency_table.count = ucount; in vega12_get_memclocks()
2426 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { in vega12_apply_clocks_adjust_rules()
2427 if (data->mclk_latency_table.entries[i].latency <= latency) { in vega12_apply_clocks_adjust_rules()
H A Dvega10_hwmgr.c3406 for (i = 0; i < data->mclk_latency_table.count; i++) { in vega10_apply_state_adjust_rules()
3407 if ((data->mclk_latency_table.entries[i].latency <= latency) && in vega10_apply_state_adjust_rules()
3408 (data->mclk_latency_table.entries[i].frequency >= in vega10_apply_state_adjust_rules()
3410 (data->mclk_latency_table.entries[i].frequency <= in vega10_apply_state_adjust_rules()
3412 mclk = data->mclk_latency_table.entries[i].frequency; in vega10_apply_state_adjust_rules()
4440 data->mclk_latency_table.entries[j].frequency = in vega10_get_memclocks()
4443 data->mclk_latency_table.entries[j].latency = 25; in vega10_get_memclocks()
4447 clocks->num_levels = data->mclk_latency_table.count = j; in vega10_get_memclocks()
H A Dvega20_hwmgr.c2854 clocks->num_levels = data->mclk_latency_table.count = count; in vega20_get_memclocks()
2858 data->mclk_latency_table.entries[i].frequency = in vega20_get_memclocks()
2861 data->mclk_latency_table.entries[i].latency = in vega20_get_memclocks()
3808 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { in vega20_apply_clocks_adjust_rules()
3809 if (data->mclk_latency_table.entries[i].latency <= latency) { in vega20_apply_clocks_adjust_rules()