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/linux/drivers/media/radio/
H A Dradio-trust.c52 struct radio_isa_card isa; member
60 return tr ? &tr->isa : NULL; in trust_alloc()
67 #define TR_DELAY do { inb(tr->isa.io); inb(tr->isa.io); inb(tr->isa.io); } while (0)
68 #define TR_SET_SCL outb(tr->ioval |= 2, tr->isa.io)
69 #define TR_CLR_SCL outb(tr->ioval &= 0xfd, tr->isa.io)
70 #define TR_SET_SDA outb(tr->ioval |= 1, tr->isa.io)
71 #define TR_CLR_SDA outb(tr->ioval &= 0xfe, tr->isa.io)
119 static int trust_s_mute_volume(struct radio_isa_card *isa, bool mute, int vol) in trust_s_mute_volume() argument
121 struct trust *tr = container_of(isa, struct trust, isa); in trust_s_mute_volume()
124 outb(tr->ioval, isa->io); in trust_s_mute_volume()
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H A Dradio-aztech.c54 struct radio_isa_card isa; member
69 struct radio_isa_card *isa = handle; in aztech_set_pins() local
70 struct aztech *az = container_of(isa, struct aztech, isa); in aztech_set_pins()
80 outb_p(bits, az->isa.io); in aztech_set_pins()
87 return az ? &az->isa : NULL; in aztech_alloc()
90 static int aztech_s_frequency(struct radio_isa_card *isa, u32 freq) in aztech_s_frequency() argument
92 lm7000_set_freq(freq, isa, aztech_set_pins); in aztech_s_frequency()
97 static u32 aztech_g_rxsubchans(struct radio_isa_card *isa) in aztech_g_rxsubchans() argument
99 if (inb(isa->io) & AZTECH_BIT_MONO) in aztech_g_rxsubchans()
104 static u32 aztech_g_signal(struct radio_isa_card *isa) in aztech_g_signal() argument
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H A Dradio-typhoon.c72 struct radio_isa_card isa; member
80 return ty ? &ty->isa : NULL; in typhoon_alloc()
83 static int typhoon_s_frequency(struct radio_isa_card *isa, u32 freq) in typhoon_s_frequency() argument
105 outb_p((outval >> 8) & 0x01, isa->io + 4); in typhoon_s_frequency()
106 outb_p(outval >> 9, isa->io + 6); in typhoon_s_frequency()
107 outb_p(outval & 0xff, isa->io + 8); in typhoon_s_frequency()
111 static int typhoon_s_mute_volume(struct radio_isa_card *isa, bool mute, int vol) in typhoon_s_mute_volume() argument
113 struct typhoon *ty = container_of(isa, struct typhoon, isa); in typhoon_s_mute_volume()
119 outb_p(vol / 2, isa->io); /* Set the volume, high bit. */ in typhoon_s_mute_volume()
120 outb_p(vol % 2, isa->io + 2); /* Set the volume, low bit. */ in typhoon_s_mute_volume()
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-cpus.dtsi259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
309 riscv,isa = "rv64imafdc";
310 riscv,isa-base = "rv64i";
311 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
334 riscv,isa = "rv64imafdc";
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/linux/arch/powerpc/boot/dts/fsl/
H A De6500_power_isa.dtsi37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
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H A De5500_power_isa.dtsi37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
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H A De500mc_power_isa.dtsi37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
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H A De500v2_power_isa.dtsi37 power-isa-version = "2.03";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-e.le; // Embedded.Little-Endian
43 power-isa-e.pm; // Embedded.Performance Monitor
44 power-isa-ecl; // Embedded Cache Locking
45 power-isa-mmc; // Memory Coherence
46 power-isa-sp; // Signal Processing Engine
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H A De500v1_power_isa.dtsi37 power-isa-version = "2.03";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-e.le; // Embedded.Little-Endian
43 power-isa-e.pm; // Embedded.Performance Monitor
44 power-isa-ecl; // Embedded Cache Locking
45 power-isa-mmc; // Memory Coherence
46 power-isa-sp; // Signal Processing Engine
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/linux/arch/riscv/kernel/
H A Dcpufeature.c494 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap) in riscv_parse_isa_string() argument
502 isa += 4; in riscv_parse_isa_string()
504 while (*isa) { in riscv_parse_isa_string()
505 const char *ext = isa++; in riscv_parse_isa_string()
506 const char *ext_end = isa; in riscv_parse_isa_string()
521 for (; *isa && *isa != '_'; ++isa) in riscv_parse_isa_string()
534 ++isa; in riscv_parse_isa_string()
560 for (; *isa && *isa != '_'; ++isa) in riscv_parse_isa_string()
561 if (unlikely(!isalnum(*isa))) in riscv_parse_isa_string()
564 ext_end = isa; in riscv_parse_isa_string()
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H A Dcpu.c52 const char *isa; in riscv_early_of_processor_hartid() local
70 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
73 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) { in riscv_early_of_processor_hartid()
78 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) { in riscv_early_of_processor_hartid()
102 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid()
108 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) { in riscv_early_of_processor_hartid()
113 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) { in riscv_early_of_processor_hartid()
257 if (!__riscv_isa_extension_available(vendor_bitmap->isa, ext_data[j].id)) in print_vendor_isa()
370 print_isa(m, hart_isa[cpu_id].isa, cpu_id); in c_show()
/linux/arch/sh/
H A DMakefile20 isa-y := any
21 isa-$(CONFIG_SH_DSP) := sh
22 isa-$(CONFIG_CPU_SH2) := sh2
23 isa-$(CONFIG_CPU_SH2A) := sh2a
24 isa-$(CONFIG_CPU_SH3) := sh3
25 isa-$(CONFIG_CPU_SH4) := sh4
26 isa-$(CONFIG_CPU_SH4A) := sh4a
27 isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
29 isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
30 isa-y := $(isa-y)-up
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/linux/arch/riscv/kvm/
H A Dvcpu_vector.c21 unsigned long *isa = vcpu->arch.isa; in kvm_riscv_vcpu_vector_reset() local
25 if (riscv_isa_extension_available(isa, v)) { in kvm_riscv_vcpu_vector_reset()
41 unsigned long *isa) in kvm_riscv_vcpu_guest_vector_save() argument
44 if (riscv_isa_extension_available(isa, v)) in kvm_riscv_vcpu_guest_vector_save()
51 unsigned long *isa) in kvm_riscv_vcpu_guest_vector_restore() argument
54 if (riscv_isa_extension_available(isa, v)) in kvm_riscv_vcpu_guest_vector_restore()
141 unsigned long *isa = vcpu->arch.isa; in kvm_riscv_vcpu_get_reg_vector() local
151 if (!riscv_isa_extension_available(isa, v)) in kvm_riscv_vcpu_get_reg_vector()
167 unsigned long *isa = vcpu->arch.isa; in kvm_riscv_vcpu_set_reg_vector() local
177 if (!riscv_isa_extension_available(isa, v)) in kvm_riscv_vcpu_set_reg_vector()
H A Dvcpu_fp.c22 if (riscv_isa_extension_available(vcpu->arch.isa, f) || in kvm_riscv_vcpu_fp_reset()
23 riscv_isa_extension_available(vcpu->arch.isa, d)) in kvm_riscv_vcpu_fp_reset()
36 const unsigned long *isa) in kvm_riscv_vcpu_guest_fp_save() argument
39 if (riscv_isa_extension_available(isa, d)) in kvm_riscv_vcpu_guest_fp_save()
41 else if (riscv_isa_extension_available(isa, f)) in kvm_riscv_vcpu_guest_fp_save()
48 const unsigned long *isa) in kvm_riscv_vcpu_guest_fp_restore() argument
51 if (riscv_isa_extension_available(isa, d)) in kvm_riscv_vcpu_guest_fp_restore()
53 else if (riscv_isa_extension_available(isa, f)) in kvm_riscv_vcpu_guest_fp_restore()
90 riscv_isa_extension_available(vcpu->arch.isa, f)) { in kvm_riscv_vcpu_get_reg_fp()
101 riscv_isa_extension_available(vcpu->arch.isa, d)) { in kvm_riscv_vcpu_get_reg_fp()
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H A Dvcpu_onereg.c218 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
236 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_get_reg_config()
237 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
240 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_get_reg_config()
245 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_get_reg_config()
288 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_set_reg_config()
300 if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) in kvm_riscv_vcpu_set_reg_config()
320 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | in kvm_riscv_vcpu_set_reg_config()
322 vcpu->arch.isa[0] = reg_val; in kvm_riscv_vcpu_set_reg_config()
329 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_set_reg_config()
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/linux/arch/mips/include/asm/
H A Dcpu-features.h18 #define __isa(isa) (cpu_data[0].isa_level & (isa)) argument
32 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) argument
33 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) argument
42 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) argument
43 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) argument
53 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) argument
54 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) argument
60 #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) argument
61 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) argument
62 #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) argument
/linux/arch/arm/mach-footbridge/
H A DMakefile8 obj-y := common.o isa-irq.o isa.o isa-rtc.o dma-isa.o
15 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
85 riscv,isa = "rv64imafdc";
86 riscv,isa-base = "rv64i";
87 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
112 riscv,isa = "rv64imafdc";
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H A Dfu740-c000.dtsi33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
87 riscv,isa = "rv64imafdc";
88 riscv,isa-base = "rv64i";
89 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
114 riscv,isa = "rv64imafdc";
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/linux/arch/riscv/include/asm/
H A Dkvm_vcpu_fp.h25 const unsigned long *isa);
27 const unsigned long *isa);
35 const unsigned long *isa) in kvm_riscv_vcpu_guest_fp_save() argument
40 const unsigned long *isa) in kvm_riscv_vcpu_guest_fp_restore() argument
H A Dkvm_vcpu_vector.h31 unsigned long *isa);
33 unsigned long *isa);
48 unsigned long *isa) in kvm_riscv_vcpu_guest_vector_save() argument
53 unsigned long *isa) in kvm_riscv_vcpu_guest_vector_restore() argument
/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts38 isa = <3000>;
43 isa = <3000>;
48 isa = <2050>;
54 isa = <2040>;
59 isa = <3000>;
64 isa = <2010>;
70 isa = <0>;
/linux/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
85 riscv,isa = "rv64imafdc";
86 riscv,isa-base = "rv64i";
87 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
116 riscv,isa = "rv64imafdc";
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/linux/arch/arc/kernel/
H A Dsetup.c87 struct bcr_generic isa; in arcompact_mumbojumbo() local
89 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); in arcompact_mumbojumbo()
91 if (!isa.ver) /* ISA BCR absent, use Kconfig info */ in arcompact_mumbojumbo()
95 atomic = isa.info & 1; in arcompact_mumbojumbo()
160 struct bcr_isa_arcv2 isa; in arcv2_mumbojumbo() local
200 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); in arcv2_mumbojumbo()
204 IS_AVAIL1(isa.be, "[Big-Endian]"), in arcv2_mumbojumbo()
217 IS_AVAIL2(isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), in arcv2_mumbojumbo()
218 IS_AVAIL2(isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), in arcv2_mumbojumbo()
219 IS_AVAIL2(isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS), in arcv2_mumbojumbo()
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