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Searched refs:intel_uncore_read (Results 1 – 25 of 42) sorted by relevance

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/linux/drivers/gpu/drm/i915/
H A Dvlv_suspend.c119 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
120 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
121 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
122 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
123 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
126 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
128 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
129 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
131 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
132 s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
[all …]
H A Di915_gpu_error.c1220 intel_uncore_read(uncore, FENCE_REG(i)); in gt_record_fences()
1239 ee->fault_reg = intel_uncore_read(engine->uncore, in engine_record_registers()
1245 ee->fault_reg = intel_uncore_read(engine->uncore, in engine_record_registers()
1248 ee->fault_reg = intel_uncore_read(engine->uncore, in engine_record_registers()
1322 ee->hws = intel_uncore_read(engine->uncore, mmio); in engine_record_registers()
1343 intel_uncore_read(engine->uncore, in engine_record_registers()
1347 intel_uncore_read(engine->uncore, in engine_record_registers()
1756 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); in gt_record_uc()
1777 gt->derrmr = intel_uncore_read(uncore, DERRMR); in gt_record_display_regs()
1780 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); in gt_record_display_regs()
[all …]
H A Di915_debugfs.c344 intel_uncore_read(uncore, DCC)); in i915_swizzle_info()
346 intel_uncore_read(uncore, DCC2)); in i915_swizzle_info()
353 intel_uncore_read(uncore, MAD_DIMM_C0)); in i915_swizzle_info()
355 intel_uncore_read(uncore, MAD_DIMM_C1)); in i915_swizzle_info()
357 intel_uncore_read(uncore, MAD_DIMM_C2)); in i915_swizzle_info()
359 intel_uncore_read(uncore, TILECTL)); in i915_swizzle_info()
362 intel_uncore_read(uncore, GAMTARBMODE)); in i915_swizzle_info()
365 intel_uncore_read(uncore, ARB_MODE)); in i915_swizzle_info()
367 intel_uncore_read(uncore, DISP_ARB_CTL)); in i915_swizzle_info()
H A Di915_irq.c99 u32 val = intel_uncore_read(uncore, reg); in gen2_assert_iir_is_zero()
168 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
224 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
225 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); in valleyview_irq_handler()
226 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
310 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
311 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
827 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
830 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
844 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
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H A Di915_vgpu.c267 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
269 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
271 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
273 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
H A Di915_hwmon.c108 reg_value = intel_uncore_read(uncore, rgadr); in hwm_field_read_and_scale()
153 reg_val = intel_uncore_read(uncore, rgaddr); in hwm_energy()
178 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power1_max_interval_show()
337 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_temp); in hwm_temp_read()
370 reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status); in hwm_in_read()
416 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power_max_read()
478 nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power_max_write()
683 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.fan_speed); in hwm_fan_input_read()
874 val_sku_unit = intel_uncore_read(uncore, in hwm_get_preregistration_info()
882 ddat->fi.reg_val_prev = intel_uncore_read(uncore, in hwm_get_preregistration_info()
H A Di915_utils.c102 intel_uncore_read(&i915->uncore, MTL_PCODE_STOLEN_ACCESS) == STOLEN_ACCESS_ALLOWED; in i915_direct_stolen_access()
H A Di915_ioctl.c82 reg->val = intel_uncore_read(uncore, entry->offset_ldw); in i915_reg_read_ioctl()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu_debugfs.c24 sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); in cherryview_sseu_device_status()
25 sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); in cherryview_sseu_device_status()
26 sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2); in cherryview_sseu_device_status()
27 sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2); in cherryview_sseu_device_status()
65 s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) & in gen11_sseu_device_status()
67 eu_reg[2 * s] = intel_uncore_read(uncore, in gen11_sseu_device_status()
69 eu_reg[2 * s + 1] = intel_uncore_read(uncore, in gen11_sseu_device_status()
119 s_reg[s] = intel_uncore_read(uncore, GEN9_SLICE_PGCTL_ACK(s)); in gen9_sseu_device_status()
121 intel_uncore_read(uncore, GEN9_SS01_EU_PGCTL_ACK(s)); in gen9_sseu_device_status()
123 intel_uncore_read(uncore, GEN9_SS23_EU_PGCTL_ACK(s)); in gen9_sseu_device_status()
[all …]
H A Dintel_rps.c299 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_init()
336 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
337 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
338 total += intel_uncore_read(uncore, CSIEC); in __ips_chipset_val()
357 tsfs = intel_uncore_read(uncore, TSFS); in ips_mch_val()
404 count = intel_uncore_read(uncore, GFXEC); in __gen5_ips_update()
506 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i)); in init_emon()
547 return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK; in init_emon()
559 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_enable()
581 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) & in gen5_rps_enable()
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H A Dintel_rc6.c300 pcbr = intel_uncore_read(uncore, VLV_PCBR); in chv_rc6_init()
322 pcbr = intel_uncore_read(uncore, VLV_PCBR); in vlv_rc6_init()
429 rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE); in intel_check_bios_c6_setup()
444 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); in bxt_check_bios_rc6_setup()
445 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); in bxt_check_bios_rc6_setup()
454 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { in bxt_check_bios_rc6_setup()
464 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; in bxt_check_bios_rc6_setup()
471 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
472 (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
473 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
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H A Dintel_sseu.c202 fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t)); in xehp_load_dss_mask()
239 eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; in xehp_sseu_info_init()
272 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & in gen12_sseu_info_init()
276 g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE); in gen12_sseu_info_init()
279 eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & in gen12_sseu_info_init()
309 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & in gen11_sseu_info_init()
313 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); in gen11_sseu_info_init()
315 eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & in gen11_sseu_info_init()
331 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); in cherryview_sseu_info_init()
387 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); in gen9_sseu_info_init()
[all …]
H A Dintel_gt_clock_utils.c16 u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); in read_reference_ts_freq()
59 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen11_read_clock_frequency()
74 u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); in gen11_read_clock_frequency()
92 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen9_read_clock_frequency()
H A Dselftest_rps.c209 intel_uncore_read(rps_to_uncore(rps), in show_pstate_limits()
214 intel_uncore_read(rps_to_uncore(rps), in show_pstate_limits()
667 if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)), in live_rps_frequency_cs()
944 timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI); in __rps_up_interrupt()
963 intel_uncore_read(uncore, GEN6_RP_PREV_UP), in __rps_up_interrupt()
964 intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD), in __rps_up_interrupt()
965 intel_uncore_read(uncore, GEN6_RP_UP_EI)); in __rps_up_interrupt()
992 timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); in __rps_down_interrupt()
1008 intel_uncore_read(uncore, GEN6_RP_PREV_DOWN), in __rps_down_interrupt()
1009 intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD), in __rps_down_interrupt()
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H A Dintel_wopcm.c203 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); in __wopcm_regs_locked()
204 u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE); in __wopcm_regs_locked()
220 return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED; in __wopcm_regs_writable()
H A Dintel_ggtt_fencing.c590 if (intel_uncore_read(uncore, DISP_ARB_CTL) & in detect_bit_6_swizzle()
601 dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0); in detect_bit_6_swizzle()
602 dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1); in detect_bit_6_swizzle()
668 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle()
707 !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { in detect_bit_6_swizzle()
863 num_fences = intel_uncore_read(uncore, in intel_ggtt_init_fences()
H A Dintel_gt_mcr.c125 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
139 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
143 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
167 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
739 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any()
H A Dintel_engine_cs.c299 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); in intel_engine_context_size()
303 cxt_size = intel_uncore_read(uncore, CXT_SIZE); in intel_engine_context_size()
318 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; in intel_engine_context_size()
768 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); in engine_mask_apply_media_fuses()
777 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); in engine_mask_apply_media_fuses()
1728 val = intel_uncore_read(engine->uncore, _reg[engine->id]); in __cs_pending_mi_force_wakes()
1785 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
1791 intel_uncore_read(uncore, GEN7_SC_INSTDONE); in intel_engine_get_instdone()
1794 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); in intel_engine_get_instdone()
1796 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); in intel_engine_get_instdone()
[all …]
H A Dintel_engine.h83 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
92 __val = intel_uncore_read((engine__)->uncore, \
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c93 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
159 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
377 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
385 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
386 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
387 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
388 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
389 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
398 res1 = intel_uncore_read(&dev_priv->uncore, in i9xx_pipe_crc_irq_handler()
404 res2 = intel_uncore_read(&dev_priv->uncore, in i9xx_pipe_crc_irq_handler()
[all …]
H A Di9xx_wm.c155 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in _intel_set_memory_cxsr()
159 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
163 val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv)); in _intel_set_memory_cxsr()
172 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
183 was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN; in _intel_set_memory_cxsr()
283 dsparb = intel_uncore_read(&dev_priv->uncore, in vlv_get_fifo_size()
285 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
290 dsparb = intel_uncore_read(&dev_priv->uncore, in vlv_get_fifo_size()
292 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
297 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc.c73 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS); in __intel_uc_reset_hw()
193 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15)); in guc_get_mmio_msg()
407 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET)); in uc_init_wopcm()
410 intel_uncore_read(uncore, GUC_WOPCM_SIZE)); in uc_init_wopcm()
420 return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) || in uc_is_wopcm_locked()
421 (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID); in uc_is_wopcm_locked()
H A Dintel_guc.c99 guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & in gen9_enable_guc_interrupts()
404 stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP); in intel_guc_dump_time_info()
547 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ in intel_guc_send_mmio()
594 response_buf[i] = intel_uncore_read(uncore, in intel_guc_send_mmio()
926 u32 status = intel_uncore_read(uncore, GUC_STATUS); in intel_guc_load_status()
939 i, intel_uncore_read(uncore, SOFT_SCRATCH(i))); in intel_guc_load_status()
H A Dintel_huc.c331 huc->loaded_via_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) & in check_huc_loading_mode()
494 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); in intel_huc_wait_for_auth_complete()
582 status = intel_uncore_read(gt->uncore, huc->status[type].reg); in intel_huc_is_authenticated()
690 intel_uncore_read(gt->uncore, huc->status[INTEL_HUC_AUTH_BY_GUC].reg)); in intel_huc_load_status()
/linux/drivers/gpu/drm/xe/display/ext/
H A Di915_irq.c30 u32 val = intel_uncore_read(uncore, reg); in gen2_assert_iir_is_zero()

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