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/linux/arch/sh/kernel/
H A Dtraps_32.c103 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
111 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
114 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
117 count = 1<<(instruction&3); in handle_unaligned_ins()
127 switch (instruction>>12) { in handle_unaligned_ins()
129 if (instruction & 8) { in handle_unaligned_ins()
161 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
169 if (instruction & 4) in handle_unaligned_ins()
183 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
194 if (instruction & 4) in handle_unaligned_ins()
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/linux/tools/objtool/include/objtool/
H A Dcheck.h30 struct instruction *first_insn, *last_insn, *nop;
43 struct instruction { struct
70 struct instruction *jump_dest; argument
71 struct instruction *first_jump_src; argument
82 static inline struct symbol *insn_func(struct instruction *insn) in insn_func() argument
97 static inline bool is_static_jump(struct instruction *insn) in is_static_jump()
103 static inline bool is_dynamic_jump(struct instruction *insn) in is_dynamic_jump()
109 static inline bool is_jump(struct instruction *insn) in is_jump()
114 struct instruction *find_insn(struct objtool_file *file,
117 struct instruction *next_insn_same_sec(struct objtool_file *file, struct instruction *insn);
H A Darch.h71 struct instruction;
79 struct instruction *insn);
83 unsigned long arch_jump_destination(struct instruction *insn);
/linux/drivers/media/usb/gspca/
H A Djl2005bcd.c107 static u8 instruction[2] = {0x95, 0x00}; in jl2005c_read_reg() local
109 instruction[1] = reg; in jl2005c_read_reg()
111 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_read_reg()
125 static u8 instruction[2] = {0x7f, 0x01}; in jl2005c_start_new_frame() local
127 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_start_new_frame()
152 u8 instruction[2]; in jl2005c_write_reg() local
154 instruction[0] = reg; in jl2005c_write_reg()
155 instruction[1] = value; in jl2005c_write_reg()
157 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_write_reg()
202 static u8 instruction[][2] = { in jl2005c_stream_start_vga_lg() local
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/linux/Documentation/virt/kvm/s390/
H A Ds390-pv.rst26 the behavior of the SIE instruction. A new format 4 state description
48 of an instruction emulation by KVM, e.g. we can never inject a
65 With the format 4 state description for PVMs, the SIE instruction already
67 to interpret every instruction, but needs to hand some tasks to KVM;
73 the instruction data, such as I/O data structures, are filtered.
78 Only GR values needed to emulate an instruction will be copied into this
82 the bytes of the instruction text, but with pre-set register values
83 instead of the actual ones. I.e. each instruction always uses the same
84 instruction text, in order not to leak guest instruction text.
88 The Secure Instruction Data Area contains instruction storage
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/linux/tools/objtool/
H A Dcheck.c27 struct instruction *insn;
38 struct instruction *find_insn(struct objtool_file *file, in find_insn()
41 struct instruction *insn; in find_insn()
51 struct instruction *next_insn_same_sec(struct objtool_file *file, in next_insn_same_sec()
52 struct instruction *insn) in next_insn_same_sec()
64 static struct instruction *next_insn_same_func(struct objtool_file *file, in next_insn_same_func()
65 struct instruction *insn) in next_insn_same_func()
67 struct instruction *next = next_insn_same_sec(file, insn); in next_insn_same_func()
84 static struct instruction *prev_insn_same_sec(struct objtool_file *file, in prev_insn_same_sec()
85 struct instruction *insn) in prev_insn_same_sec()
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/linux/arch/arm/nwfpe/
H A Dentry.S79 bne next @ get the next instruction;
82 bl EmulateAll @ emulate the instruction
88 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
105 @ plain LDR instruction. Weird, but it seems harmless.
108 .Lrep: str r4, [sp, #S_PC] @ retry current instruction
118 @ Check whether the instruction is a co-processor instruction.
126 @ lr = unrecognised instruction return address
131 sub r4, r4, #4 @ ARM instruction at user PC - 4
133 ARM_BE8(rev r0, r0) @ little endian instruction
175 @ r0 = instruction
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/linux/net/nfc/hci/
H A Dhcp.c22 u8 type, u8 instruction, in nfc_hci_hcp_message_tx() argument
75 packet->message.header = HCP_HEADER(type, instruction); in nfc_hci_hcp_message_tx()
118 u8 instruction, struct sk_buff *skb) in nfc_hci_hcp_message_rx() argument
122 nfc_hci_resp_received(hdev, instruction, skb); in nfc_hci_hcp_message_rx()
125 nfc_hci_cmd_received(hdev, pipe, instruction, skb); in nfc_hci_hcp_message_rx()
128 nfc_hci_event_received(hdev, pipe, instruction, skb); in nfc_hci_hcp_message_rx()
132 type, instruction); in nfc_hci_hcp_message_rx()
/linux/Documentation/bpf/
H A Dbpf_licensing.rst11 http://www.tcpdump.org/papers/bpf-usenix93.pdf. The corresponding instruction
13 instruction set is now known as "classic BPF".
15 However an instruction set is a specification for machine-language interaction,
18 instruction set may enjoy no copyright protection.
20 * eBPF (extended BPF) instruction set continues to be BSD
22 In 2014, the classic BPF instruction set was significantly extended. We
23 typically refer to this instruction set as eBPF to disambiguate it from cBPF.
24 The eBPF instruction set is still BSD licensed.
29 Using the eBPF instruction set requires implementing code in both kernel space
52 The HW can choose to execute eBPF instruction natively and provide eBPF runtime
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/linux/drivers/video/backlight/
H A Dotm3225a.c160 struct otm3225a_spi_instruction *instruction, in otm3225a_write() argument
169 buf[2] = instruction->reg; in otm3225a_write()
174 buf[1] = (instruction->value >> 8) & 0xff; in otm3225a_write()
175 buf[2] = instruction->value & 0xff; in otm3225a_write()
179 if (instruction->delay) in otm3225a_write()
180 msleep(instruction->delay); in otm3225a_write()
181 instruction++; in otm3225a_write()
/linux/arch/nios2/platform/
H A DKconfig.platform64 bool "Enable MUL instruction"
67 instruction. This will enable the -mhw-mul compiler flag.
70 bool "Enable MULX instruction"
73 instruction. Enables the -mhw-mulx compiler flag.
76 bool "Enable DIV instruction"
79 instruction. Enables the -mhw-div compiler flag.
103 bool "Byteswap custom instruction"
105 Use the byteswap (endian converter) Nios II custom instruction provided
110 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
113 Number of the instruction as configured in QSYS Builder.
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/linux/drivers/crypto/intel/keembay/
H A Docs-aes.c527 enum ocs_instruction instruction) in set_ocs_aes_command() argument
554 val = (cipher << 14) | (mode << 8) | (instruction << 6) | in set_ocs_aes_command()
562 enum ocs_instruction instruction) in ocs_aes_init() argument
571 set_ocs_aes_command(aes_dev, cipher, mode, instruction); in ocs_aes_init()
605 enum ocs_instruction instruction, in ocs_aes_validate_inputs() argument
617 if (instruction != OCS_ENCRYPT && instruction != OCS_DECRYPT && in ocs_aes_validate_inputs()
618 instruction != OCS_EXPAND && instruction != OCS_BYPASS) in ocs_aes_validate_inputs()
628 if (instruction == OCS_BYPASS) { in ocs_aes_validate_inputs()
746 if (instruction == OCS_DECRYPT) { in ocs_aes_validate_inputs()
799 enum ocs_instruction instruction, in ocs_aes_op() argument
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/linux/Documentation/staging/
H A Dlzo.rst22 the operands for the instruction, whose size and position depend on the
23 opcode and on the number of literals copied by previous instruction. The
59 After any instruction except the large literal copy, 0, 1, 2 or 3 literals
60 are copied before starting the next instruction. The number of literals that
61 were copied may change the meaning and behaviour of the next instruction. In
62 practice, only one instruction needs to know whether 0, less than 4, or more
65 generally encoded in the last two bits of the instruction but may also be
69 instruction may encode this distance (0001HLLL), it takes one LE16 operand
100 0..16 : follow regular instruction encoding, see below. It is worth
123 Depends on the number of literals copied by the last instruction.
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/linux/Documentation/arch/powerpc/
H A Dsyscall64-abi.rst10 The syscall is made with the sc instruction, and returns with execution
11 continuing at the instruction following the sc instruction.
14 scv 0 instruction is an alternative that may provide better performance,
32 - For the sc instruction, both a value and an error condition are returned.
38 - For the scv 0 instruction, the return value indicates failure if it is
52 For the sc instruction, the differences from the ELF ABI are as follows:
70 For the scv 0 instruction, the differences from the ELF ABI are as follows:
119 performed with the sc instruction, if it is 0x3000 then the system call was
120 performed with the scv 0 instruction.
147 The vsyscall is performed with a branch-with-link instruction to the vsyscall
/linux/Documentation/arch/arm64/
H A Dlegacy_instructions.rst7 the architecture. The infrastructure code uses undefined instruction
9 the instruction execution in hardware.
18 Generates undefined instruction abort. Default for instructions that
25 usage of emulated instruction is traced as well as rate limited
38 The default mode depends on the status of the instruction in the
43 individual instruction notes for further information.
/linux/arch/arm/probes/kprobes/
H A Dtest-core.h155 #define TEST_INSTRUCTION(instruction) \ argument
157 "1: "instruction" \n\t" \
160 #define TEST_BRANCH_F(instruction) \ argument
161 TEST_INSTRUCTION(instruction) \
165 #define TEST_BRANCH_B(instruction) \ argument
170 TEST_INSTRUCTION(instruction)
172 #define TEST_BRANCH_FX(instruction, codex) \ argument
173 TEST_INSTRUCTION(instruction) \
179 #define TEST_BRANCH_BX(instruction, codex) \ argument
185 TEST_INSTRUCTION(instruction)
/linux/Documentation/bpf/standardization/
H A Dinstruction-set.rst11 operating system kernel. This document specifies the BPF instruction
134 instruction has one or more conformance groups of which it is a member.
152 BPF has two instruction encodings:
154 * the basic instruction encoding, which uses 64 bits to encode an instruction
155 * the wide instruction encoding, which appends a second 64 bits
156 after the basic instruction for a total of 128 bits.
158 Basic instruction encoding
161 A basic instruction is encoded as follows::
177 The format of these bits varies by instruction class
180 The instruction class (see `Instruction classes`_)
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/linux/arch/s390/kvm/
H A Dtrace.h157 __field(__u64, instruction)
162 __entry->instruction = ((__u64)ipa << 48) |
167 __entry->instruction,
168 __print_symbolic(icpt_insn_decoder(__entry->instruction),
424 __field(__u64, instruction)
429 __entry->instruction = ((__u64)ipa << 48) |
434 __entry->instruction,
435 __print_symbolic(icpt_insn_decoder(__entry->instruction),
/linux/Documentation/arch/x86/x86_64/
H A Dfred.rst16 delivery) and event return by the IRET instruction with lower
27 instruction (ERETU) effects a return from ring 0 to ring 3, while the
32 instruction (LKGS) for managing the state of the GS segment register.
33 The LKGS instruction can be used by 64-bit operating systems that do
71 LKGS behaves like the MOV to GS instruction except that it loads the
79 the introduction of LKGS instruction, the SWAPGS instruction is no
94 Only execution of a FRED return instruction ERET[US], could lower the
/linux/arch/m68k/fpsp040/
H A Dbugfix.S247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
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/linux/tools/objtool/arch/loongarch/
H A Ddecode.c18 unsigned long arch_jump_destination(struct instruction *insn) in arch_jump_destination()
79 struct instruction *insn) in decode_insn_reg0i26_fomat()
100 struct instruction *insn) in decode_insn_reg1i21_fomat()
118 struct instruction *insn, in decode_insn_reg2i12_fomat()
186 struct instruction *insn, in decode_insn_reg2i14_fomat()
230 struct instruction *insn) in decode_insn_reg2i16_fomat()
286 struct instruction *insn) in arch_decode_instruction()
/linux/Documentation/trace/
H A Dkprobes.rst38 any instruction in the kernel. A return probe fires when a specified
65 instruction and replaces the first byte(s) of the probed instruction
66 with a breakpoint instruction (e.g., int3 on i386 and x86_64).
68 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
74 Next, Kprobes single-steps its copy of the probed instruction.
75 (It would be simpler to single-step the actual instruction in place,
77 instruction. This would open a small time window when another CPU
80 After the instruction is single-stepped, Kprobes executes the
82 Execution then continues with the instruction following the probepoint.
88 register set, including instruction pointer. This operation requires
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/linux/arch/s390/kernel/
H A Dcpacf.c14 #define CPACF_QUERY(name, instruction) \ argument
23 if (!cpacf_query(CPACF_##instruction, &mask)) \
43 #define CPACF_QAI(name, instruction) \ argument
51 if (!cpacf_qai(CPACF_##instruction, &qai)) \
/linux/arch/m68k/ifpsp060/src/
H A Disp.S1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
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H A Dpfpsp.S1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
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