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Searched refs:icache (Results 1 – 25 of 39) sorted by relevance

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/linux/arch/mips/mm/
H A Dc-octeon.c182 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
185 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
188 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
202 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
203 c->icache.sets = 8; in probe_octeon()
204 c->icache.ways = 37; in probe_octeon()
205 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
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/linux/arch/openrisc/kernel/
H A Dcacheinfo.c60 cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW); in init_cache_level()
61 cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); in init_cache_level()
62 cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); in init_cache_level()
63 cpuinfo->icache.size = in init_cache_level()
64 cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size; in init_cache_level()
68 cpuinfo->icache.size, cpuinfo->icache.block_size, in init_cache_level()
69 cpuinfo->icache.sets, cpuinfo->icache.ways); in init_cache_level()
99 ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu); in populate_cache_leaves()
/linux/arch/sh/kernel/cpu/sh4/
H A Dprobe.c35 boot_cpu_data.icache.way_incr = (1 << 13); in cpu_probe()
36 boot_cpu_data.icache.entry_shift = 5; in cpu_probe()
37 boot_cpu_data.icache.sets = 256; in cpu_probe()
38 boot_cpu_data.icache.ways = 1; in cpu_probe()
39 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
202 if (boot_cpu_data.icache.ways > 1) { in cpu_probe()
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/linux/arch/mips/include/asm/
H A Dr4kcache.h245 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
248 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
249 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
252 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
255 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
279 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
282 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
285 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
305 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
307 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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H A Dcpu-features.h249 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
255 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
274 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
510 #define cpu_icache_line_size() cpu_data[0].icache.linesz
H A Dcpu-info.h75 struct cache_desc icache; /* Primary I-cache */ member
/linux/arch/sh/kernel/cpu/
H A Dinit.c209 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); in detect_cache_shape()
306 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - in cpu_init()
307 current_cpu_data.icache.linesz; in cpu_init()
309 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * in cpu_init()
310 current_cpu_data.icache.linesz; in cpu_init()
H A Dproc.c111 if (c->icache.flags & SH_CACHE_COMBINED) { in show_cpuinfo()
113 show_cacheinfo(m, "cache", c->icache); in show_cpuinfo()
116 show_cacheinfo(m, "icache", c->icache); in show_cpuinfo()
/linux/Documentation/arch/riscv/
H A Dcmodx.rst9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
48 synchronized the icache and instruction storage with fence.i, the icache on the
51 migrated to may not have synchronized instruction storage and icache.
55 userspace. The syscall performs a one-off icache flushing operation. The prctl
56 changes the Linux ABI to allow userspace to emit icache flushing operations.
58 As an aside, "deferred" icache flushes can sometimes be triggered in the kernel.
62 an icache flush, this deferred icache flush will be skipped as it is redundant.
/linux/arch/sh/mm/
H A Dcache.c268 boot_cpu_data.icache.ways, in emit_cache_params()
269 boot_cpu_data.icache.sets, in emit_cache_params()
270 boot_cpu_data.icache.way_incr); in emit_cache_params()
272 boot_cpu_data.icache.entry_mask, in emit_cache_params()
273 boot_cpu_data.icache.alias_mask, in emit_cache_params()
274 boot_cpu_data.icache.n_aliases); in emit_cache_params()
307 compute_alias(&boot_cpu_data.icache); in cpu_cache_init()
H A Dcache-shx3.c28 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { in shx3_cache_init()
31 boot_cpu_data.icache.n_aliases = 0; in shx3_cache_init()
H A Dcache-debugfs.c52 cache = &current_cpu_data.icache; in cache_debugfs_show()
/linux/arch/mips/kernel/
H A Dcacheinfo.c36 leaves += (c->icache.waysize) ? 2 : 1; in init_cache_level()
84 if (c->icache.waysize) { in populate_cache_leaves()
89 populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); in populate_cache_leaves()
/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
47 icache-line-size = <32>;
49 icache-size = <32768>;
/linux/arch/openrisc/include/asm/
H A Dcpuinfo.h31 struct cache_desc icache; member
/linux/arch/powerpc/perf/
H A Dpower8-pmu.c138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dpower9-pmu.c181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dpower10-pmu.c137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts28 icache-line-size = <32>;
30 icache-size = <32768>;
H A D10m50_devboard.dts39 icache-line-size = <32>;
40 icache-size = <32768>;
/linux/arch/sh/kernel/cpu/sh2a/
H A Dprobe.c56 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux/arch/sh/kernel/cpu/sh2/
H A Dprobe.c69 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux/arch/microblaze/boot/dts/
H A Dsystem.dts55 xlnx,allow-icache-wr = <0x1>;
81 xlnx,icache-always-used = <0x1>;
82 xlnx,icache-line-len = <0x4>;
83 xlnx,icache-use-fsl = <0x1>;
111 xlnx,use-icache = <0x1>;
/linux/arch/sh/kernel/cpu/sh3/
H A Dprobe.c105 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux/arch/sh/include/asm/
H A Dprocessor.h77 struct cache_info icache; /* Primary I-cache */ member

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