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Searched refs:i915 (Results 1 – 25 of 393) sorted by relevance

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/linux/drivers/gpu/drm/i915/
H A Di915_drv.h379 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) in to_gt() argument
381 return i915->gt[0]; in to_gt()
392 #define INTEL_INFO(i915) ((i915)->__info) argument
393 #define RUNTIME_INFO(i915) (&(i915)->__runtime) argument
394 #define DRIVER_CAPS(i915) (&(i915)->caps) argument
396 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) argument
400 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) argument
401 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ argument
402 RUNTIME_INFO(i915)->graphics.ip.rel)
403 #define IS_GRAPHICS_VER(i915, from, until) \ argument
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H A Dvlv_sideband.h28 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
29 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
31 static inline void vlv_bunit_get(struct drm_i915_private *i915) in vlv_bunit_get() argument
33 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_get()
36 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
37 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
39 static inline void vlv_bunit_put(struct drm_i915_private *i915) in vlv_bunit_put() argument
41 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_put()
44 static inline void vlv_cck_get(struct drm_i915_private *i915) in vlv_cck_get() argument
46 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK)); in vlv_cck_get()
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H A Dvlv_sideband.c31 static void __vlv_punit_get(struct drm_i915_private *i915) in __vlv_punit_get() argument
45 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
46 cpu_latency_qos_update_request(&i915->sb_qos, 0); in __vlv_punit_get()
51 static void __vlv_punit_put(struct drm_i915_private *i915) in __vlv_punit_put() argument
53 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
54 cpu_latency_qos_update_request(&i915->sb_qos, in __vlv_punit_put()
60 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_get() argument
63 __vlv_punit_get(i915); in vlv_iosf_sb_get()
65 mutex_lock(&i915->sb_lock); in vlv_iosf_sb_get()
68 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_put() argument
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H A Di915_getparam.c18 struct drm_i915_private *i915 = to_i915(dev); in i915_getparam_ioctl() local
20 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in i915_getparam_ioctl()
38 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
41 value = !!i915->display.overlay; in i915_getparam_ioctl()
44 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
48 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
52 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
56 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
60 value = HAS_LLC(i915); in i915_getparam_ioctl()
63 value = HAS_WT(i915); in i915_getparam_ioctl()
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H A Di915_driver.c197 static void sanitize_gpu(struct drm_i915_private *i915) in sanitize_gpu() argument
199 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { in sanitize_gpu()
203 for_each_gt(gt, i915, i) in sanitize_gpu()
374 static int i915_set_dma_info(struct drm_i915_private *i915) in i915_set_dma_info() argument
376 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; in i915_set_dma_info()
385 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); in i915_set_dma_info()
387 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); in i915_set_dma_info()
392 if (GRAPHICS_VER(i915) == 2) in i915_set_dma_info()
404 if (IS_I965G(i915) || IS_I965GM(i915)) in i915_set_dma_info()
407 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); in i915_set_dma_info()
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H A Dintel_step.c135 static u8 gmd_to_intel_step(struct drm_i915_private *i915, in gmd_to_intel_step() argument
141 drm_dbg(&i915->drm, "Using future steppings\n"); in gmd_to_intel_step()
148 void intel_step_init(struct drm_i915_private *i915) in intel_step_init() argument
152 int revid = INTEL_REVID(i915); in intel_step_init()
155 if (HAS_GMD_ID(i915)) { in intel_step_init()
156 step.graphics_step = gmd_to_intel_step(i915, in intel_step_init()
157 &RUNTIME_INFO(i915)->graphics.ip); in intel_step_init()
158 step.media_step = gmd_to_intel_step(i915, in intel_step_init()
159 &RUNTIME_INFO(i915)->media.ip); in intel_step_init()
161 RUNTIME_INFO(i915)->step = step; in intel_step_init()
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H A Di915_switcheroo.c15 struct drm_i915_private *i915 = pdev_to_i915(pdev); in i915_switcheroo_set_state() local
18 if (!i915) { in i915_switcheroo_set_state()
22 if (!HAS_DISPLAY(i915)) { in i915_switcheroo_set_state()
28 drm_info(&i915->drm, "switched on\n"); in i915_switcheroo_set_state()
29 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; in i915_switcheroo_set_state()
32 i915_driver_resume_switcheroo(i915); in i915_switcheroo_set_state()
33 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON; in i915_switcheroo_set_state()
35 drm_info(&i915->drm, "switched off\n"); in i915_switcheroo_set_state()
36 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; in i915_switcheroo_set_state()
37 i915_driver_suspend_switcheroo(i915, pmm); in i915_switcheroo_set_state()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_driver.c83 void intel_display_driver_init_hw(struct drm_i915_private *i915) in intel_display_driver_init_hw() argument
85 struct intel_display *display = &i915->display; in intel_display_driver_init_hw()
88 if (!HAS_DISPLAY(i915)) in intel_display_driver_init_hw()
97 intel_display_wa_apply(i915); in intel_display_driver_init_hw()
115 static void intel_mode_config_init(struct drm_i915_private *i915) in intel_mode_config_init() argument
117 struct drm_mode_config *mode_config = &i915->drm.mode_config; in intel_mode_config_init()
119 drm_mode_config_init(&i915->drm); in intel_mode_config_init()
120 INIT_LIST_HEAD(&i915->display.global.obj_list); in intel_mode_config_init()
131 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); in intel_mode_config_init()
137 if (DISPLAY_VER(i915) >= 7) { in intel_mode_config_init()
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H A Dintel_display_device.h139 #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) argument
140 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) argument
141 #define HAS_BIGJOINER(i915) (DISPLAY_VER(i915) >= 11 && HAS_DSC(i915)) argument
142 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) argument
143 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) argument
144 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) argument
145 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) argument
147 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) argument
148 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) argument
149 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) argument
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H A Dintel_audio.c191 static bool needs_wa_14020863754(struct drm_i915_private *i915) in needs_wa_14020863754() argument
193 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); in needs_wa_14020863754()
199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in audio_config_hdmi_pixel_clock() local
209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
213 drm_dbg_kms(&i915->drm, in audio_config_hdmi_pixel_clock()
219 drm_dbg_kms(&i915->drm, in audio_config_hdmi_pixel_clock()
254 static int g4x_eld_buffer_size(struct drm_i915_private *i915) in g4x_eld_buffer_size() argument
258 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); in g4x_eld_buffer_size()
266 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in g4x_audio_codec_get_config() local
271 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); in g4x_audio_codec_get_config()
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H A Dintel_dpll_mgr.c67 void (*enable)(struct drm_i915_private *i915,
76 void (*disable)(struct drm_i915_private *i915,
84 bool (*get_hw_state)(struct drm_i915_private *i915,
92 int (*get_freq)(struct drm_i915_private *i915,
111 void (*update_ref_clks)(struct drm_i915_private *i915);
119 intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, in intel_atomic_duplicate_dpll_state() argument
126 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
156 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, in intel_get_shared_dpll_by_id() argument
162 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
172 void assert_shared_dpll(struct drm_i915_private *i915, in assert_shared_dpll() argument
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H A Dintel_pmdemand.c44 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_get_pmdemand_state() local
47 &i915->display.pmdemand.obj); in intel_atomic_get_pmdemand_state()
58 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_get_old_pmdemand_state() local
61 &i915->display.pmdemand.obj); in intel_atomic_get_old_pmdemand_state()
72 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_get_new_pmdemand_state() local
75 &i915->display.pmdemand.obj); in intel_atomic_get_new_pmdemand_state()
83 int intel_pmdemand_init(struct drm_i915_private *i915) in intel_pmdemand_init() argument
91 intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj, in intel_pmdemand_init()
95 if (IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0)) in intel_pmdemand_init()
97 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
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H A Dintel_modeset_setup.c39 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_disable_noatomic_begin() local
50 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in intel_crtc_disable_noatomic_begin()
58 state = drm_atomic_state_alloc(&i915->drm); in intel_crtc_disable_noatomic_begin()
60 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
70 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, in intel_crtc_disable_noatomic_begin()
79 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); in intel_crtc_disable_noatomic_begin()
82 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); in intel_crtc_disable_noatomic_begin()
86 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
119 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in reset_encoder_connector_state() local
121 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); in reset_encoder_connector_state()
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H A Dintel_dkl_phy.c17 void intel_dkl_phy_init(struct drm_i915_private *i915) in intel_dkl_phy_init() argument
19 spin_lock_init(&i915->display.dkl.phy_lock); in intel_dkl_phy_init()
23 dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) in dkl_phy_set_hip_idx() argument
27 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
29 intel_de_write(i915, in dkl_phy_set_hip_idx()
44 intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) in intel_dkl_phy_read() argument
48 spin_lock(&i915->display.dkl.phy_lock); in intel_dkl_phy_read()
50 dkl_phy_set_hip_idx(i915, reg); in intel_dkl_phy_read()
51 val = intel_de_read(i915, DKL_REG_MMIO(reg)); in intel_dkl_phy_read()
53 spin_unlock(&i915->display.dkl.phy_lock); in intel_dkl_phy_read()
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H A Dintel_backlight.c105 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_backlight_set_pwm_level() local
108 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n", in intel_backlight_set_pwm_level()
115 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_backlight_level_to_pwm() local
118 drm_WARN_ON_ONCE(&i915->drm, in intel_backlight_level_to_pwm()
146 struct drm_i915_private *i915 = to_i915(connector->base.dev); in lpt_get_backlight() local
148 return intel_de_read(i915, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
153 struct drm_i915_private *i915 = to_i915(connector->base.dev); in pch_get_backlight() local
155 return intel_de_read(i915, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
160 struct drm_i915_private *i915 = to_i915(connector->base.dev); in i9xx_get_backlight() local
164 val = intel_de_read(i915, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
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H A Dintel_tc.c180 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_tc_cold_requires_aux_pw() local
184 intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); in intel_tc_cold_requires_aux_pw()
190 struct drm_i915_private *i915 = tc_to_i915(tc); in __tc_cold_block() local
194 return intel_display_power_get(i915, *domain); in __tc_cold_block()
214 struct drm_i915_private *i915 = tc_to_i915(tc); in __tc_cold_unblock() local
216 intel_display_power_put(i915, domain, wakeref); in __tc_cold_unblock()
233 struct drm_i915_private *i915 = tc_to_i915(tc); in assert_display_core_power_enabled() local
235 drm_WARN_ON(&i915->drm, in assert_display_core_power_enabled()
236 !intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE)); in assert_display_core_power_enabled()
242 struct drm_i915_private *i915 = tc_to_i915(tc); in assert_tc_cold_blocked() local
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H A Dskl_watermark.c37 static void skl_sagv_disable(struct drm_i915_private *i915);
55 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915) in intel_enabled_dbuf_slices_mask() argument
60 for_each_dbuf_slice(i915, slice) { in intel_enabled_dbuf_slices_mask()
61 if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) in intel_enabled_dbuf_slices_mask()
72 static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915) in skl_needs_memory_bw_wa() argument
74 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
78 intel_has_sagv(struct drm_i915_private *i915) in intel_has_sagv() argument
80 return HAS_SAGV(i915) && in intel_has_sagv()
81 i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED; in intel_has_sagv()
85 intel_sagv_block_time(struct drm_i915_private *i915) in intel_sagv_block_time() argument
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H A Dintel_display_driver.h17 void intel_display_driver_init_hw(struct drm_i915_private *i915);
18 void intel_display_driver_early_probe(struct drm_i915_private *i915);
19 int intel_display_driver_probe_noirq(struct drm_i915_private *i915);
20 int intel_display_driver_probe_nogem(struct drm_i915_private *i915);
21 int intel_display_driver_probe(struct drm_i915_private *i915);
22 void intel_display_driver_register(struct drm_i915_private *i915);
23 void intel_display_driver_remove(struct drm_i915_private *i915);
24 void intel_display_driver_remove_noirq(struct drm_i915_private *i915);
25 void intel_display_driver_remove_nogem(struct drm_i915_private *i915);
26 void intel_display_driver_unregister(struct drm_i915_private *i915);
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H A Dintel_display_power.c258 sanitize_target_dc_state(struct drm_i915_private *i915, in sanitize_target_dc_state() argument
261 struct i915_power_domains *power_domains = &i915->display.power.domains; in sanitize_target_dc_state()
341 struct drm_i915_private *i915 = container_of(power_domains, in assert_async_put_domain_masks_disjoint() local
345 return !drm_WARN_ON(&i915->drm, in assert_async_put_domain_masks_disjoint()
354 struct drm_i915_private *i915 = container_of(power_domains, in __async_put_domains_state_ok() local
363 err |= drm_WARN_ON(&i915->drm, in __async_put_domains_state_ok()
368 err |= drm_WARN_ON(&i915->drm, in __async_put_domains_state_ok()
377 struct drm_i915_private *i915 = container_of(power_domains, in print_power_domains() local
382 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); in print_power_domains()
384 drm_dbg(&i915->drm, "%s use_count %d\n", in print_power_domains()
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H A Dintel_display_power.h179 void intel_display_power_suspend_late(struct drm_i915_private *i915);
180 void intel_display_power_resume_early(struct drm_i915_private *i915);
181 void intel_display_power_suspend(struct drm_i915_private *i915);
182 void intel_display_power_resume(struct drm_i915_private *i915);
193 void __intel_display_power_put_async(struct drm_i915_private *i915,
197 void intel_display_power_flush_work(struct drm_i915_private *i915);
203 intel_display_power_put_async(struct drm_i915_private *i915, in intel_display_power_put_async() argument
207 __intel_display_power_put_async(i915, domain, wakeref, -1); in intel_display_power_put_async()
211 intel_display_power_put_async_delay(struct drm_i915_private *i915, in intel_display_power_put_async_delay() argument
216 __intel_display_power_put_async(i915, domain, wakeref, delay_ms); in intel_display_power_put_async_delay()
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/linux/drivers/gpu/drm/i915/soc/
H A Dintel_gmch.c22 int intel_gmch_bridge_setup(struct drm_i915_private *i915) in intel_gmch_bridge_setup() argument
24 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); in intel_gmch_bridge_setup()
26 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); in intel_gmch_bridge_setup()
27 if (!i915->gmch.pdev) { in intel_gmch_bridge_setup()
28 drm_err(&i915->drm, "bridge device not found\n"); in intel_gmch_bridge_setup()
32 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, in intel_gmch_bridge_setup()
33 i915->gmch.pdev); in intel_gmch_bridge_setup()
36 static int mchbar_reg(struct drm_i915_private *i915) in mchbar_reg() argument
38 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in mchbar_reg()
43 intel_alloc_mchbar_resource(struct drm_i915_private *i915) in intel_alloc_mchbar_resource() argument
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/linux/drivers/gpu/drm/i915/selftests/
H A Dmock_gem_device.c46 void mock_device_flush(struct drm_i915_private *i915) in mock_device_flush() argument
48 struct intel_gt *gt = to_gt(i915); in mock_device_flush()
61 struct drm_i915_private *i915 = to_i915(dev); in mock_device_release() local
63 if (!i915->do_release) in mock_device_release()
66 mock_device_flush(i915); in mock_device_release()
67 intel_gt_driver_remove(to_gt(i915)); in mock_device_release()
69 i915_gem_drain_workqueue(i915); in mock_device_release()
71 mock_fini_ggtt(to_gt(i915)->ggtt); in mock_device_release()
72 destroy_workqueue(i915->unordered_wq); in mock_device_release()
73 destroy_workqueue(i915->wq); in mock_device_release()
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/linux/drivers/gpu/drm/xe/
H A DMakefile151 -I$(src)/compat-i915-headers \
152 -I$(srctree)/drivers/gpu/drm/i915/display/ \
156 $(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
161 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
184 i915-soc/intel_dram.o \
185 i915-soc/intel_pch.o \
186 i915-soc/intel_rom.o
190 i915-display/icl_dsi.o \
191 i915-display/intel_alpm.o \
192 i915-display/intel_atomic.o \
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/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dvlv_sideband.h27 static inline void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_get() argument
30 static inline u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg) in vlv_iosf_sb_read() argument
34 static inline void vlv_iosf_sb_write(struct drm_i915_private *i915, in vlv_iosf_sb_write() argument
38 static inline void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_put() argument
41 static inline void vlv_bunit_get(struct drm_i915_private *i915) in vlv_bunit_get() argument
44 static inline u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg) in vlv_bunit_read() argument
48 static inline void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_bunit_write() argument
51 static inline void vlv_bunit_put(struct drm_i915_private *i915) in vlv_bunit_put() argument
54 static inline void vlv_cck_get(struct drm_i915_private *i915) in vlv_cck_get() argument
57 static inline u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg) in vlv_cck_read() argument
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_wopcm.c81 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init_early() local
83 if (!HAS_GT_UC(i915)) in intel_wopcm_init_early()
86 if (GRAPHICS_VER(i915) >= 11) in intel_wopcm_init_early()
91 drm_dbg(&i915->drm, "WOPCM: %uK\n", wopcm->size / 1024); in intel_wopcm_init_early()
94 static u32 context_reserved_size(struct drm_i915_private *i915) in context_reserved_size() argument
96 if (IS_GEN9_LP(i915)) in context_reserved_size()
98 else if (GRAPHICS_VER(i915) >= 11) in context_reserved_size()
104 static bool gen9_check_dword_gap(struct drm_i915_private *i915, in gen9_check_dword_gap() argument
117 drm_err(&i915->drm, in gen9_check_dword_gap()
127 static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915, in gen9_check_huc_fw_fits() argument
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