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Searched refs:hwpwm (Results 1 – 25 of 37) sorted by relevance

12

/linux/drivers/pwm/
H A Dpwm-vt8500.c108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
109 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
112 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
115 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
120 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all …]
H A Dpwm-sunplus.c68 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
72 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
100 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); in sunplus_pwm_apply()
104 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
106 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
109 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
112 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
[all …]
H A Dpwm-sun4i.c127 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
136 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
140 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
145 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
150 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
151 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
156 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
263 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
269 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
272 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
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H A Dpwm-sprd.c75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
87 pwm->hwpwm); in sprd_pwm_get_state()
91 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
105 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
110 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
126 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
158 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all …]
H A Dpwm-bcm-iproc.c79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
84 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
97 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
102 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
106 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
154 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
158 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
159 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
163 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
164 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all …]
H A Dpwm-atmel.c235 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
237 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
240 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
242 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
253 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
263 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
265 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
273 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
295 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
[all …]
H A Dpwm-dwc-core.c70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in __dwc_pwm_configure_timer()
78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); in __dwc_pwm_configure_timer()
79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); in __dwc_pwm_configure_timer()
88 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); in __dwc_pwm_configure_timer()
93 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); in __dwc_pwm_configure_timer()
112 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in dwc_pwm_apply()
129 ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); in dwc_pwm_get_state()
130 ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); in dwc_pwm_get_state()
131 ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); in dwc_pwm_get_state()
H A Dpwm-microchip-core.c79 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
80 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()
87 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); in mchp_core_pwm_enable()
88 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; in mchp_core_pwm_enable()
95 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) in mchp_core_pwm_enable()
178 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
179 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
308 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); in mchp_core_pwm_apply_locked()
362 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_apply()
375 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_get_state()
[all …]
H A Dpwm-sti.c183 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || in sti_pwm_config()
184 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || in sti_pwm_config()
221 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); in sti_pwm_config()
227 set_bit(pwm->hwpwm, &pc->configured); in sti_pwm_config()
265 pwm->hwpwm, ret); in sti_pwm_enable()
292 clear_bit(pwm->hwpwm, &pc->configured); in sti_pwm_free()
299 struct sti_cpt_ddata *ddata = &pc->ddata[pwm->hwpwm]; in sti_pwm_capture()
305 if (pwm->hwpwm >= pc->cpt_num_devs) { in sti_pwm_capture()
306 dev_err(dev, "device %u is not valid\n", pwm->hwpwm); in sti_pwm_capture()
314 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); in sti_pwm_capture()
[all …]
H A Dpwm-twl.c82 base = pwm->hwpwm * 3; in twl_pwm_config()
106 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
112 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
136 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
142 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
158 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
196 if (pwm->hwpwm == 1) in twl4030_pwm_free()
228 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
229 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
251 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_disable()
[all …]
H A Dpwm-sophgo-sg2042.c93 pwm->hwpwm, state->enabled, period_ticks, hlperiod_ticks, state->polarity); in pwm_sg2042_set_dutycycle()
95 pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks); in pwm_sg2042_set_dutycycle()
107 pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0); in pwm_sg2042_apply()
120 unsigned int chan = pwm->hwpwm; in pwm_sg2042_get_state()
151 pwmstart |= BIT(pwm->hwpwm); in pwm_sg2044_set_outputen()
153 pwmstart &= ~BIT(pwm->hwpwm); in pwm_sg2044_set_outputen()
166 pwm_oe |= BIT(pwm->hwpwm); in pwm_sg2044_set_outputdir()
168 pwm_oe &= ~BIT(pwm->hwpwm); in pwm_sg2044_set_outputdir()
181 pwm_polarity &= ~BIT(pwm->hwpwm); in pwm_sg2044_set_polarity()
183 pwm_polarity |= BIT(pwm->hwpwm); in pwm_sg2044_set_polarity()
H A Dpwm-rz-mtu3.c132 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) in rz_mtu3_get_channel() argument
138 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) in rz_mtu3_get_channel()
146 u32 hwpwm) in rz_mtu3_pwm_is_ch_enabled() argument
152 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); in rz_mtu3_pwm_is_ch_enabled()
157 if (priv->map->base_pwm_number == hwpwm) in rz_mtu3_pwm_is_ch_enabled()
172 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_request()
201 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_free()
224 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_enable()
229 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_enable()
250 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_disable()
[all …]
H A Dpwm-visconti.c52 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
98 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_apply()
99 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_apply()
100 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
111 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_get_state()
112 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_get_state()
113 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_get_state()
H A Dpwm-samsung.c123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in __pwm_samsung_manual_update()
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()
236 pwm->hwpwm); in pwm_samsung_request()
240 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm])); in pwm_samsung_request()
248 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_enable()
264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); in pwm_samsung_enable()
274 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_disable()
288 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) in pwm_samsung_disable()
291 our_chip->disabled_mask |= BIT(pwm->hwpwm); in pwm_samsung_disable()
312 struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm]; in __pwm_samsung_config()
[all …]
H A Dpwm-lp3943.c34 lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) in lp3943_pwm_request_map() argument
38 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[hwpwm]; in lp3943_pwm_request_map()
41 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
42 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
60 pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm); in lp3943_pwm_request()
82 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_free()
105 if (pwm->hwpwm == 0) { in lp3943_pwm_config()
154 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_enable()
157 if (pwm->hwpwm == 0) in lp3943_pwm_enable()
173 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_disable()
H A Dpwm-lpc18xx-sct.c136 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); in lpc18xx_pwm_set_conflict_res()
137 val |= LPC18XX_PWM_RES(pwm->hwpwm, action); in lpc18xx_pwm_set_conflict_res()
167 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_config_duty()
208 pwm->hwpwm); in lpc18xx_pwm_config()
226 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_enable()
249 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), in lpc18xx_pwm_enable()
251 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), in lpc18xx_pwm_enable()
261 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_disable()
265 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
266 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
[all …]
H A Dpwm-hibvt.c86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
109 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
112 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
123 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
126 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
140 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
143 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
146 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
H A Dpwm-stm32-lp.c138 ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, in stm32_pwm_lp_apply()
142 ret = regmap_write(priv->regmap, pwm->hwpwm ? in stm32_pwm_lp_apply()
148 ret = stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); in stm32_pwm_lp_apply()
197 if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { in stm32_pwm_lp_apply()
253 ret = regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, in stm32_pwm_lp_apply()
259 ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm->hwpwm ? in stm32_pwm_lp_apply()
267 ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? in stm32_pwm_lp_apply()
272 ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state->polarity); in stm32_pwm_lp_apply()
309 if (pwm->hwpwm) in stm32_pwm_lp_get_state()
327 if (pwm->hwpwm) in stm32_pwm_lp_get_state()
[all …]
H A Dpwm-max7360.c52 return regmap_write_bits(regmap, MAX7360_REG_PWMCFG(pwm->hwpwm), in max7360_pwm_request()
118 ret = regmap_write(regmap, MAX7360_REG_PWM(pwm->hwpwm), wfhw->duty_steps); in max7360_pwm_write_waveform()
123 val = wfhw->enabled ? BIT(pwm->hwpwm) : 0; in max7360_pwm_write_waveform()
124 return regmap_write_bits(regmap, MAX7360_REG_GPIOCTRL, BIT(pwm->hwpwm), val); in max7360_pwm_write_waveform()
140 if (val & BIT(pwm->hwpwm)) { in max7360_pwm_read_waveform()
142 ret = regmap_read(regmap, MAX7360_REG_PWM(pwm->hwpwm), &val); in max7360_pwm_read_waveform()
H A Dpwm-spear.c126 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, in spear_pwm_config()
128 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); in spear_pwm_config()
129 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); in spear_pwm_config()
145 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_enable()
147 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_enable()
157 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_disable()
159 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_disable()
H A Dpwm-mc33xs2410.c226 MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), in mc33xs2410_pwm_apply()
227 MC33XS2410_PWM_DC(pwm->hwpwm + 1), in mc33xs2410_pwm_apply()
261 mask = MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm + 1); in mc33xs2410_pwm_apply()
268 mask = MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm + 1); in mc33xs2410_pwm_apply()
284 MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), in mc33xs2410_pwm_get_state()
285 MC33XS2410_PWM_DC(pwm->hwpwm + 1), in mc33xs2410_pwm_get_state()
298 state->polarity = (val[2] & MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm + 1)) ? in mc33xs2410_pwm_get_state()
300 state->enabled = !!(val[3] & MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm + 1)); in mc33xs2410_pwm_get_state()
H A Dpwm-keembay.c102 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); in keembay_pwm_get_state()
109 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); in keembay_pwm_get_state()
137 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); in keembay_pwm_apply()
143 keembay_pwm_disable(priv, pwm->hwpwm); in keembay_pwm_apply()
171 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); in keembay_pwm_apply()
174 keembay_pwm_enable(priv, pwm->hwpwm); in keembay_pwm_apply()
H A Dcore.c1349 dev_set_name(&export->pwm_dev, "pwm%u", pwm->hwpwm); in pwm_export_child()
1358 pwm_prop[0] = kasprintf(GFP_KERNEL, "EXPORT=pwm%u", pwm->hwpwm); in pwm_export_child()
1383 pwm_prop[0] = kasprintf(GFP_KERNEL, "UNEXPORT=pwm%u", pwm->hwpwm); in pwm_unexport_child()
1402 unsigned int hwpwm; in export_store() local
1405 ret = kstrtouint(buf, 0, &hwpwm); in export_store()
1409 if (hwpwm >= chip->npwm) in export_store()
1412 pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); in export_store()
1429 unsigned int hwpwm; in unexport_store() local
1432 ret = kstrtouint(buf, 0, &hwpwm); in unexport_store()
1436 if (hwpwm >= chip->npwm) in unexport_store()
[all …]
H A Dpwm-renesas-tpu.c217 if (pwm->hwpwm >= TPU_CHANNEL_MAX) in tpu_pwm_request()
220 tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_request()
223 tpd->channel = pwm->hwpwm; in tpu_pwm_request()
237 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_free()
246 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_config()
355 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_set_polarity()
365 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_enable()
388 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; in tpu_pwm_disable()
H A Dpwm-mxs.c71 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); in mxs_pwm_apply()
100 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); in mxs_pwm_apply()
102 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); in mxs_pwm_apply()
110 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); in mxs_pwm_apply()

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