79 	reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);  in mchp_core_pwm_enable()
80 	shift = pwm->hwpwm & 7;  in mchp_core_pwm_enable()
87 	mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);  in mchp_core_pwm_enable()
88 	mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;  in mchp_core_pwm_enable()
95 	if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))  in mchp_core_pwm_enable()
178 	writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
179 	writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
308 	period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);  in mchp_core_pwm_apply_locked()
362 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_apply()
375 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_get_state()
377 	if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))  in mchp_core_pwm_get_state()
404 	posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
405 	negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()