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Searched refs:hwc (Results 1 – 25 of 67) sorted by relevance

123

/linux/drivers/net/ethernet/microsoft/mana/
H A Dhw_channel.c9 static int mana_hwc_get_msg_index(struct hw_channel_context *hwc, u16 *msg_id) in mana_hwc_get_msg_index() argument
11 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_get_msg_index()
15 down(&hwc->sema); in mana_hwc_get_msg_index()
19 index = find_first_zero_bit(hwc->inflight_msg_res.map, in mana_hwc_get_msg_index()
20 hwc->inflight_msg_res.size); in mana_hwc_get_msg_index()
22 bitmap_set(hwc->inflight_msg_res.map, index, 1); in mana_hwc_get_msg_index()
31 static void mana_hwc_put_msg_index(struct hw_channel_context *hwc, u16 msg_id) in mana_hwc_put_msg_index() argument
33 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_put_msg_index()
37 bitmap_clear(hwc->inflight_msg_res.map, msg_id, 1); in mana_hwc_put_msg_index()
40 up(&hwc->sema); in mana_hwc_put_msg_index()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/
H A Dhw_table.c34 struct mlx5_sf_hwc_table hwc[MLX5_SF_HWC_MAX]; member
42 return &dev->priv.sf_hw_table->hwc[idx]; in mlx5_sf_controller_to_hwc()
47 struct mlx5_sf_hwc_table *hwc; in mlx5_sf_sw_to_hw_id() local
49 hwc = mlx5_sf_controller_to_hwc(dev, controller); in mlx5_sf_sw_to_hw_id()
50 return hwc->start_fn_id + sw_id; in mlx5_sf_sw_to_hw_id()
53 static u16 mlx5_sf_hw_to_sw_id(struct mlx5_sf_hwc_table *hwc, u16 hw_id) in mlx5_sf_hw_to_sw_id() argument
55 return hw_id - hwc->start_fn_id; in mlx5_sf_hw_to_sw_id()
63 for (i = 0; i < ARRAY_SIZE(table->hwc); i++) { in mlx5_sf_table_fn_to_hwc()
64 if (table->hwc[i].max_fn && in mlx5_sf_table_fn_to_hwc()
65 fn_id >= table->hwc[i].start_fn_id && in mlx5_sf_table_fn_to_hwc()
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/linux/drivers/iio/buffer/
H A Dindustrialio-hw-consumer.c52 struct iio_hw_consumer *hwc, struct iio_dev *indio_dev) in iio_hw_consumer_get_buffer() argument
56 list_for_each_entry(buf, &hwc->buffers, head) { in iio_hw_consumer_get_buffer()
75 list_add_tail(&buf->head, &hwc->buffers); in iio_hw_consumer_get_buffer()
89 struct iio_hw_consumer *hwc; in iio_hw_consumer_alloc() local
93 hwc = kzalloc_obj(*hwc); in iio_hw_consumer_alloc()
94 if (!hwc) in iio_hw_consumer_alloc()
97 INIT_LIST_HEAD(&hwc->buffers); in iio_hw_consumer_alloc()
99 hwc->channels = iio_channel_get_all(dev); in iio_hw_consumer_alloc()
100 if (IS_ERR(hwc->channels)) { in iio_hw_consumer_alloc()
101 ret = PTR_ERR(hwc->channels); in iio_hw_consumer_alloc()
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/linux/drivers/perf/
H A Driscv_pmu.c149 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_ctr_get_width_mask() local
151 if (hwc->idx == -1) in riscv_pmu_ctr_get_width_mask()
155 cwidth = rvpmu->ctr_get_width(hwc->idx); in riscv_pmu_ctr_get_width_mask()
163 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_event_update() local
168 if (!rvpmu->ctr_read || (hwc->state & PERF_HES_UPTODATE)) in riscv_pmu_event_update()
174 prev_raw_count = local64_read(&hwc->prev_count); in riscv_pmu_event_update()
176 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, in riscv_pmu_event_update()
182 local64_sub(delta, &hwc->period_left); in riscv_pmu_event_update()
189 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_stop() local
192 if (!(hwc->state & PERF_HES_STOPPED)) { in riscv_pmu_stop()
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H A Darm_pmu.c207 struct hw_perf_event *hwc = &event->hw; in armpmu_event_set_period() local
208 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
209 s64 period = hwc->sample_period; in armpmu_event_set_period()
216 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
217 hwc->last_period = period; in armpmu_event_set_period()
223 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
224 hwc->last_period = period; in armpmu_event_set_period()
237 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
249 struct hw_perf_event *hwc = &event->hw; in armpmu_event_update() local
254 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
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H A Darm_smmuv3_pmu.c256 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_update() local
259 u32 idx = hwc->idx; in smmu_pmu_event_update()
262 prev = local64_read(&hwc->prev_count); in smmu_pmu_event_update()
264 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in smmu_pmu_event_update()
274 struct hw_perf_event *hwc) in smmu_pmu_set_period() argument
276 u32 idx = hwc->idx; in smmu_pmu_set_period()
299 local64_set(&hwc->prev_count, new); in smmu_pmu_set_period()
397 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_init() local
407 if (hwc->sample_period) { in smmu_pmu_event_init()
440 hwc->idx = -1; in smmu_pmu_event_init()
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H A Driscv_pmu_sbi.c540 struct hw_perf_event *hwc = &event->hw; in pmu_sbi_ctr_get_idx() local
555 if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) { in pmu_sbi_ctr_get_idx()
568 cmask, cflags, hwc->event_base, hwc->config, in pmu_sbi_ctr_get_idx()
569 hwc->config >> 32); in pmu_sbi_ctr_get_idx()
572 cmask, cflags, hwc->event_base, hwc->config, 0); in pmu_sbi_ctr_get_idx()
576 hwc->event_base, hwc->config); in pmu_sbi_ctr_get_idx()
599 struct hw_perf_event *hwc = &event->hw; in pmu_sbi_ctr_clear_idx() local
602 int idx = hwc->idx; in pmu_sbi_ctr_clear_idx()
741 struct hw_perf_event *hwc = &event->hw; in pmu_sbi_ctr_read() local
742 int idx = hwc->idx; in pmu_sbi_ctr_read()
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/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c158 static u32 hisi_l3c_pmu_event_readl(struct hw_perf_event *hwc, u32 reg) in hisi_l3c_pmu_event_readl() argument
160 return readl((void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_readl()
163 static void hisi_l3c_pmu_event_writel(struct hw_perf_event *hwc, u32 reg, u32 val) in hisi_l3c_pmu_event_writel() argument
165 writel(val, (void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_writel()
168 static u64 hisi_l3c_pmu_event_readq(struct hw_perf_event *hwc, u32 reg) in hisi_l3c_pmu_event_readq() argument
170 return readq((void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_readq()
173 static void hisi_l3c_pmu_event_writeq(struct hw_perf_event *hwc, u32 reg, u64 val) in hisi_l3c_pmu_event_writeq() argument
175 writeq(val, (void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_writeq()
180 struct hw_perf_event *hwc = &event->hw; in hisi_l3c_pmu_config_req_tracetag() local
187 val = hisi_l3c_pmu_event_readl(hwc, L3C_TRACETAG_CTRL); in hisi_l3c_pmu_config_req_tracetag()
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H A Dhisi_uncore_pmu.c209 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_event_init() local
248 hwc->idx = -1; in hisi_uncore_pmu_event_init()
249 hwc->config_base = event->attr.config; in hisi_uncore_pmu_event_init()
268 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_enable_event() local
270 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx, in hisi_uncore_pmu_enable_event()
276 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
277 hisi_pmu->ops->enable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
286 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_disable_event() local
288 hisi_pmu->ops->disable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
289 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
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H A Dhisi_pcie_pmu.c268 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_config_event_ctrl() local
271 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); in hisi_pcie_pmu_config_event_ctrl()
277 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_clear_event_ctrl() local
279 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, HISI_PCIE_INIT_SET); in hisi_pcie_pmu_clear_event_ctrl()
384 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_init() local
391 hwc->event_base = HISI_PCIE_EXT_CNT; in hisi_pcie_pmu_event_init()
393 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
448 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_update() local
452 prev_cnt = local64_read(&hwc->prev_count); in hisi_pcie_pmu_event_update()
454 } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, in hisi_pcie_pmu_event_update()
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H A Dhisi_uncore_ddrc_pmu.c68 #define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7) argument
87 struct hw_perf_event *hwc) in hisi_ddrc_pmu_read_counter() argument
92 return readl(ddrc_pmu->base + ddrc_reg_off[hwc->idx]); in hisi_ddrc_pmu_read_counter()
94 return readq(ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); in hisi_ddrc_pmu_read_counter()
98 struct hw_perf_event *hwc, u64 val) in hisi_ddrc_pmu_write_counter() argument
103 writel((u32)val, ddrc_pmu->base + ddrc_reg_off[hwc->idx]); in hisi_ddrc_pmu_write_counter()
105 writeq(val, ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); in hisi_ddrc_pmu_write_counter()
128 struct hw_perf_event *hwc = &event->hw; in hisi_ddrc_pmu_v1_get_event_idx() local
130 int idx = GET_DDRC_EVENTID(hwc); in hisi_ddrc_pmu_v1_get_event_idx()
172 struct hw_perf_event *hwc) in hisi_ddrc_pmu_enable_counter() argument
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H A Dhisi_uncore_noc_pmu.c93 struct hw_perf_event *hwc) in hisi_noc_pmu_read_counter() argument
97 return readq(noc_pmu->base + NOC_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->idx)); in hisi_noc_pmu_read_counter()
101 struct hw_perf_event *hwc, u64 val) in hisi_noc_pmu_write_counter() argument
105 writeq(val, noc_pmu->base + NOC_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->idx)); in hisi_noc_pmu_write_counter()
109 struct hw_perf_event *hwc) in hisi_noc_pmu_enable_counter() argument
114 reg = readl(noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_enable_counter()
116 writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_enable_counter()
120 struct hw_perf_event *hwc) in hisi_noc_pmu_disable_counter() argument
125 reg = readl(noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_disable_counter()
127 writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_disable_counter()
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H A Dhisi_uncore_mn_pmu.c74 struct hw_perf_event *hwc) in hisi_mn_pmu_read_counter() argument
78 return readq(mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx)); in hisi_mn_pmu_read_counter()
82 struct hw_perf_event *hwc, u64 val) in hisi_mn_pmu_write_counter() argument
86 writeq(val, mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx)); in hisi_mn_pmu_write_counter()
128 struct hw_perf_event *hwc) in hisi_mn_pmu_enable_counter() argument
134 val |= BIT(hwc->idx); in hisi_mn_pmu_enable_counter()
139 struct hw_perf_event *hwc) in hisi_mn_pmu_disable_counter() argument
145 val &= ~BIT(hwc->idx); in hisi_mn_pmu_disable_counter()
150 struct hw_perf_event *hwc) in hisi_mn_pmu_enable_counter_int() argument
156 val &= ~BIT(hwc->idx); in hisi_mn_pmu_enable_counter_int()
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/linux/arch/loongarch/kernel/
H A Dperf_event.c253 static int loongarch_pmu_alloc_counter(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc) in loongarch_pmu_alloc_counter() argument
300 struct hw_perf_event *hwc, in loongarch_pmu_event_set_period() argument
304 u64 left = local64_read(&hwc->period_left); in loongarch_pmu_event_set_period()
305 u64 period = hwc->sample_period; in loongarch_pmu_event_set_period()
310 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
311 hwc->last_period = period; in loongarch_pmu_event_set_period()
316 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
317 hwc->last_period = period; in loongarch_pmu_event_set_period()
323 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
326 local64_set(&hwc->prev_count, loongarch_pmu.overflow - left); in loongarch_pmu_event_set_period()
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/linux/arch/x86/events/amd/
H A Diommu.c210 struct hw_perf_event *hwc = &event->hw; in perf_iommu_event_init() local
228 hwc->conf = event->attr.config; in perf_iommu_event_init()
229 hwc->conf1 = event->attr.config1; in perf_iommu_event_init()
242 struct hw_perf_event *hwc = &ev->hw; in perf_iommu_enable_event() local
243 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event()
244 u8 cntr = hwc->iommu_cntr; in perf_iommu_enable_event()
247 reg = GET_CSOURCE(hwc); in perf_iommu_enable_event()
250 reg = GET_DEVID_MASK(hwc); in perf_iommu_enable_event()
251 reg = GET_DEVID(hwc) | (reg << 32); in perf_iommu_enable_event()
256 reg = GET_PASID_MASK(hwc); in perf_iommu_enable_event()
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H A Duncore.c137 struct hw_perf_event *hwc = &event->hw; in amd_uncore_read() local
146 prev = local64_read(&hwc->prev_count); in amd_uncore_read()
152 if (hwc->event_base_rdpmc < 0) in amd_uncore_read()
153 rdmsrq(hwc->event_base, new); in amd_uncore_read()
155 new = rdpmc(hwc->event_base_rdpmc); in amd_uncore_read()
157 local64_set(&hwc->prev_count, new); in amd_uncore_read()
167 struct hw_perf_event *hwc = &event->hw; in amd_uncore_start() local
173 wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
175 hwc->state = 0; in amd_uncore_start()
176 __set_bit(hwc->idx, ctx->active_mask); in amd_uncore_start()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c211 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_event_init() local
218 hwc->config = event->attr.config; in amdgpu_perf_event_init()
219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
227 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_start() local
233 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) in amdgpu_perf_start()
240 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in amdgpu_perf_start()
241 hwc->state = 0; in amdgpu_perf_start()
243 switch (hwc->config_base) { in amdgpu_perf_start()
248 hwc->config, 0 /* unused */, in amdgpu_perf_start()
253 hwc->idx = target_cntr; in amdgpu_perf_start()
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/linux/arch/s390/kernel/
H A Dperf_cpum_sf.c33 #define OVERFLOW_REG(hwc) ((hwc)->extra_reg.config) argument
34 #define SFB_ALLOC_REG(hwc) ((hwc)->extra_reg.alloc) argument
35 #define TEAR_REG(hwc) ((hwc)->last_tag) argument
36 #define SAMPL_RATE(hwc) ((hwc)->event_base) argument
37 #define SAMPL_FLAGS(hwc) ((hwc)->config_base) argument
38 #define SAMPL_DIAG_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_DIAG_MODE) argument
39 #define SAMPL_FREQ_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_FREQ_MODE) argument
361 static unsigned long sfb_max_limit(struct hw_perf_event *hwc) in sfb_max_limit() argument
363 return SAMPL_DIAG_MODE(hwc) ? CPUM_SF_MAX_SDB * CPUM_SF_SDB_DIAG_FACTOR in sfb_max_limit()
368 struct hw_perf_event *hwc) in sfb_pending_allocs() argument
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/linux/arch/sh/kernel/
H A Dperf_event.c103 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init() local
153 hwc->config |= config; in __hw_perf_event_init()
159 struct hw_perf_event *hwc, int idx) in sh_perf_event_update() argument
178 prev_raw_count = local64_read(&hwc->prev_count); in sh_perf_event_update()
181 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sh_perf_event_update()
202 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop() local
203 int idx = hwc->idx; in sh_pmu_stop()
206 sh_pmu->disable(hwc, idx); in sh_pmu_stop()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start() local
221 int idx = hwc->idx; in sh_pmu_start()
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/linux/arch/x86/events/intel/
H A Duncore_discovery.c509 struct hw_perf_event *hwc = &event->hw; in intel_generic_uncore_msr_enable_event() local
511 wrmsrq(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
517 struct hw_perf_event *hwc = &event->hw; in intel_generic_uncore_msr_disable_event() local
519 wrmsrq(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
534 struct hw_perf_event *hwc = &event->hw; in intel_generic_uncore_assign_hw_event() local
541 hwc->config_base = uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
542 hwc->event_base = uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
552 hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
553 hwc->event_base = box_ctl + uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
557 hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx; in intel_generic_uncore_assign_hw_event()
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H A Duncore.c258 struct hw_perf_event *hwc = &event->hw; in uncore_assign_hw_event() local
260 hwc->idx = idx; in uncore_assign_hw_event()
261 hwc->last_tag = ++box->tags[idx]; in uncore_assign_hw_event()
263 if (uncore_pmc_fixed(hwc->idx)) { in uncore_assign_hw_event()
264 hwc->event_base = uncore_fixed_ctr(box); in uncore_assign_hw_event()
265 hwc->config_base = uncore_fixed_ctl(box); in uncore_assign_hw_event()
272 hwc->config_base = uncore_event_ctl(box, hwc->idx); in uncore_assign_hw_event()
273 hwc->event_base = uncore_perf_ctr(box, hwc->idx); in uncore_assign_hw_event()
460 struct hw_perf_event *hwc; in uncore_assign_events() local
473 hwc = &box->event_list[i]->hw; in uncore_assign_events()
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/linux/arch/x86/events/
H A Dcore.c130 struct hw_perf_event *hwc = &event->hw; in x86_perf_event_update() local
135 if (unlikely(!hwc->event_base)) in x86_perf_event_update()
145 prev_raw_count = local64_read(&hwc->prev_count); in x86_perf_event_update()
147 new_raw_count = rdpmc(hwc->event_base_rdpmc); in x86_perf_event_update()
148 } while (!local64_try_cmpxchg(&hwc->prev_count, in x86_perf_event_update()
163 local64_sub(delta, &hwc->period_left); in x86_perf_event_update()
378 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) in set_ext_hw_attr() argument
408 hwc->config |= val; in set_ext_hw_attr()
495 struct hw_perf_event *hwc = &event->hw; in x86_setup_perfctr() local
499 hwc->sample_period = x86_pmu.max_period; in x86_setup_perfctr()
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/linux/arch/sparc/kernel/
H A Dperf_event.c827 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, in… in sparc_pmu_enable_event() argument
845 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, i… in sparc_pmu_disable_event() argument
864 struct hw_perf_event *hwc, int idx) in sparc_perf_event_update() argument
871 prev_raw_count = local64_read(&hwc->prev_count); in sparc_perf_event_update()
874 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sparc_perf_event_update()
882 local64_sub(delta, &hwc->period_left); in sparc_perf_event_update()
888 struct hw_perf_event *hwc, int idx) in sparc_perf_event_set_period() argument
890 s64 left = local64_read(&hwc->period_left); in sparc_perf_event_set_period()
891 s64 period = hwc->sample_period; in sparc_perf_event_set_period()
895 if (unlikely(period != hwc->last_period)) in sparc_perf_event_set_period()
[all …]
/linux/drivers/dma/idxd/
H A Dperfmon.c97 struct hw_perf_event *hwc = &event->hw; in perfmon_assign_hw_event() local
99 hwc->idx = idx; in perfmon_assign_hw_event()
100 hwc->config_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
101 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
201 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_read_counter() local
203 int cntr = hwc->idx; in perfmon_pmu_read_counter()
215 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_event_update() local
217 prev_raw_count = local64_read(&hwc->prev_count); in perfmon_pmu_event_update()
220 } while (!local64_try_cmpxchg(&hwc->prev_count, in perfmon_pmu_event_update()
293 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_event_start() local
[all …]
/linux/arch/powerpc/perf/
H A Dvpa-dtl.c308 struct hw_perf_event *hwc = &event->hw; in vpa_dtl_start_hrtimer() local
310 period = max_t(u64, NSEC_PER_MSEC, hwc->sample_period); in vpa_dtl_start_hrtimer()
311 hrtimer_start(&hwc->hrtimer, ns_to_ktime(period), HRTIMER_MODE_REL_PINNED); in vpa_dtl_start_hrtimer()
316 struct hw_perf_event *hwc = &event->hw; in vpa_dtl_stop_hrtimer() local
318 hrtimer_cancel(&hwc->hrtimer); in vpa_dtl_stop_hrtimer()
352 struct hw_perf_event *hwc = &event->hw; in vpa_dtl_event_init() local
412 hrtimer_setup(&hwc->hrtimer, vpa_dtl_hrtimer_handle, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in vpa_dtl_event_init()
422 hwc->sample_period = event->attr.sample_period; in vpa_dtl_event_init()
423 local64_set(&hwc->period_left, hwc->sample_period); in vpa_dtl_event_init()
424 hwc->last_period = hwc->sample_period; in vpa_dtl_event_init()

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