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Searched refs:hwc (Results 1 – 25 of 76) sorted by relevance

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/linux/drivers/net/ethernet/microsoft/mana/
H A Dhw_channel.c9 static int mana_hwc_get_msg_index(struct hw_channel_context *hwc, u16 *msg_id) in mana_hwc_get_msg_index() argument
11 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_get_msg_index()
15 down(&hwc->sema); in mana_hwc_get_msg_index()
19 index = find_first_zero_bit(hwc->inflight_msg_res.map, in mana_hwc_get_msg_index()
20 hwc->inflight_msg_res.size); in mana_hwc_get_msg_index()
22 bitmap_set(hwc->inflight_msg_res.map, index, 1); in mana_hwc_get_msg_index()
31 static void mana_hwc_put_msg_index(struct hw_channel_context *hwc, u16 msg_id) in mana_hwc_put_msg_index() argument
33 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_put_msg_index()
37 bitmap_clear(hwc->inflight_msg_res.map, msg_id, 1); in mana_hwc_put_msg_index()
40 up(&hwc->sema); in mana_hwc_put_msg_index()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/
H A Dhw_table.c35 struct mlx5_sf_hwc_table *hwc; member
46 if (table->hwc[i].controller == controller) in mlx5_sf_controller_to_hwc()
47 return &table->hwc[i]; in mlx5_sf_controller_to_hwc()
50 return &table->hwc[!!controller]; in mlx5_sf_controller_to_hwc()
55 struct mlx5_sf_hwc_table *hwc; in mlx5_sf_sw_to_hw_id() local
57 hwc = mlx5_sf_controller_to_hwc(dev, controller); in mlx5_sf_sw_to_hw_id()
58 return hwc->start_fn_id + sw_id; in mlx5_sf_sw_to_hw_id()
61 static u16 mlx5_sf_hw_to_sw_id(struct mlx5_sf_hwc_table *hwc, u16 hw_id) in mlx5_sf_hw_to_sw_id() argument
63 return hw_id - hwc->start_fn_id; in mlx5_sf_hw_to_sw_id()
72 if (table->hwc[i].max_fn && in mlx5_sf_table_fn_to_hwc()
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/linux/drivers/perf/
H A Driscv_pmu.c149 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_ctr_get_width_mask() local
151 if (hwc->idx == -1) in riscv_pmu_ctr_get_width_mask()
155 cwidth = rvpmu->ctr_get_width(hwc->idx); in riscv_pmu_ctr_get_width_mask()
163 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_event_update() local
168 if (!rvpmu->ctr_read || (hwc->state & PERF_HES_UPTODATE)) in riscv_pmu_event_update()
174 prev_raw_count = local64_read(&hwc->prev_count); in riscv_pmu_event_update()
176 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, in riscv_pmu_event_update()
182 local64_sub(delta, &hwc->period_left); in riscv_pmu_event_update()
189 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_stop() local
192 if (!(hwc->state & PERF_HES_STOPPED)) { in riscv_pmu_stop()
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H A Dthunderx2_pmu.c325 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_l3c() local
332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
334 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
341 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_dmc() local
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
350 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
357 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_ccpi2() local
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
364 hwc->event_base = (unsigned long)tx2_pmu->base; in init_cntr_base_ccpi2()
370 struct hw_perf_event *hwc = &event->hw; in uncore_start_event_l3c() local
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H A Dstarfive_starlink_pmu.c157 struct hw_perf_event *hwc = &event->hw; in starlink_pmu_set_event_period() local
166 local64_set(&hwc->prev_count, val); in starlink_pmu_set_event_period()
167 if (hwc->config == STARLINK_CYCLES) in starlink_pmu_set_event_period()
177 struct hw_perf_event *hwc = &event->hw; in starlink_pmu_counter_start() local
192 if (hwc->config == STARLINK_CYCLES) { in starlink_pmu_counter_start()
214 struct hw_perf_event *hwc = &event->hw; in starlink_pmu_counter_stop() local
223 if (hwc->config == STARLINK_CYCLES) in starlink_pmu_counter_stop()
234 struct hw_perf_event *hwc = &event->hw; in starlink_pmu_update() local
235 int idx = hwc->idx; in starlink_pmu_update()
241 prev_raw_count = local64_read(&hwc->prev_count); in starlink_pmu_update()
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H A Dqcom_l2_pmu.c299 struct hw_perf_event *hwc = &event->hw; in l2_cache_event_update() local
301 u32 idx = hwc->idx; in l2_cache_event_update()
304 prev = local64_read(&hwc->prev_count); in l2_cache_event_update()
306 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in l2_cache_event_update()
320 struct hw_perf_event *hwc) in l2_cache_cluster_set_period() argument
322 u32 idx = hwc->idx; in l2_cache_cluster_set_period()
335 local64_set(&hwc->prev_count, new); in l2_cache_cluster_set_period()
342 struct hw_perf_event *hwc = &event->hw; in l2_cache_get_event_idx() local
347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
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H A Darm_pmu.c207 struct hw_perf_event *hwc = &event->hw; in armpmu_event_set_period() local
208 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
209 s64 period = hwc->sample_period; in armpmu_event_set_period()
216 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
217 hwc->last_period = period; in armpmu_event_set_period()
223 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
224 hwc->last_period = period; in armpmu_event_set_period()
237 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
249 struct hw_perf_event *hwc = &event->hw; in armpmu_event_update() local
254 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
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H A Dmarvell_pem_pmu.c192 struct hw_perf_event *hwc = &event->hw; in pem_perf_event_init() local
224 hwc->idx = -1; in pem_perf_event_init()
237 struct hw_perf_event *hwc = &event->hw; in pem_perf_event_update() local
241 prev_count = local64_read(&hwc->prev_count); in pem_perf_event_update()
242 new_count = pem_perf_read_counter(pmu, event, hwc->idx); in pem_perf_event_update()
243 } while (local64_xchg(&hwc->prev_count, new_count) != prev_count); in pem_perf_event_update()
251 struct hw_perf_event *hwc = &event->hw; in pem_perf_event_start() local
252 int eventid = hwc->idx; in pem_perf_event_start()
258 local64_set(&hwc->prev_count, in pem_perf_event_start()
261 hwc->state = 0; in pem_perf_event_start()
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H A Dmarvell_cn10k_tad_pmu.c54 struct hw_perf_event *hwc = &event->hw; in tad_pmu_event_counter_read() local
55 u32 counter_idx = hwc->idx; in tad_pmu_event_counter_read()
60 prev = local64_read(&hwc->prev_count); in tad_pmu_event_counter_read()
64 } while (local64_cmpxchg(&hwc->prev_count, prev, new) != prev); in tad_pmu_event_counter_read()
72 struct hw_perf_event *hwc = &event->hw; in tad_pmu_event_counter_stop() local
73 u32 counter_idx = hwc->idx; in tad_pmu_event_counter_stop()
85 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; in tad_pmu_event_counter_stop()
91 struct hw_perf_event *hwc = &event->hw; in tad_pmu_event_counter_start() local
93 u32 counter_idx = hwc->idx; in tad_pmu_event_counter_start()
97 hwc->state = 0; in tad_pmu_event_counter_start()
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H A Darm_smmuv3_pmu.c256 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_update() local
259 u32 idx = hwc->idx; in smmu_pmu_event_update()
262 prev = local64_read(&hwc->prev_count); in smmu_pmu_event_update()
264 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in smmu_pmu_event_update()
274 struct hw_perf_event *hwc) in smmu_pmu_set_period() argument
276 u32 idx = hwc->idx; in smmu_pmu_set_period()
299 local64_set(&hwc->prev_count, new); in smmu_pmu_set_period()
397 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_init() local
407 if (hwc->sample_period) { in smmu_pmu_event_init()
440 hwc->idx = -1; in smmu_pmu_event_init()
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/linux/arch/loongarch/kernel/
H A Dperf_event.c253 static int loongarch_pmu_alloc_counter(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc) in loongarch_pmu_alloc_counter() argument
300 struct hw_perf_event *hwc, in loongarch_pmu_event_set_period() argument
304 u64 left = local64_read(&hwc->period_left); in loongarch_pmu_event_set_period()
305 u64 period = hwc->sample_period; in loongarch_pmu_event_set_period()
310 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
311 hwc->last_period = period; in loongarch_pmu_event_set_period()
316 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
317 hwc->last_period = period; in loongarch_pmu_event_set_period()
323 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
326 local64_set(&hwc->prev_count, loongarch_pmu.overflow - left); in loongarch_pmu_event_set_period()
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/linux/arch/x86/events/amd/
H A Diommu.c210 struct hw_perf_event *hwc = &event->hw; in perf_iommu_event_init() local
228 hwc->conf = event->attr.config; in perf_iommu_event_init()
229 hwc->conf1 = event->attr.config1; in perf_iommu_event_init()
242 struct hw_perf_event *hwc = &ev->hw; in perf_iommu_enable_event() local
243 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event()
244 u8 cntr = hwc->iommu_cntr; in perf_iommu_enable_event()
247 reg = GET_CSOURCE(hwc); in perf_iommu_enable_event()
250 reg = GET_DEVID_MASK(hwc); in perf_iommu_enable_event()
251 reg = GET_DEVID(hwc) | (reg << 32); in perf_iommu_enable_event()
256 reg = GET_PASID_MASK(hwc); in perf_iommu_enable_event()
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H A Duncore.c138 struct hw_perf_event *hwc = &event->hw; in amd_uncore_read() local
147 prev = local64_read(&hwc->prev_count); in amd_uncore_read()
153 if (hwc->event_base_rdpmc < 0) in amd_uncore_read()
154 rdmsrq(hwc->event_base, new); in amd_uncore_read()
156 new = rdpmc(hwc->event_base_rdpmc); in amd_uncore_read()
158 local64_set(&hwc->prev_count, new); in amd_uncore_read()
168 struct hw_perf_event *hwc = &event->hw; in amd_uncore_start() local
174 wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
176 hwc->state = 0; in amd_uncore_start()
177 __set_bit(hwc->idx, ctx->active_mask); in amd_uncore_start()
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H A Dpower.c49 struct hw_perf_event *hwc = &event->hw; in event_update() local
53 prev_pwr_acc = hwc->pwr_acc; in event_update()
54 prev_ptsc = hwc->ptsc; in event_update()
93 struct hw_perf_event *hwc = &event->hw; in pmu_event_stop() local
96 if (!(hwc->state & PERF_HES_STOPPED)) in pmu_event_stop()
97 hwc->state |= PERF_HES_STOPPED; in pmu_event_stop()
100 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { in pmu_event_stop()
106 hwc->state |= PERF_HES_UPTODATE; in pmu_event_stop()
112 struct hw_perf_event *hwc = &event->hw; in pmu_event_add() local
114 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; in pmu_event_add()
H A Dcore.c350 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc) in amd_get_event_code() argument
352 return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff); in amd_get_event_code()
355 static inline bool amd_is_pair_event_code(struct hw_perf_event *hwc) in amd_is_pair_event_code() argument
360 switch (amd_get_event_code(hwc)) { in amd_is_pair_event_code()
392 static inline int amd_is_nb_event(struct hw_perf_event *hwc) in amd_is_nb_event() argument
394 return (hwc->config & 0xe0) == 0xe0; in amd_is_nb_event()
487 struct hw_perf_event *hwc = &event->hw; in __amd_get_nb_event_constraints() local
509 if (new == -1 || hwc->idx == idx) in __amd_get_nb_event_constraints()
784 struct hw_perf_event *hwc = &event->hw; in amd_pmu_v2_enable_event() local
794 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); in amd_pmu_v2_enable_event()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c211 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_event_init() local
218 hwc->config = event->attr.config; in amdgpu_perf_event_init()
219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
227 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_start() local
233 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) in amdgpu_perf_start()
240 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in amdgpu_perf_start()
241 hwc->state = 0; in amdgpu_perf_start()
243 switch (hwc->config_base) { in amdgpu_perf_start()
248 hwc->config, 0 /* unused */, in amdgpu_perf_start()
253 hwc->idx = target_cntr; in amdgpu_perf_start()
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/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_pmu.c206 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_event_init() local
245 hwc->idx = -1; in hisi_uncore_pmu_event_init()
246 hwc->config_base = event->attr.config; in hisi_uncore_pmu_event_init()
265 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_enable_event() local
267 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx, in hisi_uncore_pmu_enable_event()
273 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
274 hisi_pmu->ops->enable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
283 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_disable_event() local
285 hisi_pmu->ops->disable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
286 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
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H A Dhisi_pcie_pmu.c268 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_config_event_ctrl() local
271 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); in hisi_pcie_pmu_config_event_ctrl()
277 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_clear_event_ctrl() local
279 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, HISI_PCIE_INIT_SET); in hisi_pcie_pmu_clear_event_ctrl()
384 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_init() local
391 hwc->event_base = HISI_PCIE_EXT_CNT; in hisi_pcie_pmu_event_init()
393 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
448 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_update() local
452 prev_cnt = local64_read(&hwc->prev_count); in hisi_pcie_pmu_event_update()
454 } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, in hisi_pcie_pmu_event_update()
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H A Dhisi_uncore_ddrc_pmu.c68 #define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7) argument
87 struct hw_perf_event *hwc) in hisi_ddrc_pmu_read_counter() argument
92 return readl(ddrc_pmu->base + ddrc_reg_off[hwc->idx]); in hisi_ddrc_pmu_read_counter()
94 return readq(ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); in hisi_ddrc_pmu_read_counter()
98 struct hw_perf_event *hwc, u64 val) in hisi_ddrc_pmu_write_counter() argument
103 writel((u32)val, ddrc_pmu->base + ddrc_reg_off[hwc->idx]); in hisi_ddrc_pmu_write_counter()
105 writeq(val, ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); in hisi_ddrc_pmu_write_counter()
128 struct hw_perf_event *hwc = &event->hw; in hisi_ddrc_pmu_v1_get_event_idx() local
130 int idx = GET_DDRC_EVENTID(hwc); in hisi_ddrc_pmu_v1_get_event_idx()
172 struct hw_perf_event *hwc) in hisi_ddrc_pmu_enable_counter() argument
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H A Dhisi_uncore_noc_pmu.c92 struct hw_perf_event *hwc) in hisi_noc_pmu_read_counter() argument
96 return readq(noc_pmu->base + NOC_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->idx)); in hisi_noc_pmu_read_counter()
100 struct hw_perf_event *hwc, u64 val) in hisi_noc_pmu_write_counter() argument
104 writeq(val, noc_pmu->base + NOC_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->idx)); in hisi_noc_pmu_write_counter()
108 struct hw_perf_event *hwc) in hisi_noc_pmu_enable_counter() argument
113 reg = readl(noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_enable_counter()
115 writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_enable_counter()
119 struct hw_perf_event *hwc) in hisi_noc_pmu_disable_counter() argument
124 reg = readl(noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_disable_counter()
126 writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx)); in hisi_noc_pmu_disable_counter()
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H A Dhisi_uncore_uc_pmu.c261 struct hw_perf_event *hwc) in hisi_uc_pmu_enable_counter() argument
267 val |= (1 << hwc->idx); in hisi_uc_pmu_enable_counter()
272 struct hw_perf_event *hwc) in hisi_uc_pmu_disable_counter() argument
278 val &= ~(1 << hwc->idx); in hisi_uc_pmu_disable_counter()
283 struct hw_perf_event *hwc) in hisi_uc_pmu_read_counter() argument
285 return readq(uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); in hisi_uc_pmu_read_counter()
297 struct hw_perf_event *hwc, u64 val) in hisi_uc_pmu_write_counter_normal() argument
299 writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); in hisi_uc_pmu_write_counter_normal()
303 struct hw_perf_event *hwc, u64 val) in hisi_uc_pmu_write_counter_quirk_v2() argument
306 hisi_uc_pmu_write_counter_normal(uc_pmu, hwc, val); in hisi_uc_pmu_write_counter_quirk_v2()
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/linux/arch/s390/kernel/
H A Dperf_cpum_sf.c33 #define OVERFLOW_REG(hwc) ((hwc)->extra_reg.config) argument
34 #define SFB_ALLOC_REG(hwc) ((hwc)->extra_reg.alloc) argument
35 #define TEAR_REG(hwc) ((hwc)->last_tag) argument
36 #define SAMPL_RATE(hwc) ((hwc)->event_base) argument
37 #define SAMPL_FLAGS(hwc) ((hwc)->config_base) argument
38 #define SAMPL_DIAG_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_DIAG_MODE) argument
39 #define SAMPL_FREQ_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_FREQ_MODE) argument
361 static unsigned long sfb_max_limit(struct hw_perf_event *hwc) in sfb_max_limit() argument
363 return SAMPL_DIAG_MODE(hwc) ? CPUM_SF_MAX_SDB * CPUM_SF_SDB_DIAG_FACTOR in sfb_max_limit()
368 struct hw_perf_event *hwc) in sfb_pending_allocs() argument
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/linux/arch/sh/kernel/
H A Dperf_event.c103 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init() local
153 hwc->config |= config; in __hw_perf_event_init()
159 struct hw_perf_event *hwc, int idx) in sh_perf_event_update() argument
178 prev_raw_count = local64_read(&hwc->prev_count); in sh_perf_event_update()
181 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sh_perf_event_update()
202 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop() local
203 int idx = hwc->idx; in sh_pmu_stop()
206 sh_pmu->disable(hwc, idx); in sh_pmu_stop()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start() local
221 int idx = hwc->idx; in sh_pmu_start()
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/linux/arch/sparc/kernel/
H A Dperf_event.c827 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, in… in sparc_pmu_enable_event() argument
845 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, i… in sparc_pmu_disable_event() argument
864 struct hw_perf_event *hwc, int idx) in sparc_perf_event_update() argument
871 prev_raw_count = local64_read(&hwc->prev_count); in sparc_perf_event_update()
874 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sparc_perf_event_update()
882 local64_sub(delta, &hwc->period_left); in sparc_perf_event_update()
888 struct hw_perf_event *hwc, int idx) in sparc_perf_event_set_period() argument
890 s64 left = local64_read(&hwc->period_left); in sparc_perf_event_set_period()
891 s64 period = hwc->sample_period; in sparc_perf_event_set_period()
895 if (unlikely(period != hwc->last_period)) in sparc_perf_event_set_period()
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/linux/drivers/dma/idxd/
H A Dperfmon.c97 struct hw_perf_event *hwc = &event->hw; in perfmon_assign_hw_event() local
99 hwc->idx = idx; in perfmon_assign_hw_event()
100 hwc->config_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
101 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
201 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_read_counter() local
203 int cntr = hwc->idx; in perfmon_pmu_read_counter()
215 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_event_update() local
217 prev_raw_count = local64_read(&hwc->prev_count); in perfmon_pmu_event_update()
220 } while (!local64_try_cmpxchg(&hwc->prev_count, in perfmon_pmu_event_update()
293 struct hw_perf_event *hwc = &event->hw; in perfmon_pmu_event_start() local
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